JPH10340911A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method which can be used commonly with a process for manufacturing a MOS transistor, and restrain increases in a base current, even in the case where an electrode which contains a material having a high reactivity to hydrogen is used. SOLUTION: On the entire surface of a P-type silicon substate 201, polycrystalline silicon films 243 and 208 are formed, so as to cover a base- forming aperture 242 of an NPN transistor forming region 281. An emitter- forming aperture 231 of a lateral PNP transistor-forming region 282, and a polycrystalline silicon film 244 is formed only in a region where a gate electrode is to be formed of a PMOS transistor forming region 283. Boron fluoride ions 245A are implanted into the polycrystalline silicon films 243, 208 and 244. At this point, the impurity 245A is also introduced into the lateral PNP transistor forming region 282 and the PMOS transistor forming region 283 by using the polycrystalline silicon films 243, 208 and 244 as masks, thus forming a P<+> - collector diffusion layer 211, a source diffusion layer 246a, and a drain diffusion layer 246b.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a lateral bipolar transistor structure suitable for being incorporated into a highly integrated and highly integrated semiconductor integrated circuit, and a method of manufacturing the same.

[0002]

2. Description of the Related Art With the recent reduction in size, weight, and power consumption of electronic equipment, high integration and ultrafineness of semiconductor integrated circuits have been remarkably advanced. Under these circumstances, bipolar transistors are widely used for integrated circuits and the like. Generally, an NPN transistor and a PNP transistor are required for a bipolar transistor, and an NPN transistor is often used as a vertical transistor and a PNP transistor is used as a horizontal transistor in order to simplify a manufacturing process. However, the horizontal bipolar transistor is inferior in characteristics such as a low current amplification factor (h _FE ) as compared with the vertical bipolar transistor, and has a problem that the parasitic transistor is easily operated.

FIG. 8 shows a cross-sectional structure of a lateral PNP transistor. This lateral PNP transistor is particularly a double-layer polycrystalline silicon self-aligned transistor (Double P
(OlySelf Align) structure is widely used for integrated circuits incorporating NPN transistors. The PNP transistor of the horizontal, for example, after the N ⁺ -type buried layer 2 is formed in a predetermined region of the P-type silicon substrate 1, the N ⁺
An N-type epitaxial layer 3 is formed on the mold buried layer 2 by growth. After the field insulating film 4 is formed so as to open the active region of the lateral PNP transistor, the P ⁺ -type element isolation layer 5 reaching the P-type silicon substrate 1 and the N ⁺ -type reaching the N ⁺ -type buried layer 2. A sinker layer 6 is formed. The N-type epitaxial layer 3 is surrounded by the P ⁺ -type element isolation layer 5 and the P-type silicon substrate 1
And this region is a base region. An insulating film (silicon oxide film) 7 having openings for emitter diffusion and collector diffusion is formed on the surface of the N-type epitaxial layer 3. This insulating film 7
Polycrystalline silicon films 8 and 9 are formed thereon so as to cover the openings. The polycrystalline silicon films 8 and 9 are formed simultaneously with the NPN transistor. N
P ⁺ -type emitter diffusion layer 10 and P ⁺ -type collector diffusion layer 11 are formed in the base region of type epitaxial layer 3 by impurities diffused from polycrystalline silicon films 8 and 9, respectively. Further, after an interlayer insulating film 12 is formed on the entire surface of the P-type silicon substrate 1, the P ⁺ -type emitter diffusion layer 1 is formed.
Polycrystalline silicon film 8 on P ⁰ , P ⁺ type collector diffusion layer 11
Connection holes (contact holes) are formed in the upper polycrystalline silicon film 9 and the interlayer insulating film 12 on the N ⁺ type sinker layer 6, respectively. An emitter electrode 13, a collector electrode 14, and a base electrode 15 are respectively formed corresponding to these connection holes. The emitter electrode 13 is formed between the P ⁺ -type emitter diffusion layer 10 and the P ⁺ -type
It is formed so as to cover the respective type epitaxial layers 3.

[0004]

In the lateral PNP transistor described above, the collector current is increased from the P ⁺ -type emitter diffusion layer 10 to the P-type transistor through the N-type epitaxial layer 3.
It flows to the ⁺ type collector diffusion layer 11. However, in addition to this, the P ⁺ -type emitter diffusion layer 10 is
Since a parasitic PNP transistor reaching the P ⁺ -type element isolation layer 5 or the P-type silicon substrate 1 through the gate electrode is also formed, the collector current of the parasitic transistor flows in the direction of the arrow shown in FIG. Therefore, due to this leakage current, P
There is a problem that the current amplification factor (h _FE ) of the NP-type transistor is reduced.

In recent years, titanium (Ti), titanium oxynitride (TiON), and aluminum silicide (AlS) have been used in order to improve resistance to electromigration, heat resistance and ohmic contact.
Barrier metals containing titanium and titanium alloys such as i) are widely used as electrode materials. As can be seen from the fact that titanium is used as a hydrogen storage alloy, it has high reactivity with hydrogen. Therefore, during the sintering process after the formation of the aluminum wiring or the alloy (alloy) process for forming the titanium gold (TiAu) on the back surface, the titanium disturbs the diffusion of hydrogen to the surface of the base region, and the base region does not diffuse. Insufficient supply of hydrogen to the upper silicon / silicon oxide film interface. In addition, the dangling bond at the silicon / silicon oxide film interface
The hydrogen bonded to d) is absorbed by the lowermost titanium layer of the emitter electrode 13. As a result, the number of dangling bonds at the interface of the silicon / silicon oxide film with bonds is increased, and the trap level is formed in the forbidden band, thereby increasing the recombination current. That is, there is a problem that the current amplification factor (h _FE ) is further reduced because the base current increases.

Therefore, the same applicant as the present applicant firstly
When a material having high reactivity with hydrogen, such as titanium, is used as an electrode, a silicon nitride film having a low hydrogen diffusion rate is formed between a base region of a lateral PNP transistor and titanium at a lowermost layer of an emitter electrode. LP-SiN) to prevent hydrogen from being absorbed into titanium,
A method for suppressing an increase in dangling bonds was proposed (Japanese Patent Application No. 8-294842). However, in this method, it is necessary to newly add a step of forming a silicon nitride film, and therefore, there is a problem that a manufacturing cost is increased.
In particular, this lateral PNP transistor is connected to a MOS (Meta
(l Oxide Semiconductor) When forming simultaneously with the transistor, it is desirable that it can be formed simultaneously with the MOS structure without adding a new process.

The present invention has been made in view of the above problems, and has as its object to prevent the occurrence of leakage current due to a parasitic transistor and to reduce the base current even when an electrode containing a material highly reactive with hydrogen is used. It is an object of the present invention to provide a semiconductor device and a method for manufacturing the same, which can increase the current amplification rate by suppressing the increase in the current and can be shared with the manufacturing process of the MOS transistor.

[0008]

A semiconductor device according to the present invention comprises a base region of a second conductivity type formed in a semiconductor substrate of a first conductivity type and a base region of a first conductivity type formed in the base region. An emitter region and a first region formed in the base region.
A conductive collector region, an insulating film formed of a material capable of diffusing hydrogen on the surface of the semiconductor substrate and having an opening corresponding to the emitter region, and an insulating film electrically connected to the emitter region and A conductive layer of the first conductivity type covering the surface of the base region between the emitter region and the collector region via the first conductive type, and an electrode wiring layer formed on the conductive layer and containing a metal that captures hydrogen. ing.

A method of manufacturing a semiconductor device according to the present invention includes the steps of forming a base region of a second conductivity type in a semiconductor substrate of a first conductivity type, and an insulating film having an opening for forming an emitter region on the base region. Forming a semiconductor pattern extending from the opening of the insulating film on the semiconductor substrate by a predetermined distance defining a base width on the insulating film; and forming a base region and a semiconductor pattern not covered by the semiconductor pattern. Simultaneously introducing a first conductivity type impurity therein; activating the impurity introduced into the base region to form a collector region; and introducing the first conductivity type impurity into the base region from the semiconductor pattern through the opening. Forming an emitter region by diffusion.

Another method of manufacturing a semiconductor device according to the present invention includes a step of forming a well region and a base region of a second conductivity type in a semiconductor substrate of a first conductivity type, and an insulating film on the well region and the base region. Forming an opening for forming an emitter region in the insulating film; forming a gate semiconductor pattern on the insulating film in the well region; and forming a base width from the opening on the insulating film in the base region. A step of forming a semiconductor pattern extending a predetermined distance, a step of introducing a first conductivity type impurity into the well region and the base region using the gate semiconductor pattern and the semiconductor pattern as a mask, and a step of opening the semiconductor pattern through the opening. Forming an emitter region by diffusing a first conductivity type impurity into the base region.

In the semiconductor device according to the present invention, the surface of the base region is covered with the first conductive type conductive layer via the insulating film capable of diffusing hydrogen, and this conductive layer functions as a hydrogen supply film. Even if an electrode wiring layer having a function of capturing hydrogen is formed, hydrogen diffuses into the surface of the base region, and an increase in base current is suppressed.

In the method for manufacturing a semiconductor device according to the present invention,
An insulating film having an opening for forming an emitter region is formed on the base region, and a semiconductor pattern is formed on the opening and the insulating film. Therefore, in order to prevent capture of hydrogen by a metal contained in the electrode wiring layer. There is no need to add a new process to the system.

According to another method of manufacturing a semiconductor device according to the present invention, a gate semiconductor pattern and a semiconductor pattern are simultaneously formed on a well region and a base region,
Since the first conductivity type impurity is simultaneously introduced into the well region and the base region using the gate pattern and the semiconductor pattern as a mask, the manufacturing process is shared with the semiconductor device (MOS transistor) having the well region.

[0014]

Embodiments of the present invention will be described below in detail with reference to the drawings.

[First Embodiment] FIG. 1 shows a first embodiment of the present invention.
9 shows a cross-sectional structure of a lateral PNP transistor according to the embodiment. In this lateral PNP transistor, for example, after an N ⁺ type buried layer 102 is formed in a predetermined region of a P type silicon substrate 101, an N type epitaxial layer 103 is grown on the N ⁺ type buried layer 102. Is formed. After a field oxide film 104 is formed so as to open the active region of the lateral PNP transistor, a P ⁺ -type element isolation layer 105 reaching the P-type silicon substrate 101 and an N ⁺ -type reaching the N ⁺ -type buried layer 102. A sinker layer 106 is formed. The N-type epitaxial layer 103 is separated from the P-type silicon substrate 101 by being surrounded by the P ⁺ -type element isolation layer 105, and this region becomes a base region.

On the surface of the N-type epitaxial layer 103, an insulating film (silicon oxide film) 107 having an opening 131 for an emitter diffusion layer is formed. This insulating film 107
The polycrystalline silicon film 10 is formed thereon so as to cover the opening 131.
8 are formed. In the base region of N-type epitaxial layer 103, P ⁺ -type emitter diffusion layer 110 and P ⁺ -type collector diffusion layer 111 are formed by impurities diffused from polycrystalline silicon film. The P ⁺ -type collector diffusion layer 111 is deeper than the P ⁺ -type emitter diffusion layer 110.

After the interlayer insulating film 112 is formed on the entire surface of the P-type silicon substrate 101, the polycrystalline silicon film 10 is formed.
8, connection holes (contact holes) are respectively formed in the interlayer insulating film 112 on the P ⁺ type collector diffusion layer 111 and the N ⁺ type sinker layer 106. An emitter electrode 113, a collector electrode 114, and a base electrode 115 made of titanium (Ti) / titanium oxynitride (TiON) / aluminum silicide (AlSi) are formed corresponding to these connection holes.

As described above, in the present embodiment, the P ⁺ -type collector diffusion layer 111 is formed deeper than the P ⁺ -type emitter diffusion layer 110, so that the collector current flows from the P ⁺ -type emitter diffusion layer 110 to the N-type epitaxial diffusion layer. P ⁺ -type element isolation layer 105 or P-type silicon substrate 1 via layer 103
01 does not flow through the parasitic PNP transistor, and generation of leakage current is suppressed. Therefore, the current amplification factor (h) of the lateral PNP transistor due to this leakage current
_FE ) can be prevented from lowering. Also, the surface of the base region is protected (shielded) by the polycrystalline silicon film 108.
Since this functions as a hydrogen supply film, an increase in dangling bonds is suppressed even though the emitter electrode 113 and the collector electrode 114 contain titanium (Ti), and the current amplification factor (h _FE ) , A lateral PNP transistor having a high density can be formed. Further, the cell size of the lateral PNP transistor can be reduced as compared with the conventional structure in which the base region surface is protected by the metal electrode.

[Second Embodiment] FIGS. 2 to 7 show a method of manufacturing a lateral PNP transistor according to a second embodiment of the present invention in the order of steps. In the present embodiment, a lateral PNP transistor is manufactured simultaneously with an NPN transistor and a PMOS transistor.

First, as shown in FIG. 2, an NPN transistor forming region 281 on a P-type silicon substrate 201,
Lateral PNP transistor forming region 282 and PM
The N ⁺ -type buried layer 2 is formed in the OS-type transistor formation region 283 by vapor-phase diffusion, for example, antimony oxide (Sb) using antimony oxide (Sb ₂ O ₃ ) at 1200 ° C.
02 are respectively formed. Then, the N ⁺ type buried layer 2
An N-type epitaxial layer 203 of 1 to 5 Ωcm and 0.7 to 2.0 μm is formed on the substrate 02. Subsequently, the entire surface of the P-type silicon substrate 201 is, for example, 50 nm thick by thermal oxidation.
After forming a silicon oxide (SiO ₂ ) film having a thickness of m, a silicon nitride (Si ₃ N ₄ ) film having a thickness of 100 nm is formed on the silicon oxide film by, for example, a CVD method. Next, an NPN transistor formation region 28 is formed on the silicon nitride film.
1. forming a resist pattern having an opening in each of the active regions of the lateral PNP transistor forming region 282 and the PMOS transistor forming region 283;
Using this resist pattern as a mask, the silicon nitride film and the silicon oxide film are sequentially etched. Then, for example, a field oxide film 2 having a thickness of 600 to 1500 nm is formed by steam oxidation at 1000 to 1050 ° C. for 3 to 8 hours.
04 is formed. Subsequently, after removing the silicon nitride film, for example, phosphorus (P) is ion-implanted into the entire surface of the P-type silicon substrate 201 at about 70 keV and 5E15 atms / cm ² , and thereafter, diffusion is performed at 1000 ° C. for 30 minutes. N
An N ⁺ -type sinker layer 206 is formed in the collector lead-out portion of the PN transistor formation region 281 and the base region lead-out portion of the lateral PNP transistor formation region 282. Next, for example, boron (B) is applied to the entire surface of the P-type silicon substrate 201 at 300 to 720 keV and 1E13 to 1E1.
The P ⁺ -type element isolation layer 205 is formed by ion implantation at about 4 atms / cm ² . Thereafter, the silicon oxide film is removed, and thermal oxidation is performed at 850 to 900 ° C., for example, to thereby form a gate oxide film (insulating film) 241 having a thickness of 15 to 50 nm.
To form

Next, as shown in FIG. 3, the gate oxide film 241 is dry-etched to form an opening 242 for forming the base of the NPN transistor forming region 281 and an emitter for forming the lateral PNP transistor forming region 282. An opening 231 is formed. Subsequently, for example, CVD (Chemical Vapor Dep.) Is applied on the entire surface of the P-type silicon substrate 201.
osition) method to form a polycrystalline silicon layer of 150 to 300 nm. Next, this polycrystalline silicon layer is formed, for example, by Cl ₂ (chlorine) / CH ₂ F ₂ (methane difluoride) / S
It is selectively removed by dry etching using an F ₆ (sulfur hexafluoride) gas system. As a result, the polycrystalline silicon film 243 covers the base forming opening 242 of the NPN transistor forming region 281 and the emitter forming opening 231 of the lateral PNP transistor forming region 282.
A polycrystalline silicon film 208 covers PMO
The polysilicon film 244 is left only in the region where the gate electrode is to be formed in the S-type transistor formation region 283.

Subsequently, as shown in FIG. 4, the N ⁺ type sinker layer 206 is covered and the polycrystalline silicon film 243 of the NPN type transistor formation region 281, the active region of the lateral PNP type transistor formation region 282 and the PMO
A resist film 245 having an opening corresponding to the active region of the S-type transistor formation region 283 is formed. Using the resist film 245 as a mask, the P-type silicon substrate 20
1 On the entire surface, for example, boron fluoride (BF ₂ ) is
Impurity 245A is implanted into the polycrystalline silicon films 243, 208, 244 by ion implantation of about 1E16 atoms / cm ^2.
Is introduced. At this time, the polycrystalline silicon films 243, 20
Using impurities 8 and 244 as masks, impurities 245 are also present in N-type epitaxial layer 203 in lateral PNP transistor formation region 282 and PMOS transistor formation region 283.
A is introduced, whereby the P ⁺ type collector diffusion layer 21 is formed.
1. A source diffusion layer 246a and a drain diffusion layer 246b are respectively formed. Note that the energy of the ion implantation penetrates through the gate oxide film 241 under the polycrystalline silicon films 243, 208, and 244 and the N-type epitaxial layer 20.
3 and the polycrystalline silicon films 243, 208, 2
The gate oxide film 24 below the region where no 44 is formed
The thickness of the gate oxide film 241 and the thicknesses of the polycrystalline silicon films 243, 208, and 244 are determined so as to be sufficiently below 1. For example, if the thickness of the gate oxide film 241 is 30 n
m and the thickness of the polycrystalline silicon films 243, 208 and 244 are respectively 200 nm, the ion implantation energy is 70 keV. After the ion implantation, the resist film 245 is removed.

Next, as shown in FIG. 5, the entire surface of the P-type silicon substrate 201 has a thickness of 300
An m-th silicon oxide film (SiO ₂ ) 260 is formed. Subsequently, the silicon oxide film 260 and the polycrystalline silicon film 243 in the NPN transistor formation region 281 are sequentially etched to form an emitter formation opening 247 where the P-type silicon substrate 201 is exposed. For example, 30 to 5 boron fluoride (BF ₂ ) is formed in the opening 247 for forming the emitter.
0 keV, ion implantation of about 1E13 to 1E14 atms / cm ² to introduce a P-type impurity
Intrinsic base region 248 in type transistor formation region 281
To form

Subsequently, a 600-nm-thick silicon oxide film (SiO ₂ ) is formed on the entire surface of the P-type silicon substrate 201 by, for example, the CVD method.
Anneal for 0 minutes. Thereafter, the entire surface of the silicon oxide film is etched back to form a side wall (side wall) 249 for separating the emitter diffusion layer and the base region of the NPN transistor formation region 281 as shown in FIG. By the annealing at this time, the P-type impurity diffuses from the polycrystalline silicon film 243 in the NPN transistor formation region 281 to the N-type epitaxial layer 203 to form the graft base region 250, and the activated intrinsic base region 248 and Connected. Further, P-type impurities are also diffused from the polycrystalline silicon film 208 in the lateral PNP transistor formation region 282 to the N-type epitaxial layer 203 to form a P ⁺ -type emitter diffusion layer 210 shallower than the P ⁺ -type collector diffusion layer 211. Is done. Further, by this annealing, the source diffusion layer 246a and the drain diffusion layer 246b of the PMOS transistor formation region 283 are activated.

Next, as shown in FIG. 7, a film thickness of 150
A polycrystalline silicon film 252 of nm is formed. For example, arsenic (As) is applied to this polycrystalline silicon film 252 for 30 to 70 k.
After ion implantation at about eV, 1E15 to 1E16 atms / cm ² , annealing is performed at 1000 to 1100 ° C. for 5 to 30 seconds to form a P ⁺ type emitter diffusion layer 251 in the NPN transistor forming region 281. Thereafter, dry etching is performed on the polycrystalline silicon film 252 to leave the polycrystalline silicon film 252 only in the region where the emitter electrode is to be formed in the NPN transistor forming region 281.

Subsequently, NPN is performed using lithography technology.
Polysilicon film 24 in type transistor formation region 281
3 and the N ⁺ type sinker layer 206, the polycrystalline silicon film 208 of the lateral PNP transistor formation region 282,
P ⁺ type collector diffusion layer 211 and N ⁺ type sinker layer 2
06 and the PMOS transistor forming region 283
A connection hole (contact hole) is formed on polycrystalline silicon film 244, source diffusion layer 246a and drain diffusion layer 246b. Thereafter, the polycrystalline silicon film 243 and the N ^{+ in} the NPN transistor formation region 281 are formed.
A base electrode 254 and a collector electrode 255 are formed in the connection holes opened on the mold sinker layer 206, and an emitter electrode 253 is formed on the polycrystalline silicon film 252, respectively. Further, the P ^{+ of the} lateral PNP transistor formation region 282
A collector electrode 213, an emitter electrode 212, and a base electrode 214 are formed in connection holes opened on the type collector diffusion layer 211, the polycrystalline silicon film 208, and the N ⁺ type sinker layer 206, respectively. Further, a source electrode 256 and a drain electrode 257 are formed in connection holes opened on the source diffusion layer 246a and the drain diffusion layer 246b in the PMOS transistor formation region 283. The base electrode 254, 214, the emitter electrode 253, 212, the collector electrode 255, 213, the source electrode 256, and the drain electrode 257 are all Ti /
The electrode is made of TiON / AlSi. Thus, an NPN transistor 291, a lateral PNP transistor 292, and a PMOS transistor 293 are formed.

As described above, also in this embodiment, the horizontal PN
P ⁺ -type collector diffusion layer 211 of P-type transistor 292
Is formed deeper than the P ⁺ -type emitter diffusion layer 210, the leakage current flowing through the parasitic PNP transistor is suppressed, and a decrease in the current amplification factor (h _FE ) can be prevented. Further, since the surface of the base region is protected (shielded) by the polycrystalline silicon film 208, the emitter electrode 2
12 and the collector electrode 213 contain titanium (Ti), an increase in dangling bonds is suppressed, and a lateral PNP having a high current amplification factor (h _FE ).
The type transistor 292 can be formed.

Further, in the present embodiment, the width of the base region of the lateral PNP transistor 292 is limited by the amount A of the emitter forming opening 231 and the polycrystalline silicon film 208 and the gate oxide film 241 (see FIG. 7). Is determined in a self-aligned manner. Therefore, the total distance of the overlying amount of the polycrystalline silicon film on the P ⁺ -type emitter diffusion layer, the overlying amount of the polycrystalline silicon film on the P ⁺ -type collector diffusion layer, and the separation amount between these polycrystalline silicon films is Compared with the required conventional structure, the width of the base region can be reduced, and the current amplification factor (h _FE ) can be improved.

In this embodiment, the polycrystalline silicon film 208 of the lateral PNP transistor 292 is
Film 243 of PMOS transistor 291 and polysilicon film 24 of PMOS transistor 293
4 and at the same time, the introduction of impurities into the polycrystalline silicon film 208 and the P ⁺ -type collector diffusion layer 211 of the lateral PNP transistor 292 is performed by the NPN transistor 2.
91, the polysilicon film 244 of the PMOS transistor 293, the source diffusion layer 24
Since the process is performed simultaneously with the introduction of the impurity into the drain diffusion layer 6a and the drain diffusion layer 246b, the manufacturing process can be shared and the manufacturing cost can be reduced.

Although the present invention has been described with reference to the embodiment, the present invention is not limited to the above embodiment, and can be variously modified. For example, in the above embodiment, the lateral PNP transistor is manufactured simultaneously with the NPN transistor and the PMOS transistor. However, the present invention can be applied to the process of manufacturing only the vertical NPN transistor at the same time. .

[0031]

As described above, according to the semiconductor device of the present invention, the surface of the base region is covered with the conductive layer of the first conductivity type via the insulating film capable of diffusing hydrogen. Therefore, since this conductor layer functions as a hydrogen supply film, even if an electrode wiring layer having a function of capturing hydrogen is formed, hydrogen diffuses into the surface of the base region, and an increase in base current is suppressed, and current amplification is suppressed. The effect is that the rate can be increased. Furthermore, since the surface of the base region is covered with the conductive layer of the first conductivity type, the size of the semiconductor device can be reduced as compared with the conventional structure in which the surface of the base region is protected by the electrode wiring layer. .

According to the method of manufacturing a semiconductor device of the present invention, an insulating film having an opening for forming an emitter region is formed on a base region, and a plurality of insulating films are formed on the opening and the insulating film. Since a semiconductor pattern of crystalline silicon is formed, there is no need to add a new process to prevent the capture of hydrogen by the metal contained in the electrode wiring layer, and the device can be easily manufactured by a conventional process. .

In particular, according to the method of manufacturing a semiconductor device of the present invention, a gate semiconductor pattern and a semiconductor pattern are simultaneously formed on the well region and the base region, and the well region is formed using the gate pattern and the semiconductor pattern as a mask. In addition, since the first conductivity type impurity is simultaneously introduced into the base region and the base region, the manufacturing process can be shared with the semiconductor device (MOS transistor) having the well region, and the manufacturing cost can be reduced. To play.

[Brief description of the drawings]

FIG. 1 shows a horizontal PNP according to a first embodiment of the present invention.
FIG. 4 is a cross-sectional view illustrating a structure of a type transistor.

FIG. 2 shows a horizontal PNP according to a second embodiment of the present invention.
Transistor, NPN transistor and PMOS
It is sectional drawing showing the manufacturing process of a type transistor.

FIG. 3 is a sectional view illustrating a step following FIG. 2;

FIG. 4 is a sectional view illustrating a step following FIG. 3;

FIG. 5 is a cross-sectional view illustrating a process following the process in FIG.

FIG. 6 is a sectional view illustrating a step following FIG. 5;

FIG. 7 is a sectional view illustrating a step following FIG. 6;

FIG. 8 is a cross-sectional view illustrating a structure of a conventional lateral PNP transistor.

[Explanation of symbols]

101: silicon substrate, 102: N ⁺ type buried layer, 1
03 ... N type epitaxial layer, 104 ... Field oxide film, 105 ... P ⁺ type isolation layer, 106 ... N ⁺ type sinker layer, 107 ... Insulating film, 108 ... Polycrystalline silicon film, 1
10 ... P ⁺ type emitter diffusion layer (emitter region), 111
... P ⁺ -type collector diffusion layer (collector region), 112 ... interlayer insulating film, 113 ... emitter electrode, 114 ... collector electrode, 115 ... base electrode, 131 ... opening

Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 27/082 29/78 21/336

Claims (8)

[Claims] A first conductive type base region formed in a first conductive type semiconductor substrate; a first conductive type collector region formed in the base region; and a second conductive type collector region formed in the base region. A first conductivity type emitter region, an insulating film formed of a material capable of diffusing hydrogen on the surface of the semiconductor substrate and having an opening corresponding to the emitter region, and electrically connected to the emitter region A conductive layer of the first conductivity type covering the surface of the base region between the emitter region and the collector region via the insulating film; and a metal formed on the conductive layer and capturing hydrogen. A semiconductor device comprising: an electrode wiring layer including: 2. The semiconductor device according to claim 1, wherein said electrode wiring layer is formed of a barrier metal containing titanium and a titanium alloy. 3. The semiconductor device according to claim 2, wherein said conductor layer is a polycrystalline silicon film. 4. The semiconductor device according to claim 1, wherein said collector region is formed deeper than said emitter region. 5. A step of forming a base region of a second conductivity type in a semiconductor substrate of a first conductivity type; a step of forming an insulating film having an opening for forming an emitter region on the base region; Forming a semiconductor pattern extending a predetermined distance defining a base width on the insulating film from the opening of the insulating film on the semiconductor substrate; and forming a first region in the base region and the semiconductor pattern not covered by the semiconductor pattern. Simultaneously introducing a conductivity type impurity, activating the impurity introduced into the base region to form a collector region, and diffusing a first conductivity type impurity from the semiconductor pattern into the base region through the opening. Forming an emitter region by performing the method. 6. A step of forming a second conductivity type well region and a base region in a first conductivity type semiconductor substrate; a step of forming an insulating film on the well region and the base region; Forming an opening for forming an emitter region in the film; forming a gate semiconductor pattern on the insulating film in the well region; and defining a base width from the opening on the insulating film in the base region. Forming an extending semiconductor pattern; and forming a first semiconductor layer in the well region and the base region using the gate semiconductor pattern and the semiconductor pattern as a mask.
A semiconductor device comprising: a step of introducing a conductive impurity; and a step of forming an emitter region by diffusing a first conductive impurity from the semiconductor pattern into the base region through the opening. Production method. 7. The method according to claim 6, wherein the gate semiconductor pattern and the semiconductor pattern are polycrystalline silicon films. 8. A first region in the well region and the base region.
7. The method according to claim 6, wherein the impurity is introduced into the gate semiconductor pattern only in the step of introducing the conductive impurity.
The manufacturing method of the semiconductor device described in the above.