JPH10340594A - Semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a high speed operation by confining the operation one cycle time only within a precharge on the data line of small load and a read-out outputted on the bit line by means of a precharge circuit onto each of the bit lines and selecting column switches, here provided that the bit lines of two pieces each are prepared on every row and are connected with the memory cells in the columnar direction to each other. SOLUTION: The first bit lines Bαi are connected with the memory cells of odd numbered columns A11-Amn, and the second bit lines Bβi are connected with the memory cells of even numbered columns A12 to Amn-1. The first precharge circuit 26 precharges onto the first bit lines Bdi, and the second precharge circuit 27 precharges onto the second bit lines, and the column switch 24 selects the first/second bit lines. Making use of the characteristics of sequential access, while the data of j-1 column is being read out in the row direction, the other bit lines are precharged beforehand to output the data of each of the rows of the j column.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device such as a ROM, and more particularly, to a semiconductor memory device in which power consumption is reduced by controlling the operation of a memory.

[0002]

2. Description of the Related Art In general, in a data processing system such as an information processing apparatus which handles a huge amount of data, a large-capacity and low-cost semiconductor memory is used to store a huge amount of data.

A ROM (read only memory) is a read-only semiconductor memory, and is used to store fixed information such as microprograms and constants whose contents do not change. The ROM includes a mask ROM in which information is previously written in a manufacturing process and a PROM (programmable ROM) in which a user can freely write information.

FIG. 11 is a diagram showing a basic configuration of a semiconductor memory device in a conventional ROM.

In FIG. 11, a semiconductor memory device 10 comprises:
A memory cell array 11 composed of ROM cells A11 to Amn (m and n are both positive integers), an address generation circuit 12, a word line address decoder 13, a bit line address decoder 14, a column switch 15, a bit line precharge circuit 16, It includes a data line precharge circuit 17 and a sense amplifier 18.

Reference numeral 19 is a data line, B1 to Bm are bit lines, W1 to Wn are word lines, BP is a bit line precharge signal, DP is a data line precharge signal, and C1 to Cm are column selection signals.

FIG. 12 is a timing chart showing a series of operations of the semiconductor memory device 10.

In FIG. 12, in a precharge period, a bit line precharge signal BP and a data line precharge signal DP are turned ON (when high level), and the bit lines B1 to Bm and the data line 19 are precharged. .

Next, in the read period, for example, when the address (i, j) is selected by the address generation circuit 12, the word line Wj is turned on by the word line address decoder 13 to open the column switch 15, and the ROM
Data of cells A11 to Amn (m and n are both positive integers) are output to bit lines B1 to Bm. At the same time, the column selection signal Ci is turned ON, the data Dij of the ROM cell Aij is output through the data line 19 and the sense amplifier 18, and one cycle is completed.

[0010]

However, in the operation of such a conventional semiconductor memory device, the precharging of the bit line and the reading of the data, that is, the discharging of the bit line are performed every cycle. Generally, since a large number of memory cells are connected to the bit line, the load is large.

Therefore, in the ROM, there is a problem that the time required for precharging the bit line and reading (discharging) data to the bit line greatly depends on the operating speed limit.

An object of the present invention is to provide a semiconductor memory device capable of achieving a significantly high-speed operation by performing only one cycle of precharging of a data line with a small load and reading of data.

[0013]

A semiconductor memory device according to the present invention has n word lines for selecting a column, a word line decoder for selecting one of the n word lines, and a row for selecting a row. M column switches, m bit lines for transferring data written to the storage elements in the selected column, m × n storage elements connected to the word lines and bit lines, and bit lines And at least two bit lines are prepared for each row, the first bit line is connected to the odd-numbered column storage element, and the second bit line is connected to the second column. The bit lines are connected to the storage elements in the even columns, and a first bit line precharge circuit for precharging the first bit lines and a second bit line precharge circuit are provided.
, A second bit line precharge circuit for precharging the bit line and a column switch for selecting each of the first bit line and the second bit line.

In the semiconductor memory device according to the present invention, when addresses are sequentially selected in the row direction, the first bit lines are used to sequentially output the data of the storage elements in the columns selected by the word lines to the outside. 1 between the first process and the first process, the second bit line precharge circuit is used.
And a second process of reading out data of the storage element selected by the word line of the next column to a second bit line after precharging the bit line of the next column. May be repeatedly operated.

In the semiconductor memory device according to the present invention, when addresses are sequentially selected in the column direction, the data of the storage element connected to the word line and the first bit line selected by the column switch are output to the outside. A first process and a second process for precharging a second bit line using a second bit line precharge circuit between the first process and the first process are provided. The processing of step 2 may be repeatedly performed.

In the semiconductor memory device according to the present invention, a first bit line precharge circuit for precharging an odd-numbered row of a first bit line and a second bit line for precharging an even-numbered row of the first bit line are provided. Bit line precharge circuit, a third bit line precharge circuit for precharging odd-numbered rows of the second bit line, and a fourth bit line precharge circuit for precharging even-numbered rows of the second bit line When a charge circuit is provided and addresses are sequentially selected in the column direction,
Precharging adjacent first bit lines and second bit lines using different bit line precharge circuits,
The bit line connected to the last addressed storage element in the column and the bit line connected to the first addressed storage element in the next column are the same first bit line or second bit. Even if it is a line, it may be made operable.

In the semiconductor memory device according to the present invention, a bit line precharge circuit for precharging a first bit line and a second bit line in each row is separately provided for each bit line, and a column is provided. When addresses are sequentially selected in the direction, only the bit line to be used next may be precharged.

In the semiconductor memory device according to the present invention, n word lines for selecting a column and one of n word lines are selected.
A word line decoder for selecting a book, m column switches for selecting a row, m bit lines for transferring data written in a storage element in a selected column, and connection to a word line and a bit line And a bit line precharge circuit for precharging the bit lines, at least two word lines are prepared for each column, and the first word line is provided in the first half. And the second word line is connected to the storage elements connected to the bit lines of the latter row, and the second word line is connected to the storage elements connected to the bit lines of the second row. , A second word line decoder for selecting one of the n second word lines, and a first word line for precharging the bit lines of the first half row. Bit line precharge circuit and The bit lines of the second half of the line constituting a second bit line precharge circuit for precharging.

In the semiconductor memory device according to the present invention, when addresses are sequentially selected in the row direction, a first memory cell sequentially outputs the data of the memory elements in the first half row of the column selected by the first word line to the outside. After the process and the first process are performed, the bit lines in the latter half row connected to the second word line are precharged, and then, in the column whose address is selected in the first process, After the second process for outputting data of the storage element connected to the second word line to the bit line in the latter half row and the second process, the second process is performed.
A third process of sequentially outputting the data output to the bit lines in the process of (1) to the outside, and, while the third process is being performed, of the first half of the row connected to the first word line. After precharging the bit line, the data of the storage element connected to the first word line is output to the bit line of the first half row in the next column whose address is selected in the second processing. A fourth process may be provided, and the first to fourth processes may be repeatedly performed.

In the semiconductor memory device according to the present invention, two bit lines are prepared for each row, the first bit line is connected to the odd-numbered column storage element, and the second bit line is connected to the even-numbered column. A first bit line precharge circuit connected to the storage element and precharging the first bit line; a second bit line precharge circuit for precharging the second bit line; And a column switch for selecting each of the second bit lines. While the address is selected and the data of the storage element is read and output to the outside, all the data not connected to the storage element selected at this time are output. A first process of precharging the bit lines of
After the first process is completed, an address of any of the storage elements connected to the bit line precharged in the first process is selected, and the data of the selected storage element is read and output to the outside. The second process may be performed, and the first process and the second process may be repeatedly performed.

In the semiconductor memory device according to the present invention, the storage element may be a ROM cell.

[0022]

FIG. 1 is a configuration diagram of a semiconductor memory device according to a first embodiment of the present invention. The semiconductor memory device shown in FIG. 1 is an example in which the present invention is applied to a mask ROM as a memory cell array. In the description of the semiconductor memory device according to the present embodiment, the same components as those of the semiconductor memory device shown in FIG. 11 are denoted by the same reference numerals.

In FIG. 1, the semiconductor memory device 20 has
M × n R consisting of n rows and n (m and n are integers) columns
A memory cell array 21 composed of OM cells A11 to Amn, an address generation circuit 22, a word line address decoder 13,
Bit line address decoder 23, column switch 24,
It includes a bit line precharge circuit 25, a data line precharge circuit 17, and a sense amplifier 18.

Reference numeral 19 denotes a data line, and Bαi (i is 1 to
m is an arbitrary integer), a first bit line of two bit lines provided in each row, Bβi is a second bit line of two bit lines provided in each row, and W1 to Wn are words. line,
BPα is a bit line precharge signal for the first bit line Bαi, BPβ is a bit line precharge signal for the second bit line Bβi, DP is a data line precharge signal, Cα1
To Cαm are column selection signals of the first bit line Bαi;
β1 to Cβm are column selection signals for the second bit line Bβi.

The bit line precharge circuit 25 comprises a PMOS transistor and a first bit line precharge circuit 26 for precharging the first bit line Bαi, as shown by the broken line in FIG. 1, and a PMOS transistor. And a second bit line precharge circuit 27 for precharging the second bit line Bβi.

That is, the semiconductor memory device 20 includes n word lines Wn for selecting a column (word line), a word line address decoder 13 for selecting one of the n word lines Wn, and a word line Wn. M × n ROM cells A11 to Amn (storage elements) connected to Wn and bit lines Bαi, Bβi
, And m bit lines for transferring data written in the storage elements of the selected column are prepared two by two in each row, and the first bit line Bαi is provided in the odd column. ROM cell Aix (x is an odd number from 1 to n)
And the second bit line Bβ
i is a first bit line precharge circuit 26 connected to a ROM cell represented by ROM cells Aiy (y is an even number from 1 to n) in an even column to precharge the first bit line Bαi; , A second bit line precharge circuit 27 for precharging the second bit line Bβi, and a column switch 24 for selecting each of the first bit line Bαi and the second bit line Bβi.

Thus, ROΜ according to the present embodiment is:
m × n memory cells A11 to M × n of m rows and n columns
And two bit lines (Bαi, Bβi) in each row of the memory cells A11 to Amn, which are connected to every other cell in the column direction. That is, B
.alpha.i is the cell in the first, third, fifth,.
6, ... are connected to cells in the column. The bit line precharge signals BPα and BPβ and the column selection signal Cα
1 to Cαm and Cβ1 to Cβm are separately provided for the bit lines Bαi and Bβi, respectively.

The operation of the semiconductor memory device 20 configured as described above will be described below.

FIG. 2 is a timing chart showing the operation of the semiconductor memory device 20. The ROM shown in FIG.
11, A21,..., Am1, A12, A22,..., Am2,.

In this case, the word line is continuously turned on m times until the access to the memory cell in the column is completed. Therefore, by preparing two bit lines in each row and connecting them to every other cell in the column direction, the j-th column is read in advance while the data in the (j-1) -th column is being read. Are precharged, and data of the memory cell is read out to all bit lines in the first to m-th rows.

First, the bit line precharge signal B is set in the data read period (the period 120 in FIG. 2) of the j-1st column.
When Pβ is turned ON (high level), the bit line B
β1 to Bβm are precharged.

Next, after the bit line precharge signal BPβ is turned off (low level), the word line Wj is turned on.
And the data of all the rows in the j-th column are bit lines Bβ1 to
Output to Bβm. When the data reading of the (j-1) -th column is completed and the data reading period of the j-th column is reached (period 121 in FIG. 2), the data line precharge signal DP is turned on and the data line is precharged. , The column selection signal Cβ1 is turned on and the data previously output to the bit line Bβ1 is changed to the data line 19 and the sense amplifier 18.
Output to the outside through

Thereafter, rows are selected in order, and data is read out.

During the data reading period of the j-th column, the next j
In preparation for the data reading of the (+1) th column, the bit line precharge signal BPα is turned on to precharge Bα1 to Bαm, and then the word line Wj + 1 of the (j + 1) th column is turned on.
And the same operation is repeated thereafter.

FIG. 3 is a timing chart showing the operation of the semiconductor memory device 20. The ROM shown in FIG.
11, A12, ..., A1n, A21, A22, ..., A2m, ..., Amn
7 is a timing chart showing the operation when the data is sequentially accessed in the column direction as shown in FIG.

For example, while the data of Ai (j-1) is being read (see 141 in FIG. 3), the bit line precharge signal BPβ is turned on, and the bit lines Bβ1 to Bβm are precharged in advance. When the reading of the data of Ai (j-1) is completed, BPβ is turned off, the data line precharge signal DP is turned on and the data line 19 is precharged, and then the word line Wj and the column selection signal Cβi
Is turned ON, and the data of Aij is read.

During the reading period of Aij, the next Ai
In preparation for reading (j + 1), BPα and DP are turned ON, and the bit lines Bα1 to Bαm are precharged.

Hereinafter, the same operation is repeated.

As described above, the semiconductor memory device 20 according to the first embodiment includes the word line Wn and the bit line B
m × n ROM cells A11-A connected to αi, Bβi
mn and a memory cell array 21 of
Two m-bit lines for transferring data written in the OM cells A11 to Amn are prepared in each row, and the first bit line Bαi is connected to the odd-numbered column ROM cells A11 to Amn. The second bit line Bβi is connected to the ROM cell A12 of the even column.
, And a first bit line precharge circuit 26 for precharging the first bit line Bαi, a second bit line precharge circuit 27 for precharging the second bit line Bβi, A column switch 24 for selecting each of the first bit line Bαi and the second bit line Bβi
By using the feature of sequential access, two bit lines are prepared for each row and alternately connected to the memory cells in the column direction.
In the case of sequential access in the row direction as shown in (1), while the data in the (j-1) -th column is being read, the other bit line is precharged in advance, and the data in each row in the j-th column is stored in the bit line. , So that the precharging of the bit line with a large load and the data reading operation, which were required each time, are not required, and the operation performed during one cycle is performed by precharging the bit line with a small load and bit Only the data that has been output up to the line is read out, and a significant high-speed operation becomes possible.

When the data is sequentially accessed in the column direction as shown in FIG. 3, while the data of Ai (j-1) is being read using the bit line Bαi, the connection to the j-th column is performed in advance. By precharging the stored bit line Bβi, the precharging of the bit line that was required every time becomes unnecessary, and the operation required during one cycle is performed by precharging the data line and data from the memory cell. , It is possible to perform a significantly high-speed operation.

Therefore, high-speed memory access can be performed, which is suitable for application to an information processing device such as a data processing device which requires high speed.

FIG. 4 is a configuration diagram of a semiconductor memory device according to the second embodiment of the present invention. In the description of the semiconductor memory device according to the present embodiment, the same components as those of the semiconductor memory device shown in FIG.

In FIG. 4, the semiconductor memory device 30 has
M × n ROM cells A11 to A, each having two rows and n columns
mn memory cell array 21 and address generation circuit 3
1, a word line address decoder 13, a bit line address decoder 23, a column switch 24, a bit line precharge circuit 32, a data line precharge circuit 17, and a sense amplifier 18.

19 is a data line, and Bαi is 2 in each row.
A first bit line among the bit lines provided one by one, Bβi
Is a second bit line of two bit lines provided in each row, W1 to Wn are word lines, BPαA is a first bit line B
bit line precharge signal of the odd-numbered row of αi, BPαB
Is a bit line precharge signal of an even line of the first bit line Bαi, BPβA is a bit line precharge signal of an odd line of the second bit line Bβi, and BPβB is an even line of the second bit line Bβi. Bit line precharge signal, DP
Is a data line precharge signal, Cα1 to Cαm are column selection signals for the first bit line Bαi, and Cβ1 to Cβm are column selection signals for the second bit line Bβi.

The bit line precharge circuit 32 includes a first bit line precharge circuit 33 for precharging an odd-numbered row of the first bit line Bαi, as shown by a broken line in FIG. A first bit line precharge circuit 34 for precharging an even-numbered row of the line Bαi, a second bit line precharge circuit 35 for precharging an odd-numbered row of the second bit line Bβi, and a second bit Line Bβi
And a second bit line precharge circuit 36 for precharging the even-numbered row of.

Thus, ROΜ according to the present embodiment is:
m × n memory cells A11 to M × n of m rows and n columns
Amn, and there are a total of four bit line precharge signals, two on each of the α and β sides.
Bit lines on the α side of the rows 5, 7,..., For example, Bα1, Bα3
BPαB precharges the bit lines on the α side in rows 2, 4, 6, 8,..., For example, Bα2, Bα4. Similarly,
BPβA is a bit line on the β side in rows 1, 3, 5, 7,.
For example, Bβ1, Bβ3, BPβB are 2, 4, 6, 8, ...
The bit lines on the β side of the row, for example, Bβ2 and Bβ4 are precharged.

Hereinafter, the operation of the semiconductor memory device 30 configured as described above will be described.

FIG. 5 is a timing chart showing the operation of the semiconductor memory device 30. The ROM shown in FIG.
11, A12, ..., A1n, A21, A22, ..., A2m, ..., Amn
7 is a timing chart showing the operation when the data is sequentially accessed in the column direction as shown in FIG.

In the precharge operation of the semiconductor memory device 20 according to the first embodiment, when the precharge signal on the α side (BPα in FIG. 2) is turned on, all the bit lines on the α side are precharged. When the precharge signal on the β side (BPβ in FIG. 2) is turned on, all bit lines on the β side are precharged.
When BPαA in FIG. 4 is turned on, Bα1, Bα3, Bα5,
…, When BPαB is turned on, Bα2, Bα4, Bα6,
Are precharged respectively. BPβA is O
When it becomes N, Bβ1, Bβ3, Bβ5,.
When N, Bβ2, Bβ4, Bβ6,... Are precharged, respectively. Other operations are the same as those in the first embodiment.

As described above, the semiconductor memory device 30 according to the second embodiment includes the bit line precharge circuit 3
2, a first bit line precharge circuit 33 for precharging an odd-numbered row of the first bit line Bαi, and a first bit line precharge circuit for precharging an even-numbered row of the first bit line Bαi 34, a second bit line precharge circuit 35 for precharging odd-numbered rows of the second bit line Bβi, and a second bit line precharge circuit for precharging even-numbered rows of the second bit line Bβi 36, and when sequentially selecting addresses in the column direction, the adjacent first bit line and second bit line are precharged using different bit line precharge circuits. In addition to the effects of the first embodiment, adjacent bit lines are always precharged with different precharge signals, so that the first column and the nth column are in contact with the same side bit line. Even if they are, it becomes operable.

For example, in the case of FIG. 4, the bit line on the α side is 1
The column and the n-th column are connected to the same side bit line,
In this embodiment, the bit line precharge signal BPαA is O
When it becomes N, the odd-numbered bit lines on the α side are precharged,
Even if the even-numbered bit line next to it is on the α side, BPαB is O
It is not precharged until it reaches N. Therefore, even when the columns are connected to the bit lines on the same side, operation becomes possible.

FIG. 6 is a configuration diagram of a semiconductor memory device according to the third embodiment of the present invention. In the description of the semiconductor memory device according to the present embodiment, the same components as those of the semiconductor memory device shown in FIG.

In FIG. 6, the semiconductor memory device 40 has
M × n ROM cells A11 to A, each having two rows and n columns
a memory cell array 21 composed of a mn array, an address generation circuit 41, a word line address decoder 13, a bit line address decoder 23, a column switch 24, a bit line precharge circuit 42, a data line precharge circuit 17,
And a sense amplifier 18.

The bit line precharge circuit 42 includes a first bit line Bαi and a second bit line Bβi of each row.
, And is provided separately for each bit line.

That is, the RO # according to the present embodiment includes m × n memory cells as in the first and second embodiments, and the bit lines are provided as shown in the outputs BP1 to BP2m of the address generation circuit 41. There are 2m precharge signals, one for each bit line.

Hereinafter, the operation of the semiconductor memory device 40 configured as described above will be described.

FIG. 7 is a timing chart showing the operation of the semiconductor memory device 40. The ROM shown in FIG.
11, A12, ..., A1n, A21, A22, ..., A2m, ..., Amn
7 is a timing chart showing the operation when the data is sequentially accessed in the column direction as shown in FIG. The bit line precharge signal BP indicates up to BP4.

In this embodiment, only the precharge signal of the bit line to be used next is turned ON, and the other bit lines are not precharged. For example, as shown in FIG. 7, when precharging the first bit line, only the bit line precharge signals BP1 and BP2 are turned on, and the bit line precharge signals for the other bit lines (BP in FIG. 7).
1, BP2) Not precharged. That is, the second
The operation is the same as that of the embodiment.

As described above, the semiconductor memory device 40 according to the third embodiment includes a ROM having first and second bit lines.
In the above, since the precharge circuit 42 for precharging the first bit line and the second bit line of each row is separately provided for each bit line, the description has been given in the second embodiment. In addition to the effect, only the bit line to be used next is precharged, so that there is no extra precharge operation of the bit line, resulting in lower power consumption.

FIG. 8 is a configuration diagram of a semiconductor memory device according to the fourth embodiment of the present invention. In the description of the semiconductor memory device according to the present embodiment, the same components as those of the semiconductor memory device shown in FIG.

In FIG. 8, the semiconductor memory device 50 is
M × n ROM cells A11 to A, each having two rows and n columns
mn memory cell array 21 and address generation circuit 5
1, a word line address decoder A52, a word line address decoder B53, a bit line address decoder 54, a column switch 55, a bit line precharge circuit 56, a data line precharge circuit 17, and a sense amplifier 18.

The bit line precharge circuit 56 includes a first bit line precharge circuit 57 composed of PMOS transistors for precharging the bit lines in the first half row, and a bit line precharge circuit 57 in the second half row, as shown by the broken line in FIG. And a second bit line precharge circuit 58 for precharging the bit lines.

That is, the semiconductor memory device 50 prepares two word lines for each column, and the first word line WAj is connected to the ROM cells A11 to A11 connected to the bit lines in the first half row.
mn (storage element), and the second word line WBj is connected to the ROM cells A11 to Amn connected to the bit lines in the latter half of the row, and the n first word lines WBj are connected to the first half.
A word line address decoder A52 (first word line decoder) for selecting one of the word lines WAj, and a word line address decoder B53 for selecting one of the n second word lines WBj ( (Second word line decoder)
And a first bit line precharge circuit 57 for precharging the bit lines in the first half row, and a second bit line precharge circuit 58 for precharging the bit lines in the second half row.

As described above, ROΜ according to the present embodiment is:
As in the first, second, and third embodiments, m × n memory cells are provided, and each column has two word lines (WAj, Wj).
Bj) exists, WΑj is connected to the cells in the first to i-th rows, WBj is connected to the cells in the i + 1 to m-th rows, respectively, and word line address decoders A52 and B53 are provided respectively. Two bit line precharge signals (BP
A, BPB), the bit line precharge signal BPA is B1 to Bi, and the bit line precharge signal BPB is Bi + 1.
~ Bm is precharged.

Hereinafter, the operation of the semiconductor memory device 50 configured as described above will be described.

FIG. 9 is a timing chart showing the operation of the semiconductor memory device 50.

When the data is sequentially accessed in the row direction, data is read out to the precharge bit lines in the (i + 1) to m-th rows while the data in the first to i-th rows is being read. While the data in the m-th row is being read, the precharge
Read data to the bit line.

First, during the readout period of A (i + 1) (j-1) to Am (j-1) (period 420 shown in FIG. 9), the bit line precharge signal BPA turns ON (high level). , Bit lines B1 to Bi are precharged.

Next, W # j is turned ON (high level) by the word line address decoder A52, and the data of the RO # cells A1j-Aij is output to the bit lines B1-Bi.

The reading period of A (i + 1) (j-1) to Am (j-1) is completed, and the reading period of A1j to Aij (see FIG. 9).
21), the data line precharge signal DP
Becomes ON (high level) and the data line 19 is precharged, and then the column selection signal C1 becomes ON (high level) and the data previously output to the bit line B1 is replaced by the data line 19 and the sense amplifier 18. Output to the outside through

Thereafter, the rows are sequentially selected, and the data is read. During the reading period of A1j to Aij,
Bit line precharge signal BPB is ON (high level)
, The bit lines Bi + 1 to Bm are precharged, and the same operation is repeated thereafter.

As described above, in the semiconductor memory device 50 according to the fourth embodiment, two word lines are prepared for each column, and the first word line WAj is connected to the bit line in the first half row. The second word line WBj is connected to the ROM cells A11 to Amn connected to the bit lines in the latter half row, and the n first cells are connected to the memory cell array 21 composed of the ROM cells A11 to Amn. A word line address decoder A52 for selecting one of the word lines WAj, a word line address decoder B53 for selecting one of the n second word lines WBj, and a bit line in the first half row are pre-selected. A first bit line precharge circuit 57 for charging and a second bit line precharge circuit 58 for precharging bit lines in the latter half of the row are provided, and when addresses are sequentially selected in the row direction. A first process for sequentially outputting the data of the ROM cells A11 to Amn in the first half row of the column selected by the first word line WAj to the outside, and a second process for performing the first process. After precharging the bit lines in the latter half row connected to the word line WBj of the second word line WBj, the second word line WB
j, the data of the ROM cells A11 to Amn connected to
A second process of outputting to the bit line of the latter half row;
After the end of the third process, a third process of sequentially outputting the data output to the bit lines in the second process to the outside,
Is performed, the bit line in the first half row connected to the first word line WAj is precharged, and then the first column is selected in the next column whose address is selected in the second process. ROM cells A11 to A11 connected to the word line WAj of
A fourth process for outputting the data of Amn to the bit line in the first half row is provided, and the first to fourth processes are repeatedly performed. By dividing the line into the first to i-th rows and the i + 1 to m-th rows, the bit lines in the (i + 1) to m-th rows are precharged in advance while the data in the first to i-th rows are being read. By reading data onto the bit line, a significantly high-speed operation can be performed.

FIG. 10 is a configuration diagram of a semiconductor memory device according to the fifth embodiment of the present invention. In the description of the semiconductor memory device according to the present embodiment, the same components as those of the semiconductor memory device shown in FIG.

In FIG. 10, a semiconductor memory device 60 includes:
m × n ROM cells A11 through m rows and n columns
Amn, a memory cell array 21, an address generation circuit 61, a word line address decoder A62, a word line address decoder B63, a bit line address decoder 23,
Column switch 24, bit line precharge circuit 64,
Data line precharge circuit 17 and sense amplifier 18
It is comprised including.

The bit line precharge circuit 64 includes a first bit line precharge circuit 65 for precharging an odd-numbered row of the first bit line Bαi, as shown by a broken line in FIG. A first bit line precharge circuit 66 for precharging even-numbered rows of the line Bαi;
A second bit line precharge circuit 67 for precharging an odd-numbered row of the bit line Bβi
and a second bit line precharge circuit 68 for precharging an even-numbered row of i.

As described above, ROΜ according to the present embodiment is:
There are two word lines (WΑj, WBj) in each column,
WΑj is connected to the cells in the first to i-th rows, and WBj is connected to the cells in the i + 1 to m-th rows, respectively, and word line address decoders A62 and B63 are provided respectively. There are four bit line precharge signals (BPαA, BPαB, B
PβA, BPβB), and BPαA is Bα1-Bαi
, BPαB represents Bβ1 to Bβi, and BPβA represents Bαi + 1 to Bβi.
αm and BPβB precharge Bβi + 1 to Bβm, respectively.

Hereinafter, the operation of the semiconductor memory device 60 configured as described above will be described.

The basic operation is the same as that described in the first embodiment. In this embodiment, for example, Aij
During the reading of the precharge signal BPαA,
BPβA and BPβB are turned ON (high level) and BPα
All bit lines (Bα1 to Bαm, Bβi + 1 to Bβm in this case) other than the bit lines precharged by B are precharged in advance. That is, while Aij is being read, Bα1 to Bαm, Bβi + 1 to Bβm
Is pre-charged in advance.

As described above, in the semiconductor memory device 60 according to the fifth embodiment, two word lines are prepared for each column, and the first word line WAj is connected to the bit line in the first half row. The second word line WBj is connected to the ROM cells A11 to Amn connected to the bit lines in the latter half row, and the n first cells are connected to the memory cell array 21 composed of the ROM cells A11 to Amn. A word line address decoder A52 for selecting one of the word lines WAj and a word line address decoder B53 for selecting one of the n second word lines WBj are provided. 2
The first bit line is connected to the odd-numbered column ROM cells A11 to Amn, and the second bit line is connected to the even-numbered column RO.
First bit line precharge circuits 65, 66 connected to M cells A11 to Amn to precharge the first bit line
And second bit line precharge circuits 67 and 68 for precharging the second bit line;
And a column switch 24 for selecting each of the bit lines. The address is selected, and while the data of the ROM cells A11 to Amn are read and output to the outside, the address of the ROM cells A11 to Amn selected at this time is stored in the ROM cells A11 to Amn. A first process for precharging all the bit lines that are not connected, and after the first process is completed, any one of the ROM cells A11 connected to the bit line precharged in the first process.
~ Amn is selected, and the selected ROM cell A11 ~
A second process for reading Amn data and outputting it to the outside is provided, and the first process and the second process are repeatedly performed. Therefore, in addition to the effects of the first embodiment, When Aij is read out, Bα1 to Bαm,
Since Bβi + 1 to Bβm are precharged in advance, the next selected ROM cell is bit lines Bα1 to Bα
m, Bβi + 1 to Bβm, high-speed operation is possible even with an access method other than the case where addresses are sequentially selected.

In the semiconductor memory device according to each of the above embodiments, a ROM cell array is used as a memory cell array. However, any memory element may be used.
It may be applied to a ROM cell.

In each of the above embodiments, the semiconductor memory device is applied to a ROM control device.
It goes without saying that the present invention can be applied to any semiconductor memory device.

Further, as long as the semiconductor memory device according to each of the above embodiments has at least two bit lines in each row or at least two word lines in each column, Such a configuration may be used,
The number of bit lines, word lines, various peripheral circuits and the like, the connection state, and the like are not limited to the above embodiments.

[0083]

In the semiconductor memory device according to the present invention, at least two bit lines are prepared for each row, the first bit line is connected to the odd-numbered column storage element, and the second bit line is connected to the even-numbered column. A first bit line precharge circuit that connects to the storage element in the column and precharges the first bit line, a second bit line precharge circuit that precharges the second bit line, Since a column switch for selecting each of the bit line and the second bit line is provided, it is possible to eliminate the need for the pre-charging and the data reading operation of the bit line having a large load, which is required each time. The operations performed during this period are only precharging of the data line with a small load and reading of data that has been output up to the bit line, and a significant high-speed operation can be realized.

Further, in the semiconductor memory device according to the present invention,
A first bit line precharge circuit for precharging an odd row of the first bit line, a second bit line precharge circuit for precharging an even row of the first bit line, and a second bit 3rd to precharge odd lines of line
And a fourth bit line precharge circuit for precharging an even-numbered row of the second bit line. When an address is sequentially selected in the column direction, the adjacent first bit line And the second bit line is precharged using a different bit line precharge circuit, so that adjacent bit lines are always precharged with different precharge signals, so that the first column and the nth column Operation is possible even when the eyes are connected to the same bit line.

In the semiconductor memory device according to the present invention,
A bit line precharge circuit for precharging the first bit line and the second bit line of each row is separately provided for each bit line, and is used next when address is sequentially selected in the column direction. Since only the bit line to be used is precharged, only the bit line to be used next is precharged, so that an extra bit line precharge operation is eliminated and lower power consumption can be achieved. .

In the semiconductor memory device according to the present invention,
At least two word lines are prepared for each column. The first word line is connected to the storage element connected to the bit line in the first half row, and the second word line is connected to the bit line in the second half row. A first word line decoder connected to the connected storage element and selecting one of n first word lines, and selecting one of n second word lines. A second word line decoder, a first bit line precharge circuit for precharging the bit lines in the first half row, and a second bit line precharge circuit for precharging the bit lines in the second half row When the word line is divided into the first to i-th rows and the i + 1 to m-th rows, the bit lines in the (i + 1) to m-th rows are precharged while the data in the first to i-th rows are being read. And read the data of each row to the bit line Can, it is possible to significantly high-speed operation.

In the semiconductor memory device according to the present invention,
Two bit lines are prepared for each row, the first bit line is connected to the odd-numbered column storage elements, the second bit line is connected to the even-numbered column storage elements, and the first bit line is connected to the odd-numbered column storage elements. A first bit line precharge circuit for precharging;
A second bit line precharge circuit for precharging the first bit line and a column switch for selecting each of the first bit line and the second bit line. A first process of precharging all bit lines that are not connected to the storage element whose address is selected at this time, and the first process after the first process is completed. And a second process for selecting an address of any of the storage elements connected to the bit line precharged in step 2, reading data of the selected storage element, and outputting the data to the outside. Is repeated, so that high-speed operation is possible even with an access method other than when addresses are sequentially selected.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a semiconductor memory device according to a first embodiment to which the present invention is applied.

FIG. 2 is a timing chart showing an operation of the semiconductor memory device when addresses are sequentially selected in a row direction.

FIG. 3 is a timing chart showing an operation of the semiconductor memory device when addresses are sequentially selected in a column direction.

FIG. 4 is a configuration diagram of a semiconductor memory device according to a second embodiment to which the present invention is applied.

FIG. 5 is a timing chart showing an operation of the semiconductor memory device when an address is sequentially selected in a column direction.

FIG. 6 is a configuration diagram of a semiconductor memory device according to a third embodiment to which the present invention is applied.

FIG. 7 is a timing chart showing an operation when addresses are sequentially selected in a column direction of the semiconductor memory device.

FIG. 8 is a configuration diagram of a semiconductor memory device according to a fourth embodiment to which the present invention is applied.

FIG. 9 is a timing chart showing an operation of the semiconductor memory device when addresses are sequentially selected in a row direction.

FIG. 10 is a configuration diagram of a semiconductor memory device according to a fifth embodiment to which the present invention is applied.

FIG. 11 is a diagram showing a configuration of a conventional ROM.

FIG. 12 is a timing chart showing the operation of a conventional ROM.

[Explanation of symbols]

13 word line address decoder, 17 data line precharge circuit, 18 sense amplifier, 19 data line, 2
0, 30, 40, 50, 60 semiconductor memory devices, 21
Memory cell array, 22, 31, 41, 51, 61 address generation circuit, 23, 32, 54 bit line address decoder, 24, 55 column switch, 25, 42,
56, 64 bit line precharge circuit, 26 first bit line precharge circuit, 27 second bit line precharge circuit, 33, 34, 65, 66 first bit line precharge circuit, 35, 36, 67 , 68 Second bit line precharge circuit, 52, 62 Word line address decoder A, 53, 63 Word line address decoder B, 57 First bit line precharge circuit, 58
A second bit line precharge circuit, Bαi first bit line, Bβi second bit line, W1 to Wn word lines,
BPα Bit line precharge signal for first bit line Bαi, BPβ Bit line precharge signal for second bit line Bβi, DP data line precharge signal, Cα1
~ Cαm The column selection signal of the first bit line Bαi, C
β1 to Cβm A column selection signal for the second bit line Bβi

Claims (9)

[Claims] 1. An n (n is an arbitrary integer) word line for selecting a column, a word line decoder for selecting one of the n word lines, and an m (m is an integer) for selecting a row. An arbitrary integer) column switch, m bit lines for transferring data written in the storage elements of the selected column, m × n storage elements connected to the word lines and bit lines, and bits In a semiconductor memory device having a bit line precharge circuit for precharging a line, at least two bit lines are prepared in each row, and a first bit line is connected to a storage element in an odd column, and
A first bit line precharge circuit for precharging the first bit line, and a second bit line precharge circuit for precharging the second bit line. A semiconductor memory device comprising: a charge circuit; and a column switch for selecting each of the first bit line and the second bit line. 2. The semiconductor memory device according to claim 1, wherein, when an address is sequentially selected in a row direction, data of a storage element in a column selected by a word line is sequentially transmitted using said first bit line. Between the first processing to output to the outside and the first processing, the second bit line precharge circuit is used to precharge the second bit line, and then the next bit line is used for the next column. A second processing for reading data of a selected storage element to a second bit line, wherein the first processing and the second processing are repeatedly performed. 3. The semiconductor memory device according to claim 1, wherein when address selection is performed sequentially in a column direction, the semiconductor memory device is connected to the first bit line selected by the word line and a column switch. Between the first process of outputting data of the storage element being stored to the outside and the first process, the second bit line is precharged by using the second bit line precharge circuit. A semiconductor memory device comprising: a second process, wherein the first process and the second process are repeatedly operated. 4. The semiconductor memory device according to claim 1, wherein said first bit line is precharged to an odd-numbered row.
A second bit line for precharging an even-numbered row of the first bit line.
A third bit line for precharging an odd-numbered row of the second bit line.
And a fourth line for precharging an even-numbered row of the second bit line.
When address selection is performed sequentially in the column direction, adjacent first bit lines and second bit lines are precharged using different bit line precharge circuits. The bit line connected to the last addressed storage element and the bit line connected to the first addressed storage element in the next column are the same first bit line or second bit line A semiconductor memory device characterized by being operable even in the case of (1). 5. The semiconductor memory device according to claim 1, wherein a bit line precharge circuit for precharging a first bit line and a second bit line in each row is provided. A semiconductor memory device provided separately for each bit line, and when sequentially selecting addresses in the column direction, only the next used bit line is precharged. 6. An n (n is an arbitrary integer) word line for selecting a column, a word line decoder for selecting one of the n word lines, and an m (m is an integer) for selecting a row. An arbitrary integer) column switch, m bit lines for transferring data written in the storage elements of the selected column, m × n storage elements connected to the word lines and bit lines, and bits In a semiconductor memory device having a bit line precharge circuit for precharging a line, at least two word lines are prepared in each column, and a first word line is connected to a bit line in a first half row. A first word line that connects to the elements and a second word line that connects to the storage elements that are connected to the bit lines in the second half row and selects one of the n first word lines A decoder and one of the n second word lines A second word line decoder, a first bit line precharge circuit for precharging the bit lines in the first half row, a second bit line precharge circuit for precharging the bit lines in the second half row, A semiconductor memory device comprising: 7. The semiconductor memory device according to claim 6, wherein, when addresses are sequentially selected in a row direction, data of storage elements in a first half row of a column selected by said first word line are sequentially sent to the outside. A first process for outputting, and while the first process is being performed, a bit line in a second half row connected to the second word line is precharged. A second process of outputting the data of the storage element connected to the second word line to the bit line of the latter half row in the column where the address is selected, and after the second process is completed. A third process for sequentially outputting data output to the bit line in the second process to the outside, and a third process for connecting to the first word line while the third process is being performed. After precharging the bit lines in the first half of A fourth process of outputting data of a storage element connected to the first word line to a bit line in the first half row in a next column whose address is selected in the second process. A semiconductor memory device, comprising: repeatedly operating the first processing to the fourth processing. 8. The semiconductor memory device according to claim 6, wherein two bit lines are prepared for each row, and said first bit line is connected to a storage element in an odd column. A second bit line connected to the storage element in the even column, a first bit line precharge circuit for precharging the first bit line, and a second bit line for precharging the second bit line. A bit line precharge circuit, and a column switch for selecting each of the first bit line and the second bit line. While the address is selected, the data of the storage element is read and output to the outside. A first process of precharging all bit lines not connected to the storage element selected at this time, and after the first process is completed, the first process is performed. A second process of address-selecting any storage element connected to the bit line, reading data of the selected storage element, and outputting the data to the outside, wherein the first processing and the second processing are performed. A semiconductor memory device which is operated repeatedly. 9. The semiconductor memory device according to claim 1, wherein said memory element is a ROM cell.