JPH10336526A - Solid-state image-pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain high speed measurement and to eliminate the effect of dispersion in offset at the same time. SOLUTION: A current signal outputted from a photodiode PD is stored in a capacitive element C1 and integrated, based on an instruction of a Reset signal in an integration circuit 10, consisting of parallel connection of an amplifier A1 and the capacitive element C1. First and second signal levels, outputted from the integration circuit 10 at 1st and 2nd times for each integration operation period in the integration circuit 10, are given to a CDS circuit 20 via a switch element S2 operated, based on the instruction of the Sample signal and a signal equivalent to the difference of the both is latched by the CDS circuit 20 and outputted, based on the instruction of a Clamp signal. The signal outputted from the CDS circuit 20 is read as a charge amount by a read circuit 30 operated based on an instruction of a Scan signal or the like, and the charge amount is converted into a voltage signal by a current voltage conversion circuit 40 and then outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state imaging device for converting an input optical signal into an electric signal corresponding to the amount of light.

[0002]

2. Description of the Related Art An imaging apparatus using a solid-state imaging device is used in various fields such as home video and nondestructive inspection. As such solid-state imaging devices, those using a charge-coupled device (CCD) and those using a silicon photodiode array are known. Among them, a solid-state imaging device using a photodiode array has excellent charge transfer efficiency even when relatively large charges are handled, and is therefore used in the field of manufacturing various consumer products.

[0003] For example, US Pat.
1 is a circuit configuration diagram of a solid-state imaging device using a photodiode as shown in FIG. In the solid-state imaging device shown in this figure, the signal VIN output from the photodiode is
The integration is performed for a predetermined time by an integration circuit including the amplifier 25, the capacitance element C3, and the switches S5 and S6, and the integration result is output as a voltage signal V1 corresponding to the electric charge stored in the capacitance element C3. When the photodiodes are arrayed, the integration circuit is provided for each photodiode.

The voltage signal V1 output from the integrating circuit
Is connected to the amplifier 27 and the capacitor C1 via the capacitor C2.
And a readout circuit composed of switch elements S2 to S4, which sequentially read out the data, and output the readout result as a voltage signal V2 corresponding to the charge stored in the capacitor C1. Then, the electric charge stored in the capacitance element C1 of the read circuit is converted into a voltage signal VOUT by a current-voltage conversion circuit including the amplifier 29, the capacitance element C0 and the switch element S1, and the voltage signal VOUT is output. That is, the voltage signal VOUT indicates the amount of light received by the photodiode.

[0005]

However, the above-mentioned conventional solid-state imaging device has the following problems. That is, generally, since the amplifier 25 and the like are manufactured using the CMOS technology, there is a problem that occurrence of offset variation cannot be avoided. Here, the offset variation of the amplifier 25 means that the output level of the amplifier 25 varies when there is no input (that is, when the photodiode does not receive light) and that the switch element S6
Means that the output level of the amplifier 25 is different between the ON state and the OFF state. As described above, when there is offset variation in the amplifier 25, the voltage signal VOUT output from the current-voltage conversion circuit has a component in which the offset variation is superimposed. Therefore, the amount of light received by the photodiode cannot be measured accurately, and the light image obtained by the photodiode array also becomes inaccurate.

Further, in this conventional solid-state imaging device, the signal VIN output from the photodiode passes through an integrating circuit (such as the amplifier 25), a readout circuit (such as the amplifier 27), and a voltage through a current-voltage conversion circuit (such as the amplifier 29). Since a series of processes of outputting as the signal VOUT is performed each time light is received by the photodiode, there is a problem that the above series of processes requires time. In particular, the larger the number of elements in the photodiode array, the longer the time required for the series of processes.

Incidentally, in recent years, the PL method (product liability law)
With the enforcement of the law, products flowing on the belt conveyor in the field of manufacturing various foods and other consumer goods
It has become essential to perform line non-destructive inspection, and in many cases, a one-dimensional long silicon photodiode array is used in a non-destructive inspection device. Also, there is an increasing demand from manufacturers to be able to move the belt conveyor faster and inspect more products in a shorter time. However, as described above, the conventional solid-state imaging device has a limit in increasing the speed.

As described above, both high-speed and high-precision solid-state imaging devices are desired, but analog devices including solid-state imaging devices generally achieve both high-speed and high-precision. It was difficult.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has solved the problem of offset variation.
It is another object of the present invention to provide a solid-state imaging device capable of high-speed measurement.

[0010]

According to the present invention, there is provided a solid-state imaging device comprising: (1) a photoelectric conversion element for converting an input optical signal into a current signal; a light receiving unit for outputting the current signal; )
An amplifier for inputting a current signal output from the light receiving section and a capacitance element are connected in parallel, and an integration circuit for accumulating and integrating the current signal in the capacitance element based on an instruction of a reset signal; (3)
A first terminal is connected to an output terminal of the integration circuit, and based on an instruction of the sample signal, at the first and second times during each integration operation period in the integration circuit, the first and the second output from the integration circuit are respectively provided. Each of the second signal levels is
And (4) holding a signal corresponding to the difference between the first and second signal levels output from the second terminal of the switch element based on the instruction of the clamp signal. A readout circuit for reading out the signal output from the CDS circuit as an electric charge based on the instruction of the hold signal; and (6) a readout circuit for converting the electric charge read out by the readout circuit into a voltage signal. The present invention is characterized by comprising: a current-voltage conversion circuit for conversion; and (7) timing control means for outputting each of a reset signal, a sample signal, a clamp signal, and a hold signal at a predetermined timing.

According to this solid-state imaging device, the input signal light is converted into a current signal by the photoelectric conversion element of the light receiving section and output, and the current signal is converted by the integration circuit in which the amplifier and the capacitor are connected in parallel. , And is accumulated and integrated in the capacitance element based on the instruction of the reset signal. Each of the first and second signal levels output from the integration circuit at each of the first and second times during each integration operation period in the integration circuit is supplied to the CDS via a switch element that operates based on the instruction of the sample signal. A signal corresponding to the difference between the two is input to the circuit and is held and output by the CDS circuit based on the instruction of the clamp signal. The signal output from the CDS circuit is read as a charge by a read circuit that operates based on the instruction of the hold signal, and the charge is converted into a voltage signal by a current-voltage converter and output. The signal output from the current-voltage conversion circuit indicates the amount of signal light input to the photoelectric conversion element.

[0012] Further, (1) the light receiving section includes a predetermined number of two or more photoelectric conversion elements, and outputs a current signal from each of the predetermined number of photoelectric conversion elements. (2) an integration circuit, a switch element, The CDS circuit and the readout circuit are provided for each of the predetermined number of photoelectric conversion elements, and (3) the readout circuit further outputs the predetermined number of photoelectric conversion elements from the CDS circuit at mutually different timings based on the instruction of the scan signal. The output signal is read as a charge amount, and (4) the timing control means further outputs a scan signal at a predetermined timing.

In this case, the current signal output from each of the predetermined number of photoelectric conversion elements of the light receiving section is converted by an integrating circuit, a switch element, a CDS circuit, and a reading circuit provided corresponding to each of the predetermined number of photoelectric conversion elements. Processed sequentially. However, the signal output from each CDS circuit is read out as a charge amount by each readout circuit at different timings based on the instruction of the scan signal, and the charge amount sequentially read out by each readout circuit is Are sequentially converted into voltage signals by the current-voltage conversion circuit and output. The signal output from the current-voltage conversion circuit indicates the amount of signal light input to each of the predetermined number of photoelectric conversion elements in time series.

Further, (1) the light receiving section includes a predetermined number of photoelectric conversion elements two-dimensionally arranged in M rows and N columns, and for each of the M rows, the light receiving section of each row is instructed based on the instruction of the first scan signal. Current signals from each of the N photoelectric conversion elements are output at mutually different timings. (2) An integrating circuit, a switch element, a CDS circuit, and a readout circuit are provided for each row of the light receiving section including the N photoelectric conversion elements. (3) Further, the readout circuit further performs the timing control for each row of the N photoelectric conversion elements in the light receiving unit at different timings based on the instruction of the second scan signal.
The signal output from the DS circuit is read as a charge amount,
(4) The timing control means further outputs each of the first and second scan signals at a predetermined timing.

In this case, for each of the M rows in the light receiving section composed of a predetermined number of photoelectric conversion elements arranged two-dimensionally in M rows and N columns, the current signals from each of the N photoelectric conversion elements in each row are the first signals. The signals are output at different timings based on the instruction of the scan signal, and are sequentially processed by the integrating circuit, the switching element, the CDS circuit, and the reading circuit.
However, the signal output from each CDS circuit is further changed to the second
N in the light receiving section based on the instruction of the scan signal of
Each row of the photoelectric conversion elements is read out as a charge amount by each readout circuit at different timing from each other, and the charge amount sequentially read out by each readout circuit is sequentially converted into a voltage signal by the current-voltage conversion circuit. Is output. The signal output from the current-voltage conversion circuit indicates the amount of signal light input to each of the M × N photoelectric conversion elements in time series.

[0016]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. In the description of the drawings, the same elements will be denoted by the same reference symbols, without redundant description.

FIG. 1 is a circuit configuration diagram of a solid-state imaging device according to a first embodiment. This figure is
1 shows a circuit configuration of a solid-state imaging device having a light receiving unit in which photodiodes (photoelectric conversion elements) PD are arranged in a one-dimensional array, and each unit 100 ₁ to 10 shown in the figure.
0 _M each is a photodiode PD, an integrating circuit 1
0, switch element S2, CDS (correlated double sa)
mpling) circuit 20 and readout circuit 30 are included one by one. Each of the units 100 _{1 to} 100 _M has the same configuration, and their output terminals are both connected to the input terminal of the current-voltage conversion circuit 40. Also,
Units 100 _{1 to} 100 _M and current / voltage conversion circuit 4
0 Each control signal indicating each operation timing is:
It is output from the timing control circuit 50.

The photodiode PD has an anode terminal grounded and a cathode terminal connected to the input terminal of the integration circuit 10. The integration circuit 10 for inputting a current signal output from the photodiode PD is configured such that an amplifier A1, a capacitor C1, and a switch S1 are connected in parallel between an input terminal and an output terminal. The switch element S1 is on / off controlled by a Reset signal output from the timing control circuit 50.

The switch element S2 has one terminal connected to the output terminal of the integrating circuit 10 and the other terminal connected to the CDS.
The timing control circuit 5 is connected to the input terminal of the circuit 20.
On / off control is performed by a Sample signal output from 0.

In the CDS circuit 20, a capacitance element C2 and an amplifier A2 are cascaded in this order between the input terminal and the output terminal, and the amplifier A2, the capacitance element C3 and the switch element S3 are connected in parallel. It is configured. The on / off control of the switch element S3 is controlled by the Clamp signal output from the timing control circuit 50.

The read circuit 30 has an input terminal of the CDS circuit 2
0, the switching element S4, the capacitance element C4, and the switching element S5 are cascaded in this order between the input terminal and the output terminal, and between the capacitance element C4 and the switching element S5. A switch element S6 is provided between the connection point and the ground. The switch element S4 is on / off controlled by a Hold signal, the switch element S5 is on / off controlled by a Scan signal, and the switch element S6 is on / off controlled by a Reset signal. Here, the Hold signal is a signal represented by the logical sum of the logical product of the Hold_1 signal and the Scan signal and the Hold_0 signal,
Each of the Hold_0 signal, the Hold_1 signal, and the Scan signal is output from the timing control circuit 50. Further, Scan signal is a pulse signal generated at different timings depending on the respective units 100 ₁ to 100 _M.

The current-to-voltage conversion circuit 40 has an input terminal connected to the readout circuit 30 of each of the units 100 _{1 to} 100 _M.
The switch element S8 and the amplifier A3 are cascaded in this order between the input terminal and the output terminal, and the amplifier A3, the capacitance element C5, and the switch element S9 are connected in parallel. Further, a switch element S7 is provided between the input terminal and the ground.
Here, each of the switch elements S7 and S9 is Fres
On / off control is performed by the et signal, and the switch element S8
Are controlled on / off by the Hold_1 signal.

The timing control circuit 50 outputs a Reset signal,
Sample signal, Clamp signal, Hold_0 signal, Hold_1 signal, Sc
This is a circuit that outputs each of the an signal and the Freset signal at a predetermined timing shown in FIG. 2 to be described later based on a reference clock signal or the like.

In this figure, the lines of the control signals from the timing control circuit 50 to the units 100 _{1 to} 100 _M and the current / voltage conversion circuit 40 are omitted. In this figure, the output terminal of the integrating circuit 10 is point A, and the input terminal of the CDS circuit 20 is point B.
The output terminal of the CDS circuit 20 is set to a point C;
, And the output terminal of the current-voltage conversion circuit 40 is indicated by a point E. In the following, the potentials at points A, B, C, D and E will be referred to as VA, VB, respectively.
, VC, VD and VE. The code Cp is
The parasitic capacitance between each of the units 100 _{1 to} 100 _M and the current-voltage conversion circuit 40 is shown.

Next, the operation of the solid-state imaging device will be described with reference to a timing chart shown in FIG. FIG. 2 is a timing chart illustrating the operation of the solid-state imaging device according to the present embodiment. As shown in FIG. 2A, the rising time of a certain reset signal pulse and the next
One cycle is between the rising time of the reset signal pulse and each control signal is a signal that is repeated with this one cycle as a cycle. FIG. 2 shows each control signal and the potential at each point during a period of two cycles.

In the solid-state imaging device according to this embodiment, the first
In the period of the cycle, the signal from the photodiode PD is integrated by the integrating circuit 10, and the integration result is processed by the CDS circuit 20, and in the subsequent second cycle, the output from the CDS circuit 20 is read out. The data is read out by the circuit 30 and converted into a voltage signal by the current-voltage conversion circuit 40. Then, within one cycle period, the processing in each of the integration circuit 10 and the CDS circuit 20 and the processing in each of the readout circuit 30 and the current-voltage conversion circuit 40 are performed independently of each other. The details will be described below.

While the Reset signal (FIG. 2A) for controlling the switch element S1 of the integrating circuit 10 is at a high level, the switch element S1 is turned on, and the connection between the input terminal and the output terminal of the amplifier A1 is established. In a short-circuit state, the capacitive element C1 is discharged. On the other hand, while the Reset signal is at the low level, the switch element S1 is in the off state, and the current signal output from the photodiode PD is stored in the capacitor C1. That is, the integration circuit 10 performs the Reset
Only when the signal is at the low level, the photodiode P
The current signal output from D is stored in the capacitor C1 as electric charge, and a voltage signal corresponding to the stored electric charge is output to the output terminal (point A). Therefore, the potential VA at point A
As shown in FIG. 2B, the signal changes only during a period when the reset signal is at a low level, and is maintained at an offset level during a period when the reset signal is at a high level.

As shown in FIG. 2C, the Sample signal for controlling the switch element S2 is a signal in which two pulses having the same pulse width are present during one cycle, and the first pulse is , A pulse that rises after the fall of the reset signal pulse, and the second pulse is the next Res.
It is a pulse that falls before the rising of the et signal pulse.

During one cycle, first, when the switch element S2 is turned on by the first pulse of the Sample signal, the potential VB of the input terminal (point B) of the CDS circuit 20 becomes
At this time, the potential VA of the output terminal of the integrating circuit 10 becomes the value V1. After that, while the Sample signal is low level,
The potential VB of the input terminal (point B) of the CDS circuit 20 is the value V
Maintained at 1. Next, when the switch element S2 is turned on by the second pulse of the Sample signal, CD
The potential VB of the input terminal (point B) of the S circuit 20 becomes the value V2 of the potential VA of the output terminal of the integrating circuit 10 at that time. That is, the potential VB of the input terminal (point B) of the CDS circuit 20
Changes rapidly from the value V1 to the value V2 by the second pulse of the Sample signal, as shown in FIG. 2D.

The Clamp signal for controlling the switch element S3 of the CDS circuit 20 falls before the rising of the second pulse of the Sample signal, as shown in FIG.
The signal rises after the fall of the second pulse of the signal. That is, the Clamp signal is at the low level for a certain period including the period during which the second pulse of the Sample signal is at the high level. A second pulse of the Sample signal is generated during a period in which the Clamp signal is at the low level and the switch element S3 is in the OFF state, and the potential VB of the input terminal (point B) of the CDS circuit 20 changes from the value V1 to the value V1. When the voltage changes to V2, a charge corresponding to the amount of the change is accumulated in the capacitor C3.
As shown in (f), the potential VC corresponding to the charge amount becomes C
It appears at the output terminal (point C) of the DS circuit 20. This potential V
The value V3 of C is expressed as follows: V3 = (V2-V1) .C2 / C3 (1) After that, even if the Clamp signal goes high and the switch element S3 is turned on, the CDS circuit 2
The output potential VC from 0 is maintained at the value V3.

The Hold signal for controlling the switch element S4 of the read circuit 30 is formed by the logical product of the Hold_1 signal and the Scan signal and Ho.
This signal is a logical sum with the ld_0 signal. Also, the Scan signal is
On / off control of the switch element S5 is performed. Reset as described above
The signal controls on / off of the switch element S6.

The Hold_0 signal is, as shown in FIG.
This is a pulse signal generated at the same timing as the second pulse of the sample signal (a sample signal pulse generated while the clamp signal is at a low level). Hold_1 signal is
As shown in (h), the signal has M pulses in one cycle period. Here, M is the unit 100
It indicates the number of ₁ to 100 _M. The Scan signal is a signal having one pulse in one cycle period as shown in FIG. 2 (i), and its pulse width is substantially equal to the pulse width of the Hold_1 signal, and its pulse generation is performed. The timing substantially coincides with the generation timing of any one of the M pulses of the Hold_1 signal during one cycle period, but differs depending on each of the units 100 _{1 to} 100 _M. Therefore, the Hold signal is a signal having two pulses within one cycle as shown in FIG. 2 (j), and the first pulse is different depending on each of the units 100 _{1 to} 100 _M. The second pulse is generated at the same timing as the pulse of the Hold_0 signal.

The read circuit 30 whose timing is controlled by the control signal as described above, during one cycle,
When the reset signal is at the high level, the switch element S6 is turned on, the electric charge of the capacitor C4 is discharged, and thereafter, the reset signal is at the low level and the switch element S6 is turned on.
6 is turned off. At the time of the first pulse of the Hold signal, the Scan signal is also at the high level, and the switch element S
4 and S6 are both turned on, and the CDS circuit 20
Is output from the readout circuit 30 via the capacitive element C4. Therefore, the potential VD output from the output terminal (point D) of the read circuit 30 is as shown in FIG. Note that the actual potential at point D is
_Although the potentials sequentially output from _{1 to} 100 _M are integrated, FIG. 2 (k) shows one unit 1
Only the potential read from the 00 _m read circuit 30 is shown.

As described above, each of the units 100 ₁ to 100 ₁
00 _M signals sequentially outputted from the respective readout circuits 30 are input to the current-voltage conversion circuit 40. The reset signal for turning on / off the switch elements S7 and S9 of the current-voltage conversion circuit 40 is a signal obtained by inverting the high level and the low level of the Hold_1 signal as shown in FIG. The Freset signal switching element (S7) which is turned on / off controlled by discharges the parasitic capacitance Cp to the period in which the signals from the respective unit 100 ₁ to 100 _M respectively has not reached. The switch element (S9) which is turned on / off controlled by Freset signals, signals from each unit 100 ₁ to 100 _M, respectively to discharge the capacitor C5 to the period is not reached.
The switch element S8, which has been turned on / off by the Hold_1 signal, is turned on during a period in which a signal has arrived from each of the units 100 _{1 to} 100 _M , and the signal is output as a voltage signal from the current-voltage conversion circuit 40. Output to terminal (point E).

Therefore, the potential VE at the output terminal (point E) of the current-voltage conversion circuit 40 becomes, as shown in FIG.
A signal having M pulses in one cycle period, and each of the M pulses is connected to each unit 100 ₁
-100 _M corresponds to the signal output from each readout circuit 30, and the level of each of the M pulses corresponds to the light amount of the optical signal received by each photodiode PD.

As described above, during the first cycle, the signal output from the photodiode PD is integrated by the integrating circuit 10 (FIG. 2B), and the first and second pulses of the Sample signal are obtained. A signal corresponding to the level difference of the output signal of the integrating circuit 10 at each time is held and output by the CDS circuit 20 (FIG. 2 (f)). And the second
During the cycle of, the signal held in the CDS circuit 20 is read by the read circuit 30 to each of the units 100 _{1 to} 100 _M
Each of the units 100 _{1 to} 100 _M is read out at a different timing every time (FIG. 2 (k)), and the signals from each of the units 100 _{1 to} 100 _M are converted into voltage signals by the current / voltage conversion circuit 40 and output in time series (FIG. m)).

During the second cycle, the integrating circuit 10 and the CDS circuit 20 are operating, and the signal held in the CDS circuit 20 during the second cycle is changed to the third signal. In the read circuit 30
And the current-voltage conversion circuit 40 respectively. Therefore, the time required for one cycle is the longer of the time required for processing by each of the integrating circuit 10 and the CDS circuit 20 and the time required for processing by each of the reading circuit 30 and the current-voltage conversion circuit 40. It is possible to perform higher-speed measurement than a conventional solid-state imaging device.

Also, during the integration operation of the integration circuit 10,
The CDS circuit 20 holds the charge corresponding to the difference between the output signals of the integration circuit 10 at the time of each of the first and second pulses of the sample signal. Therefore, the influence of the offset variation of the amplifier A1 of the integration circuit 10 is eliminated, whereby accurate light quantity measurement is possible, and in the case of a photodiode array, accurate light image acquisition is possible.

(Second Embodiment) FIG. 3 is a circuit configuration diagram of a solid-state imaging device according to a second embodiment. This figure is
FIG. 1 is a circuit diagram of a solid-state imaging device having a light receiving unit in which photodiodes (photoelectric conversion elements) PD are two-dimensionally arranged in M rows × N columns.

In this case, N photodiodes PD, integrating circuit 10, switch element S2, CDS circuit 20, and readout circuit 30 are regarded as one unit, and M units are provided. In each of the _M units 200 ₁ to 200 _M , the output signal from each of the N photodiodes PD is converted to the Scan signal output from the timing control circuit 150.
The signal is sequentially processed by the integrating circuit 10 and the CDS circuit 20 based on the signal _1, and the output signal of the CDS circuit 20 is sequentially read by the reading circuit 30 based on the Scan_0 signal. The signals sequentially arrived from the _M units 200 ₁ to 200 _M are sequentially converted into voltage signals by the current-voltage conversion circuit 140. By doing so, M ×
Each signal corresponding to the light amount received by each of the N photodiodes is sequentially output as a voltage signal by the current-voltage conversion circuit 140. Also in this case, speeding up of the measurement and removal of the influence of the offset variation can be achieved at the same time.

The present invention is not limited to the above embodiment, and various modifications are possible. In the solid-state imaging device according to the above embodiment, the light receiving unit is a one-dimensional photodiode array, and each photodiode is provided with an integrating circuit, a CDS circuit, and a readout circuit. However, the present invention is not limited to this. .

For example, a solid-state imaging device may be configured to include a photodiode, an integration circuit, a switch element, a CDS circuit, a readout circuit, and a current-voltage conversion circuit. Also in this case, the processing by the integration circuit and the CDS circuit and the processing by the readout circuit and the current-voltage conversion circuit can be performed in parallel, so that high-speed measurement is possible. Further, the influence of the offset variation of the amplifier of the integration circuit is also eliminated.

In the second embodiment, M = 1
It may be. In this case, one unit including N photodiodes, an integrating circuit, a switching element, a CDS circuit, and a reading circuit is provided. In this case, the Scan_0 signal is unnecessary.

[0044]

As described above in detail, according to the present invention, the input signal light is converted into a current signal by the photoelectric conversion element of the light receiving section and output, and the current signal is converted by the amplifier and the capacitor. Are accumulated in the capacitance element and integrated by the integration circuit connected in parallel based on the instruction of the reset signal. Each of the first and second signal levels output from the integration circuit at each of the first and second times during each integration operation period in the integration circuit is supplied to the CDS via a switch element that operates based on the instruction of the sample signal. A signal corresponding to the difference between the two is input to the circuit and is held and output by the CDS circuit based on the instruction of the clamp signal. The signal output from the CDS circuit is read as a charge by a read circuit that operates based on the instruction of the hold signal, and the charge is converted into a voltage signal by a current-voltage converter and output. The signal output from the current-voltage conversion circuit indicates the amount of signal light input to the photoelectric conversion element.

With such a configuration, the integration circuit and the capacitor C can be operated during one cycle period indicated by the reset signal.
The processing by each of the DS circuits and the processing by each of the reading circuit and the current-voltage conversion circuit are performed in parallel. Therefore, the time required for one cycle is the time required for processing by each of the integrating circuit and the CDS circuit, and
Either the time required for processing by the readout circuit or the time required for processing by the current-voltage conversion circuit, whichever is longer, and higher-speed measurement is possible as compared with a conventional solid-state imaging device.

During the integration operation of the integration circuit, the charge corresponding to the difference between the output signals of the integration circuit at each of the first and second times indicated by the sample signal is C.
Since the data is held by the DS circuit, the influence of the offset variation of the amplifier of the integration circuit is removed, thereby enabling accurate light quantity measurement.

The present invention is applicable not only to the case where the light receiving section is formed of one photoelectric conversion element, but also to the case where the light receiving section is formed of a plurality of photoelectric conversion elements arranged in a one-dimensional or two-dimensional array. . In any case, the high-speed measurement and the elimination of the influence of the offset variation are achieved at the same time. In the latter case, an accurate optical image can be obtained.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram of a solid-state imaging device according to a first embodiment.

FIG. 2 is a timing chart illustrating the operation of the solid-state imaging device according to the first embodiment.

FIG. 3 is a circuit configuration diagram of a solid-state imaging device according to a second embodiment.

FIG. 4 is a circuit configuration diagram of a conventional solid-state imaging device.

[Explanation of symbols]

10 integration circuit, 20 CDS circuit, 30 readout circuit,
40 ... current-voltage conversion circuit, 50 ... timing control circuit,
100 _{1 to} 100 _M ... unit, A1 to A3 ... amplifier,
C1 to C5: capacitance element, Cp: parasitic capacitance, PD: photodiode, S1 to S9: switch element.

Claims (3)

[Claims] A light-receiving unit that outputs the current signal; and an amplifier and a capacitor that input the current signal output from the light-receiving unit. An integration circuit that is connected in parallel and accumulates and integrates the current signal in the capacitance element based on an instruction of a reset signal; a first terminal is connected to an output terminal of the integration circuit, and based on an instruction of the sample signal, A switch element for outputting, from a second terminal, first and second signal levels output from the integration circuit at first and second times during each integration operation period in the integration circuit; and a clamp signal. A CDS circuit that holds and outputs a signal corresponding to the difference between each of the first and second signal levels output from the second terminal of the switch element based on the instruction of A read circuit for reading a signal output from the CDS circuit as a charge amount based on an instruction of a hold signal; a current-voltage conversion circuit for converting the charge amount read by the read circuit into a voltage signal; A solid-state imaging device comprising: a timing control unit that outputs each of the reset signal, the sample signal, the clamp signal, and the hold signal at a predetermined timing. 2. The light receiving unit includes two or more predetermined number of photoelectric conversion elements, and outputs current signals from each of the predetermined number of photoelectric conversion elements. The integration circuit, the switch element, the CDS circuit, The readout circuit is provided for each of the predetermined number of photoelectric conversion elements, and the readout circuit further includes:
A signal output from the CDS circuit is read out as a charge amount at different timings for each of the predetermined number of photoelectric conversion elements, and the timing control unit further outputs the scan signal at a predetermined timing. The solid-state imaging device according to claim 1. 3. The light receiving section includes a predetermined number of photoelectric conversion elements two-dimensionally arranged in M rows and N columns. For each of the M rows, N photoelectric conversion elements in each row are specified based on an instruction of a first scan signal. Outputting current signals from the conversion elements at mutually different timings, wherein the integration circuit, the switch element, the CDS circuit, and the readout circuit are provided for each of the rows of the N photoelectric conversion elements in the light receiving unit. The readout circuit further includes a timing different from each other for each row of the N photoelectric conversion elements in the light receiving unit based on an instruction of a second scan signal.
The signal output from the CDS circuit is read as a charge amount, and the timing control unit further outputs each of the first and second scan signals at a predetermined timing. Solid-state imaging device.