JPH10336523A - Photoelectric converter and solid-state image-pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain high resolution by increasing the number of light-receiving sections capable of being arranged per unit length, so as to increase the density of the arrangement with respect to the photoelectric converter. SOLUTION: Light-receiving sections 31,... are arranged at a prescribed pitch P4,..., and transfer gate sections 35,... are arranged at the same pitch as the pitch P4,.... Electrodes 34 formed on a transfer path 33 provided along the arrangement direction of the light-receiving sections 31,... are arranged at the same pitch as the pitch P4,.... A pulse-generating circuit 31 gives drive pulse signals ϕ1-ϕ4 to the transfer gate sections 35,... and the electrodes 34,... selectively in a desired timing, and the timing when the signal charge is outputted from each light-receiving section 31 is adjusted. In this case, one transfer gate section 35 and one electrode 34 have only to be made corresponding to one transfer gate section 35, and the size of the one light-receiving section 31 is decreased to a degree of the width of the one electrode 34 for attaining high density arrangement.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a CCD type photoelectric conversion device and a solid-state imaging device, and more particularly to a line sensor in which light receiving portions are arranged in a one-dimensional line.

[0002]

2. Description of the Related Art Heretofore, in a solid-state imaging device using a CCD, an attempt has been made to increase the number of pixels (light receiving portions) arranged per unit area to thereby improve the resolution. . In order to improve the resolution, in a line sensor in which the pixels (light receiving units) are arranged in a one-dimensional line, more pixels (light receiving units) are arranged in the arrangement direction (line direction) to achieve the high resolution. Is achieved.

A layout of a pixel (light receiving section 11) and a charge transfer section 12 arranged adjacent to the pixel in a conventional line sensor will be described below with reference to FIG. In FIG. 21, in order to simplify the description, among the many light receiving units 11 of the line sensor 10, particularly three light receiving units 11-1 and 11-
2, 11-3 are shown.

In this line sensor 10, each light receiving section 11
-1, 11-2, 11-3 are arranged in the line direction at predetermined pitches P1, P1,..., And are adjacent to the light receiving sections 11-1, 11-2, 11-3 and charge transfer along the arrangement direction. A part 12 is provided. The charge transfer section 12 includes a transfer path 13 and a plurality of electrodes 14 (in the illustrated example, twelve electrodes 14-1 and 14-1).
-2,..., 14-12) and the electrode 14 (14-1, 14-)
2,..., 12-12), when a predetermined voltage is supplied, a potential well having a certain depth is formed in the transfer path 13 below the electrode 14 having the predetermined voltage.

A predetermined voltage is supplied at the time of forming a potential well by driving a four-phase driving pulse signal φ from a pulse generation circuit (not shown).
1 to φ4 are connected to these electrodes 14 (14-1, 14-2,.
It is performed by supplying to 2). In this case, the pulse generating circuit includes a plurality of electrodes 14 (14-1, 14-2,..., 14).
-12), the four-phase drive pulse signals φ1 to φ4 having different timings at which a predetermined potential is obtained are selectively supplied, whereby the potential well formed in the transfer path 13 is moved in the transfer path 13. Can be done.

In such a four-phase driven line sensor 10, the transfer paths 1 are transmitted from all the light receiving units 11 at a fixed timing.
3, the signal charge is transferred to an empty potential well. Therefore, the same number of independent potential wells as the light receiving portions (pixels) 11 must be formed in the transfer path 13 during transfer. Therefore, in the four-phase drive line sensor 10,
As shown in FIG. 21, four electrodes 14 are arranged in a line direction with respect to one light receiving unit (pixel) 11 (electrodes 14-1 to 14-4 corresponding to light receiving unit 11-1; Part 11-2
(Electrodes 14-5 to 14-8, corresponding to the light receiving portion 11-3).

In order to transfer signal charges from each light receiving section 11 to a potential well, one transfer gate section 15 is provided for one light receiving section 11. In the illustrated line sensor 10, the transfer gate unit is formed integrally with one of the four electrodes 14 arranged for one light receiving unit 11 (for example, the light receiving unit 11-). For 1, the transfer gate section 15-1) is connected to the electrode 14-1.

As described above, in the four-phase drive line sensor 10, since four electrodes 14 must be provided for one light receiving portion 11, the light receiving portion 11 may be made smaller to increase the density. However, the width (machining dimension) of four electrodes 14 arranged in the line direction with respect to one light receiving unit 11 hindered the high-density arrangement of the light receiving units 11 in the line sensor 10. .

In such a four-phase driven line sensor, as shown in FIG. 22, two electric charges are provided on both sides of the light receiving sections 21, 21... Line sensor 2 provided with transfer units 22
0 has been proposed. The line sensor 20 has a structure in which signal charges generated and accumulated in the light receiving units 21 and 21 adjacent to each other are distributed to different charge transfer units 22 and 22 and transferred in the potential well. . Therefore, the line sensor 20 has one light receiving unit 21 on one side as compared with the line sensor 10 shown in FIG.
It is only necessary to dispose two electrodes 24, 24 (in the illustrated example, for example, the electrode
3, 24-14, electrodes 24-1 and 24-2 on the lower side), light receiving unit 2
The pitch P2 of the light receiving units 21, 21,... Is set to about half of the pitch P1 of the line sensor 10 shown in FIG.
.. Can be arranged at twice the density. Incidentally, FIG.
Reference numeral 25 denotes a transfer gate unit.

[0010]

However, with the recent advancement of image processing technology, the demand for higher resolution in line sensors has been increasing, as described above. As shown in the line sensor 20 shown in FIG. 1, two electrodes are arranged in the arrangement direction (line direction) for one light receiving unit 21.
There is a limit in reducing the processing size of the electrode 24, and the pitch width of the light receiving section 21 in the arrangement direction cannot be narrower than the width of the two electrodes, which has hindered high density. .

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and aims to increase the number of light receiving sections that can be arranged per unit length, increase the density of the light receiving sections, and achieve high resolution. It is an object of the present invention to provide a photoelectric conversion device and a solid-state imaging device that can perform the above-described operations.

[0012]

According to a first aspect of the present invention, there is provided a photoelectric conversion device, comprising: a plurality of light receiving portions arranged at a predetermined pitch; A plurality of transfer gates arranged at a pitch equal to a predetermined pitch, a transfer path provided along an arrangement direction of the plurality of transfer gates, and a plurality of transfer gates arranged at a pitch equal to the predetermined pitch on the transfer path. And a charge transfer unit comprising: a plurality of electrodes, wherein the plurality of transfer gates and the plurality of electrodes selectively drive pulses to the plurality of transfer gates and the plurality of electrodes, and at a desired timing. Driving means for supplying is connected.

The photoelectric conversion device according to claim 2, wherein the transfer gate portion and the electrode corresponding to the transfer gate portion are formed integrally, and the transfer gate portion and the electrode formed integrally therewith. A first well forming a potential well below the electrode from the driving means;
, A second potential for turning on the transfer gate portion, and a third drive pulse of a third potential that does not form a potential well under the electrode are selectively supplied at desired timing. Things.

The photoelectric conversion device according to claim 3, wherein the plurality of light receiving units are alternately divided into three or more stages in the order of arrangement, and the transfer units adjacent to the light receiving units in each stage are individually adjacent to each other. The gate section and the electrode corresponding to the gate section are connected to individual signal lines for each stage, and drive pulses having different phases for each stage are supplied from the driving means via the signal line to the transfer gate section and the electrode. It is supplied to.

According to a fourth aspect of the present invention, in the photoelectric conversion device, the plurality of light receiving units are divided into four stages, and the plurality of transfer gate units and the plurality of electrodes are phase-shifted from the driving unit for each stage. Are supplied. A solid-state imaging device according to a fifth aspect uses the photoelectric conversion device according to any one of the first to fourth aspects, and the solid-state imaging device further includes the plurality of transfer gate units and the plurality of the plurality of transfer gate units. The driving unit that supplies the driving pulse to the electrode, a storage unit that stores optical signals from the respective light receiving units sequentially output from the photoelectric conversion device, and an optical signal stored in the storage unit is rearranged. And an image generation unit for generating image information.

According to a sixth aspect of the present invention, there is provided a photoelectric conversion device comprising: a plurality of light receiving units arranged at a predetermined pitch; and a plurality of light receiving units arranged adjacent to each of the plurality of light receiving units at a pitch equal to the predetermined pitch. A first transfer gate section, a plurality of charge storage sections individually adjacent to the plurality of first transfer gate sections, and a plurality of charge storage sections individually adjacent to each other and arranged at a pitch equal to the predetermined pitch. A plurality of second transfer gate portions, a transfer path provided along an arrangement direction of the plurality of second transfer gate portions, and a plurality of electrodes arranged on the transfer path at a pitch equal to the predetermined pitch. And a plurality of first transfer gates, the plurality of second transfer gates, and the plurality of electrodes, the plurality of first transfer gates, Alternatively the drive pulses to the plurality of second transfer gate portion and the plurality of electrodes, and one in which the drive means is connected to supply at a desired timing.

Further, in the photoelectric conversion device according to the present invention, the second transfer gate portion and the electrode corresponding to the second transfer gate portion are integrally formed, and the second transfer gate portion is formed integrally with the second transfer gate portion. A second potential for forming a potential well under the electrode, a second potential for turning on the second transfer gate, and a second potential for the second transfer gate and the electrode. Ternary drive pulse of a third potential which does not form a potential well under the third potential is supplied selectively and at a desired timing.

In the photoelectric conversion device according to the present invention, the plurality of first transfer gate sections may be supplied with a fourth potential for turning on the first transfer gate sections at the same timing from the driving means. Is supplied. Further, the photoelectric conversion device according to claim 9 is
The plurality of light receiving units are divided into three or more stages alternately in the order of arrangement, and the second transfer gate unit and the electrode corresponding to each of the light receiving units in each stage are provided with individual signal lines for each stage. And a driving pulse having a different phase for each stage is supplied from the driving unit to the second transfer gate unit and the electrode via the signal line.

The photoelectric conversion device according to claim 10 is
The plurality of light receiving units are divided into four stages, and four driving pulses having different phases for each stage are supplied from the driving unit to the plurality of second transfer gate units and the plurality of electrodes. is there. The solid-state imaging device according to claim 11 uses the photoelectric conversion device according to any one of claims 6 to 10, and further includes the solid-state imaging device, wherein the solid-state imaging device includes the plurality of first transfer gate units, A driving unit for supplying the driving pulse to the plurality of second transfer gate units and the plurality of electrodes; and a storage unit for storing optical signals from the respective light receiving units sequentially output from the photoelectric conversion device. And an image generation unit for rearranging the optical signals stored in the storage unit to generate image information.

Further, the photoelectric conversion device according to claim 12 is
A plurality of light receiving portions arranged at a predetermined pitch, a plurality of transfer gate portions individually adjacent to the plurality of light receiving portions and arranged at a pitch equal to the predetermined pitch, and along a direction in which the plurality of transfer gate portions are arranged; And a charge transfer unit including a plurality of electrodes disposed at a pitch equal to the predetermined pitch on the transfer path, and connected to at least the plurality of transfer gate units by individual signal lines. A drive unit for selectively supplying drive pulses to the plurality of transfer gate units and the plurality of electrodes at a desired timing, wherein the drive unit has a first potential at different timings from each other. The second drive pulse is distributed to the plurality of electrodes to form a plurality of independent potential wells under the electrodes,
By adjusting the timing at which the distributed second drive pulse becomes the first potential, the plurality of independent potential wells are sequentially moved in the transfer path, and the plurality of transfer gates are arranged in the order of arrangement. Supplying a first drive pulse having a second potential via the individual signal line at a timing at which the transfer gate portion and the sequentially moving empty potential well are adjacent to each other to turn on the transfer gate portion. Thus, the signal charges accumulated in the light receiving section are sequentially transferred to the empty potential well.

Further, the photoelectric conversion device according to claim 13 is:
The plurality of light receiving units are divided into three or more stages alternately in the order of arrangement, and the driving unit applies at least the electrodes corresponding to the light receiving units of each stage to the electrodes at different timings for each stage. The second drive pulse for supplying a potential of 1 is supplied. Further, in the photoelectric conversion device according to claim 14, the transfer gate portion adjacent to each of the plurality of light receiving portions and the electrode corresponding to the transfer gate portion are integrally formed, and the driving unit includes A third drive pulse in which the first drive pulse and the second drive pulse are superimposed is supplied to the transfer gate portion and the electrode formed integrally.

Further, the photoelectric conversion device according to claim 15 is:
A plurality of light receiving portions arranged at a predetermined pitch; a plurality of first transfer gate portions individually adjacent to the plurality of light receiving portions and arranged at a pitch equal to the predetermined pitch; and the plurality of first transfer gates A plurality of charge storage units individually adjacent to the unit, a plurality of second transfer gate units individually adjacent to the plurality of charge storage units and arranged at a pitch equal to the predetermined pitch, and A charge transfer section including a transfer path provided along the transfer gate section arrangement direction and a plurality of electrodes arranged on the transfer path at a pitch equal to the predetermined pitch; and at least the plurality of second transfer gates And a plurality of second transfer gates and the plurality of electrodes are selectively supplied at desired timings to the plurality of second transfer gates and the plurality of electrodes. A driving unit, wherein the driving unit distributes two or more types of second driving pulses having a first potential to the plurality of electrodes at different timings from each other, and provides a plurality of independent potentials below the electrodes. Forming a well, adjusting the timing at which the distributed second drive pulse becomes the first potential, sequentially moving the independent potential wells within a transfer path, and The first drive pulse which becomes the second potential at the timing when the second transfer gate portion and the sequentially moving empty potential well are adjacent to each other in the arrangement order of the transfer gate portions is transmitted via the individual signal line. And the second transfer gate is turned on, whereby the signal charges respectively stored in the charge storage unit from the light receiving unit via the first transfer gate unit are transferred to the empty charge. One in which sequentially transferred to the well.

Further, the photoelectric conversion device according to claim 16 is
The drive means supplies a drive pulse having a fourth potential to turn on the first transfer gate unit to the plurality of first transfer gate units at the same timing. Further, in the photoelectric conversion device according to the seventeenth aspect, the plurality of light receiving units may have at least three
The driving means is divided into at least two stages, and the driving means applies the second driving pulse which becomes the first potential at a timing different for each stage to at least the electrodes respectively corresponding to the light receiving portions of the respective stages. Supply.

Further, the photoelectric conversion device according to claim 18 is
A second transfer gate unit and the electrode respectively corresponding to each of the plurality of light receiving units are integrally formed, and the driving unit applies the first transfer gate unit and the electrode to the integrally formed transfer gate unit and the electrode. A third drive pulse in which the drive pulse and the second drive pulse are superimposed is supplied.

(Operation) According to the first aspect of the present invention, one electrode and one transfer gate are arranged for each light receiving section, and the driving means connected to the electrode and the transfer gate operates. By making the timings at which the signal charges are transferred from the plurality of light receiving sections to the transfer path different from each other, the number of light receiving sections to transfer the signal charges to the transfer path at the same timing can be reduced. Therefore, the number of potential wells that must be formed in the transfer path can be reduced, and the number of electrodes to be arranged for one light receiving unit can be set to one. At this time, the signal charge from the light receiving unit is not mixed with the signal charge from the other light receiving units, and the width of the light receiving unit is reduced by one by the number of electrodes that must be provided for one light receiving unit. The width of the electrodes can be reduced to about the width, and the number of light receiving sections that can be arranged per unit length can be increased.

According to the second aspect of the present invention, the transfer gate portion and the electrode can be easily formed,
By making the drive pulse supplied from the drive unit to the transfer gate unit and the electrode formed as one unit a common ternary drive pulse, the configuration of the drive unit can also be simplified. According to the third aspect of the present invention,
Even when one electrode and one transfer gate are provided for each light receiving unit, the light receiving unit is divided into three or more stages, so that the electrodes and the transfer gates corresponding to the light receiving units divided into three or more stages are provided. By supplying drive pulses to the section at different timings of the second potential for each stage, independent potential wells can be formed on the transfer path by the number of light receiving sections included in each stage. Thus, signal charges can be transferred to the independent potential wells from the light receiving section included in one stage at a time.

According to the fourth aspect of the present invention, the light receiving section is provided
By dividing into two stages, the electrode and the transfer gate portion divided into four stages corresponding to the light receiving portion can be easily formed as a two-layer structure. According to the fifth aspect of the present invention, even when an optical signal is output from the photoelectric conversion device in an order different from the arrangement order of the light receiving units, the optical signals are rearranged in the arrangement order of the light receiving units. , Images can be generated.

According to the present invention, a charge storage section is provided between the light receiving section and the transfer path, and a first transfer gate section is provided between the light receiving section and the charge storage section. A second transfer gate unit is provided between the charge storage unit and the transfer path, and the first drive unit operates first by the operation of the driving unit.
To turn on the transfer gate section and temporarily accumulate the signal charges generated by the light receiving section in the charge accumulating section at a desired timing, and thereafter, turn on the second transfer gate section at a desired timing and thereby accumulate the signal charges. The timing at which the signal charges are transferred from the unit to the transfer path can be different from each other. As a result, it is possible to reduce the number of light receiving sections where signal charges are transferred from the charge storage section to the transfer path at the same timing, and to reduce the number of potential wells that must be formed in the transfer path. Thus, by adjusting the timing at which the signal charge from the light receiving unit is transferred to the transfer path, even if the number of electrodes to be arranged for one light receiving unit is 1, the signal charge from the other light receiving unit is mixed. Disappears. In this case, the width of the light receiving section can be made about the width of one electrode, and the number of light receiving sections that can be arranged per unit length can be increased. In addition, the timing of transfer from each light receiving section to the charge storage section can be adjusted by the timing at which the first transfer gate section is turned on, so that the charge storage period in each light receiving section can be adjusted.

According to the seventh aspect of the present invention, the second transfer gate portion and the electrode can be easily formed, and the second transfer gate portion and the electrode formed integrally with the second transfer gate portion and the electrode. By making the drive pulse supplied from the means a common ternary drive pulse, the configuration of the drive means can be simplified. According to the eighth aspect of the present invention, by simultaneously transferring signal charges from the light receiving section to the charge storage section, the charge accumulation period in each light receiving section can be made constant.

According to the ninth aspect of the present invention, even when one electrode and one second transfer gate are provided for each light receiving portion, the light receiving portion is divided into three or more stages, and By simply supplying a driving pulse having at least a different timing to the second potential to the electrode corresponding to the light receiving portion and the second transfer gate portion for each stage, the number of light receiving portions included in each stage in the transfer path and The same number of independent potential wells will be formed.

According to the tenth aspect of the present invention, by dividing the light receiving portion into four stages, the electrode and the second transfer gate portion corresponding to the light receiving portion in each stage can be formed in a two-layer structure. it can. According to the eleventh aspect of the present invention, even when an optical signal is output from the photoelectric conversion device in an order different from the arrangement order of the light receiving sections, the optical signals are rearranged in the arrangement order of the light receiving sections. , Desired image data can be generated.

According to the twelfth aspect of the present invention, the light receiving section 1
By arranging one electrode and one transfer gate unit each, and making the timing at which signal charges are transferred from the plurality of light receiving units to the transfer path from the driving means different for each light receiving unit, the transfer path is changed. The signal charges from the light receiving unit can be transferred to the potential well at a timing adjacent to the light receiving unit in the order of their arrangement. As a result, even if the number of electrodes to be arranged for one light receiving unit is 1, signal charges from a specific light receiving unit can be transferred in the transfer path without being mixed with signal charges from other light receiving units. Therefore, the number of electrodes that must be provided for one light receiving unit can be set to one, and the width of the light receiving unit can be set to about the width of one electrode, and the number of light receiving units that can be arranged per unit length can be increased. it can.

According to the thirteenth aspect of the present invention, the timing at which the second drive pulse supplied to each stage becomes the second potential is made different for each stage, so that a plurality of independent drive pulses are provided. A potential well can be formed in the transfer path and moved. According to the invention of claim 14, the transfer gate portion and the electrode can be easily formed, and the drive pulse supplied from the driving means to the transfer gate portion and the electrode formed integrally is By using a common ternary drive pulse, the configuration of the drive unit can be simplified.

According to the fifteenth aspect of the present invention, a charge storage section is provided between the light receiving section and the transfer path, and a first transfer gate section is provided between the light receiving section and the charge storage section.
A second transfer gate section is provided between the charge storage section and the transfer path, and the first transfer gate section is first turned on by the operation of the driving means to convert a signal charge generated in the light receiving section into a desired signal. The charge is temporarily stored in the charge storage section, and then the second transfer gate section is sequentially turned on, so that the timing at which the signal charge is transferred from the charge storage section to the transfer path is different from the arrangement order of the light receiving sections. be able to. As a result, the number of potential wells that must be formed in the transfer path can be reduced. In this case, even if the number of electrodes to be arranged for one light receiving unit is 1, it does not mix with the signal charges from other light receiving units, and the width of the light receiving unit can be reduced to about the width of one electrode. It is possible to increase the number of light receiving sections that can be arranged at one end.
In addition, the timing of transfer from each light receiving section to the charge storage section can be adjusted by the timing at which the first transfer gate section is turned on, so that the charge storage period in each light receiving section can be adjusted.

According to the sixteenth aspect of the present invention, by simultaneously transferring signal charges from the light receiving section to the charge storage section, the charge accumulation period in each light receiving section can be made constant. According to the seventeenth aspect of the present invention, even when one electrode and one second transfer gate are provided for each light receiving portion, the light receiving portion is divided into three or more stages, and the light receiving portion of each stage is provided. And the second transfer gate section at different timings for each stage.
By supplying the driving pulse having the potential of (i), the same number of independent potential wells as the number of light receiving sections included in each stage can be formed in the transfer path.

According to the eighteenth aspect of the present invention, the second
And the driving pulse supplied from the driving means to the integrally formed second transfer gate portion and the electrode can be formed by a common ternary driving pulse. By using pulses, the configuration of the driving unit can be simplified.

[0037]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. Note that the first embodiment corresponds to claims 1 to 5.

FIG. 1 shows a line sensor (photoelectric conversion device) 30.
FIG. 2 is a cross-sectional view taken along the line II-II of FIG. 1, FIG. 3 is a cross-sectional view taken along the line III-III of FIG.
FIG. 4 is a cross-sectional view showing an output unit 30D of the line sensor 30,
FIG. 5 is a block diagram showing the overall configuration of the solid-state imaging device 50 using the line sensor 30, and FIG.
FIG. 7 is a timing chart showing the waveforms of the drive pulse signals φ1 to φ4 supplied to the CD transfer electrodes 39-1 to 39-4. FIG. 7 shows the timing chart when the drive pulse signals φ1 to φ4 shown in FIG. Are explanatory diagrams showing potential wells W, W.

The line sensor 30 of the first embodiment includes:
As shown in FIG. 1, a plurality (twelve in the illustrated example) of light receiving units 31-1, 31-2, 31-3... 31-12 are provided. 2,31-3 ... 31-12
Are arranged in the line direction at predetermined pitches P4, P4,. Further, a plurality of light receiving sections 31-1, 31-2, 31-3,.
The transfer paths 33 are arranged along the two array directions (the horizontal direction in FIG. 1).
Is formed on the transfer path 33 and the predetermined pitch P
The electrodes 34-1, 34-2 ..., 34 at the same pitch as 4, P4 ...
-12 are arranged.

Further, a plurality of light receiving sections 31-1, 31-2, 31-3
... 31-12 and the electrodes 34-1, 34-2 ..., 34-
12 between the transfer gates 35-1, 35-2, 35-3,... 3 at a pitch equal to the predetermined pitch P4, P4,.
5-12 are provided. In this case, the electrodes 34-1 and 34-
, 34-12 and the transfer path 33 constitute a charge transfer section 32.

In the line sensor 30 of the first embodiment, the electrodes 34-1, 34-2,..., 34-12 and the transfer gates 35-1, 35-2, 35-3,. Are the same conductive layer (polycrystalline silicon film 42 shown in FIG. 2)
Are formed integrally. By the way, in the line sensor 30 of the first embodiment, the plurality of light receiving sections 31-1, 3
.., 31-12 are divided into four stages (first to fourth stages) alternately in the arrangement order. That is,
The light receiving sections 31-1, 31-5, and 31-9 are the first stage, and the light receiving sections 31-
2, 31, 6 and 31-10 are the second stage, and the light receiving sections 31-3, 31-7,
Reference numeral 31-11 designates a third stage, and light receiving units 31-4, 31-8, and 31-12 constitute a fourth stage.

Further, the light receiving section 31-1, divided into four stages,
31-2, 31-3,.
, 34-12 and transfer gate portions 35-1, 35-2, 35-3,.
Are divided into four stages (first to fourth stages) corresponding to the light receiving units 31-1, 31-2,... .., 34-12 and the transfer gate portions 35-1, 35-2, 35-3,..., 35-12 are individually provided for each stage. CCD transfer electrodes 39-1 to 39 through signal lines
Connected to -4.

In the line sensor 30 configured as described above, the signal shown in FIG. 5 is transmitted through the CCD transfer electrodes 39-1 to 39-4.
The four-phase driving pulse signals φ1 to φ4 from the pulse generating circuit (driving means) 51 are supplied to each stage (FIG. 6). Drive pulse signals φ1 to φ4 supplied at this time
Is a ternary drive pulse signal having an intermediate potential (first potential) VM, a highest potential (second potential) VH, and a lowest potential (third potential) VL.

The driving pulse signals φ1 to φ4
Are at the desired timing, the respective potential wells W, W,... (In the example shown in FIG. 3) are formed. The plurality of potential wells W, W... Are generated as the potentials of the drive pulse signals φ1 to φ4 supplied from the pulse generation circuit 51 change over time as shown in FIG.
As shown in FIG. 7, they move in the transfer path 33 while being independent from each other.

The transfer gates 35-1 and 35-3
The drive pulse signals φ1 to φ4 are also supplied to 5-2, 35-3... 35-12 for each stage. in this case,
The drive pulse signals φ1 to φ4 each have the highest potential VH at different timings (for example, in the timing chart of FIG. 6, φ1 is the timing of t1, φ2 is the timing of t3, φ3 is the timing of t5, and φ4 is the timing of t6. At the maximum potential VH), and at each timing, for each stage, the transfer gate units 35-1, 35-2, 35-3
..., 35-12 turns on.

As described above, the transfer gate section 35 (3
5-1, 35-2, 35-3,..., 35-12) are turned on at different timings for each stage, and the signal charges stored in the light receiving unit 31 via the transfer gate unit 35 turned on. Are transferred to the potential wells W, W,. The signal charges transferred from the light receiving sections 31, 31 to the potential wells W, W.
Are transferred as they move through the transfer path 33 as shown in FIG.

The signal charges generated and stored in the light receiving sections 31, 31... Are simultaneously transferred to the potential wells W, W. With the movement of the wells W, W,.
0 to the output unit 30D.
Output from That is, at the timing when the drive pulse signal φ1 becomes the highest potential VH, the first-stage light receiving units 31-1 and 31-
The signal charges from 5, 31-9 are transferred to the potential wells W, W... At a time, and then output from the output unit 30D. Next, at the timing when the drive pulse signal φ2 becomes the highest potential VH, the signal charges from the second-stage light receiving units 31-2, 31-6, 31-10 are temporarily transferred to the potential wells W, W.
Output from the output unit 30D.

Thereafter, similarly, at the timing when the drive pulse signal φ3 becomes the highest potential VH, the light receiving sections 31-3, 3-3 of the third stage are similarly operated.
The signal charges from 1-7, 31-11 are transferred to the potential wells W, W,... And output from the output unit 30D, and the driving pulse signal φ
4 at the timing when the potential 4 reaches the maximum potential VH.
The signal charges from 1-4, 31-8, 31-12 are transferred to potential wells W,
, And then output from the output unit 30D.

Next, the device structure of the line sensor 30 will be described with reference to FIGS. FIG. 2 is II of FIG.
FIG. 2 is a cross-sectional view taken along the line II. As shown in the figure, the p-type silicon substrate 41 has an n-type diffusion layer 41A forming the transfer path 33 and an n-type diffusion layer forming the light receiving section 31. Layer 41
B is formed. Also, the diffusion layers 41A and 41B
Between them, a p-type channel region 41C is formed.

On the upper surface of the p-type silicon substrate 41,
Polycrystalline silicon film 42 is formed via silicon oxide film 43. The polycrystalline silicon film 42 forms the electrode 34 of the line sensor 30 and the transfer gate unit 35. That is, a transistor is constituted by the diffusion layer 41A, the diffusion layer 41B, and a part (42A) of the polycrystalline silicon film 42, and a part (4
2A) becomes the transistor gate section 35. In addition, the polycrystalline silicon film 42 (42B) above the diffusion layer 41A constitutes the electrode 34. In the drawing, reference numeral 44 denotes a silicon oxide film, 45A denotes an aluminum film forming a light shielding portion, and 45B denotes an aluminum film forming a lead electrode. The polycrystalline silicon film 42 forming the electrode 34 has a two-layer structure as shown in FIG.

As shown in FIG. 4, a known floating diffusion amplifier is formed at the output section 30D of the line sensor 30. Here, the output MO is formed by the n-type diffusion layer 41D, the diffusion layer 41A, and the polycrystalline silicon film 42C formed on the p-type silicon substrate 41.
An S transistor is configured. Also, in the figure, reference numeral 46
A is an aluminum film constituting the output terminal OUT, 46B is an aluminum film connected to the constant voltage source VDD, and 47 is a polycrystalline silicon film constituting a reset gate. In this case, when a reset pulse is input to the polycrystalline silicon film 47, the signal charges from the light receiving section 31 are discharged to the constant voltage source VDD connected to the aluminum film 46B.

Next, a solid-state imaging device 50 using the above-configured line sensor 30 as a sensor section will be described with reference to FIG. As shown in FIG. 5, the solid-state imaging device 50 includes a pulse generation circuit 51 for outputting a four-phase drive pulse signal to the line sensor 30, a level correction circuit 52, and light receiving sections 31, 31. An asynchronous read / write memory (storage means) 54 for storing signals (optical signals corresponding to signal charges) sequentially output from each stage, and an address circuit 55 for determining the reading order of the stored optical signals. And an image processing device 56 that generates an image based on an optical signal read from the asynchronous read / write memory 54 based on an address signal from the address circuit 55. Note that the asynchronous read /
The write memory (storage unit) 54 and the image processing device 56 function as an image generation unit.

Here, the order of reading the optical signals stored in the output order in the asynchronous read / write memory 54 by the address circuit 55 is appropriately rearranged. In the line sensor 30, for example, the drive pulse signal φ1 is set to the maximum potential VH. When it becomes, the first stage light receiving units 31-1, 31-5, 31
-9, the signal charge generated and accumulated at one time is transferred to transfer path 3.
3 are transferred to empty potential wells W, W.
After that, the drive pulse signal φ2 becomes the highest potential VH, and the second-stage light receiving sections 31-1, 31-5, 31
-9, the signal charge generated and accumulated at one time is transferred to transfer path 3.
., 31-3, the signal charges output from the light receiving sections 31-1, 31-2, 31-3,. This is because they are output in order.

As shown by a broken line in FIG. 5, instead of the asynchronous read / write memory 54 and the address circuit 55,
A rearranging circuit 59 composed of a personal computer (not shown) or the like may be provided to rearrange the optical signals output for each stage, and then output to the image processing device 56. Next, the waveforms of the four-phase drive pulse signals φ1 to φ4 supplied to the line sensor 30 having the above configuration,
And the potential wells W, W...
Will be described with reference to FIGS. 6 and 7.

The electrodes 35-1 and 35-2 of the line sensor 30
, 35-12, as described above, each stage (first stage,
(2nd stage, 3rd stage, 4th stage), four-phase drive pulse signals φ1 to φ4 having different waveforms from each other are applied to the CCD transfer electrodes 39-1 to 3-4.
Supplied from 39-4. In FIG. 6, a period t1 to t2 is a period until the signal charges generated and accumulated in the first-stage light receiving units 31-1, 31-5, and 31-9 are transferred to the output unit 30D and output. is there.

Similarly, the signal charges generated and stored in the second-stage light receiving units 31-2, 31-6, and 31-10 during periods t3 to t4, and the third-stage light receiving units during periods t5 to t6. Parts 31-3, 31
-7, 31-11, the signal charges generated and accumulated in the period t
6 to t7 are periods until the signal charges generated and accumulated in the fourth-stage light receiving units 31-4, 31-8, and 31-12 are transferred to the output unit 30D and output.

As shown in FIG. 6, drive pulse signals φ1 to φ4 output from pulse generation circuit 51 are four-phase drive pulse signals having mutually different waveforms, and drive pulse signals φ1 to φ4 have the lowest potential. The timing from (third potential) VL to the intermediate potential (first potential) VM,
The timing of transition from the intermediate potential VM (first potential) to the highest potential (second potential) VH is different from each other.

In particular, the timing at which the drive pulse signals φ1 to φ4 are switched from the lowest potential VL to the intermediate potential VM is adjusted, and as shown in FIG. 7, the electrodes 34-1, 34-2, 3
A plurality of potential wells W, W... (Three in the illustrated example) are formed independently of each other in the transfer path 33 below 4-3,. The transfer path 3
3 are moved toward the output unit 30D independently of each other.

On the other hand, the drive pulse signals φ1 to φ4 rise to the highest potential VH at different timings (in this embodiment, from the intermediate potential VM to the highest potential VH).
Will be launched). That is, as shown in FIG. 7, three empty potential wells W, W, and W are formed independently of each other in the transfer path 33, and these three empty potential wells W move independently of each other in the transfer path 33. Empty potential wells W, W, W
At the timing (period t1 in FIG. 6) adjacent to the first-stage electrodes 34-1, 34-5, and 34-9, for example.
When 1 rises to the maximum potential VH, the first-stage transfer gates 35-1, 35-5, 35-9 are all turned on, and the first-stage light receiving units 31-1, 31-5, 31- are turned on. Generated at 9
The accumulated signal charges are simultaneously transferred to the transfer path 33.

The signal charges generated and accumulated in the first-stage light receiving sections 31-1, 31-5, and 31-9 during the period t2 reach the potential wells W, W, and W. It moves in the transfer path 33 while being accommodated in the inside, and thereafter is output from the output unit 30D. The first stage light receiving units 31-1, 31-5, 31
When all of the -9 signal charges are output from the output unit 30D, all the potential wells W, W, and W formed in the transfer path 33 become empty again.

Then, during the period t3, when the empty potential wells W, W, W are adjacent to the second-stage electrodes 34-2, 34-6, 34-10, the drive pulse signal φ2 is changed to the highest potential VH.
(Period t3). When the drive pulse signal φ2 rises to the maximum potential VH, the second-stage transfer gates 35-2, 35-6, and 35-10 are all turned on, and the second-stage light-receiving units 31-2, 31-. 6,31-10
Are transferred to the potential wells W, W, W in the transfer path 33 at the same time, and thereafter output from the output unit 30D until the period t4.

Similarly, the drive pulse signal φ3 is raised to the maximum potential VH in the period t5 shown in FIG. 6, whereby the third-stage transfer gate units 35-3 and 35-
7, 35-11 are all turned on, and the third-stage light receiving section 31-3,
The signal charges generated and accumulated in 31-7 and 31-11 are simultaneously transferred to the potential wells W, W and W in the transfer path 33, and thereafter output from the output unit 30D until the period t6. You.

Finally, when the drive pulse signal φ4 rises to the maximum potential VH in the period t6 and the transfer gates 35-4, 35-8, 35-12 of the fourth stage are all turned on, the fourth stage The signal charges generated and accumulated in the light receiving units 31-4, 31-8, and 31-12 are transferred to the potential wells W, W, and W in the transfer path 33, and thereafter, the output unit is operated until a period t7. Output from 30D.

By the series of operations described above, all the light receiving sections 31-1, 31-2,
The signal charges generated and accumulated in 31-12 are output from the output section 30D. When this series of operations is completed, the first-stage light receiving units 31-1, 31-5, and 31 are again activated.
-9, second stage light receiving units 31-2, 31-6, 31-10, third stage light receiving units 31-3, 31-7, 31-11, fourth stage light receiving unit 3
The signal charges generated and accumulated in the light receiving section 31 of each stage in the order of 1-4, 31-8, 31-12 are output for each stage.

As described above, this line sensor 3
0, for each stage, that is, the first stage light receiving units 31-1, 31
-5, 31-9, second-stage light receiving sections 31-2, 31-6, 31-1
0, the signal charges are read out from the light receiving units 31-3, 31-7, 31-11 of the third stage and the light receiving units 31-4, 31-8, 31-12 of the fourth stage, and the output units thereof are read out. A signal charge (optical signal) is output from each of the stages 30D from each stage. These output signal charges (optical signal) are output to an asynchronous read / write memory 54 and an address circuit 55 provided outside the line sensor 30.
The image processing device 56
The image is obtained in (FIG. 5).

As described in detail above, the line sensor 30 according to the first embodiment includes light receiving sections 31-1, 31-2, 31-3.
... at a pitch equal to the pitches P4, P4 ... at which 31-12 are arranged, and transfer gate portions 35-1, 35-2, 35-3,.
... and 35-12, and the pitches P4 and P4
The electrodes 34-1, 34-2, 34-3,... 3 at the same pitch as.
Since 4-12 are arranged, it is only necessary to provide one electrode 34 in the arrangement direction (line direction) for one light receiving unit 31. Therefore, a line sensor in which four electrodes are arranged for one light receiving portion in the line direction (FIG. 21)
And a line sensor 3 compared to a line sensor (FIG. 20) in which two electrodes are arranged in a line direction for one light receiving unit.
0 means that the light receiving portions (pixels) 31, 31,... Can be arranged at high density, and high resolution is achieved. If the number of pixels is the same, the size of the line sensor can be reduced. When the size is reduced in this way, the transfer distance of the signal charge is shortened, and the transfer efficiency is improved.

The light-receiving portions 31, 31... Can be formed in a desired direction by expanding the light-receiving portion 31 in a direction perpendicular to the line direction (vertical direction in FIG. 1) even if the width in the line direction becomes short. It can be an area. (Second Embodiment) Next, a second embodiment of the present invention will be described with reference to FIGS. This second embodiment corresponds to claims 6 to 11.

FIG. 8 is a plan view showing a layout of the line sensor 60, FIG. 9 is a sectional view taken along line IX-IX of FIG.
0 is a CCD transfer electrode 69-1 to 69-4 of the line sensor 60
5 is a timing chart showing the waveforms of the drive pulse signals φ1 to φ4 and the drive pulse signal TG supplied to FIG. The line sensor (photoelectric conversion device) 60 of the second embodiment
Are different from the line sensor 30 of the first embodiment in that the light receiving section 61 (61-1, 61-2, 61-3,.
3, the charge storage section 66 (66-1, 66-2, 66-
3, ... 66-12).

That is, as shown in FIG. 8, the line sensor 60 includes a plurality of (for example, 12) light receiving units 61 (61-1, 61-1).
61-12) are arranged at predetermined pitches P4, P4,..., And these light receiving sections 61-1, 61-2, 61-3,.
-12, a plurality of (12) charge storage units 66 (66-
1, 66-2, 66-3,... 66-12) are provided adjacent to each other. The first transfer gates 67 (67-1, 67-2, 67-3,..., 67) are arranged at a pitch equal to the predetermined pitches P4, P4.
-12).

The charge storage units 66-1, 66-2, 66-3,
, 66-12, corresponding to the individual ones, the electrodes 64 (64-64) are formed on the transfer path 63 at a pitch equal to the predetermined pitch P4, P4.
1, 64-2..., 64-12). , 64-12 and the corresponding electrode storage units 66-1, 66-2, 66-3,.
At a pitch equal to the predetermined pitches P4, P4.
2) second transfer gate units 65-1, 65-2,
65-3,... 65-12 are provided. The charge transfer section 62 is constituted by the transfer section 63 and the electrodes 64-1, 64-2,..., 64-12.

Also in the line sensor 60 of the second embodiment, the electrodes 64-1, 64-2,..., 64-12 and the second transfer gate portions 65-1, 65-2, 65-3,. 12
Are integrally formed in the same conductive layer (polycrystalline silicon film 72 in FIG. 9). Also, the light receiving units 61-1 and 61-2,
61-3 are divided into four stages (first to fourth stages) alternately in the arrangement order. In the illustrated example, the light receiving units 61-1, 61-5, and 61-9 are provided with four stages. First stage, light receiving units 61-2, 61
-6, 61-10 are the second stage, and the light receiving units 61-3, 61-7, 61-11
Is the third stage, and the light receiving units 61-4, 61-8, and 61-12 are the fourth stage.

The light receiving units 61-1 and 41-1 divided into four stages
61-2, 61-3... 61-12 corresponding to the electrodes 64-1,
64-2,..., 64-12 and the second transfer gate section 6
5-1, 65-2, 65-3,..., 65-12 are also divided into four stages (first to fourth stages) in accordance with this, and each stage has a CCD transfer electrode via an individual signal line. 69-1 to 69-4.

The first transfer gate portions 67-1, 67-2, 67-3,..., 67-12 are integrally formed of the same conductive layer (polycrystalline silicon film 74 in FIG. 9). It is connected to the signal line L6. In the line sensor 60 as well, the drive pulse signals φ1 to φ4 are supplied to the electrodes 64-1, 64-2,. You. These drive pulse signals φ1 to φ4 are ternary drive pulse signals having an intermediate potential (first potential) VM, a highest potential (second potential) VH, and a lowest potential (third potential) VL.

The first transfer gates 67-1, 67-2, 67-3...
The drive pulse signal TG supplied via the signal line L6
Is a binary drive pulse signal having a highest potential (fourth potential) VH2 and a lowest potential (fifth potential) VL2 (FIG. 1).
0). In the line sensor 60 thus configured, when the drive pulse signal TG reaches the maximum potential VH2 (t0 in FIG. 10), the first transfer gate units 67-1, 67-2, 67-. All of 3 ... 67-12 are turned on at a time, and each light receiving section 61-1, 61-2, 61-3 ... 61-12
Are simultaneously transferred to the charge storage units 66-1, 66-2, 66-3,... 66-12.

On the other hand, in the charge transfer section 62, the electrodes 64-1,.
64-2, 64-3,..., 64-12 are supplied with the four-phase drive pulse signals φ1 to φ4 having the intermediate potential VM at different desired timings for each stage. Are formed independently of each other.
The plurality of independent potential wells W, W... Correspond to the first potential wells as the potentials of the drive pulse signals φ1 to φ4 change with time (sequentially become intermediate potentials with time).
As in the case of the line sensor 30 according to the embodiment, the transfer path 63 is moved while being independent of each other.

Transfer gate sections 65-1, 65-2, 65 to which drive pulse signals φ1 to φ4 are supplied for each stage.
-3... 65-12, as the drive pulse signals φ1 to φ4 reach the maximum potential VH at desired timing (for example, in the timing chart of FIG. 10, φ1 is t1, φ2 is t3, φ3 is t5, φ4 is t6) Each stage turns on. At this time, the signal charges transferred to the charge storage units 66-1, 66-2, 66-3,..., 66-12 at a fixed timing (t0 in FIG. 10) are turned on for each stage. Through the gate portions 65-1, 65-2, 65-3 ..., 65-12,
Are transferred to the potential wells W, W... Adjacent to the transfer gate section 65 which is turned on.

The signal charges transferred to the potential wells W, W... Are transferred along the transfer path 63 as the potential wells W, W... Move (see FIG. 7), and thereafter output from the output unit 60D. Next, the device structure of the line sensor 60 will be described with reference to FIG. As shown in FIG. 9, on a p-type silicon substrate 71, an n-type diffusion layer 71A forming a transfer path 63 and an n-type diffusion layer 7 forming a light receiving portion 61 are provided.
1B and an n-type diffusion layer 71D constituting the charge storage section 66.
Are formed. Further, between the diffusion layers 71A and 71D and between the diffusion layers 71D and 71B,
Channel regions 71C, 71C are formed respectively.

On the upper surface of a p-type silicon substrate 71, polycrystalline silicon films 72, 74 are interposed via a silicon oxide film 73.
Are formed. Among them, the polycrystalline silicon film 72 is
The electrode 64 of the line sensor 30 and the second transfer gate unit 65 are configured. On the other hand, the polycrystalline silicon film 74
Constitute the first transfer gate section 67.

In this case, a transistor is formed by the diffusion layer 71A, the diffusion layer 71D and a part (72A) of the polycrystalline silicon film 72, and a part (7
2A) becomes the second transfer gate section 65. or,
Polycrystalline silicon film 72 (72B) above diffusion layer 71A
Becomes the electrode 64. Further, a transistor is constituted by the diffusion layer 71D, the diffusion layer 71B and the polycrystalline silicon film 74, and the polycrystalline silicon film 74 becomes the first transfer gate section 65.

In the figure, reference numeral 76 denotes a silicon oxide film, 7
5A is an aluminum film forming a light shielding portion, and 75B is an aluminum film forming a lead electrode. In the line sensor 60, a well-known floating diffusion amplifier similar to the output unit 30D of the line sensor 30 of the first embodiment is formed in the output unit 60D (see FIG. 4).

The signal charge output from the output unit 60D is converted into an optical signal as an optical signal in the same manner as the line sensor 30 of the first embodiment. ) Are sequentially output. Further, the overall configuration of the solid-state imaging device using the line sensor 60 includes a configuration of the line sensor 60 itself,
The second embodiment is different from the first embodiment only in that the drive pulse signal TG is output from the pulse generation circuit, and the other configuration is the same as that of the solid-state imaging device 50, and the description thereof is omitted.

Next, the driving pulse signals TG and 4 supplied from the pulse generation circuit to the line sensor 60 having the above configuration
FIG. 10 shows the waveforms of the phase drive pulse signals φ1 to φ4.
This will be described with reference to FIG. For the electrodes 65-1, 65-2,..., 65-12 provided on the line sensor 60, as described above, each stage (first stage, second stage, third stage, fourth stage) And four-phase drive pulse signals φ1 to φ4 having different waveforms from each other,
It is supplied from CCD transfer electrodes 69-1 to 69-4.

Incidentally, in the line sensor 60 of the second embodiment, as described above, the light receiving sections 61-1 and 61-
61-12 are simultaneously transferred to the charge storage units 66-1, 66-2, 66-3,..., 66-12. That is, in the period t0 in FIG.
First transfer gate sections 67-1, 67-2, 67-3,...
The drive pulse signal TG supplied to 67-12 rises to the highest potential VH2.

This drive pulse signal TG is at the highest potential VH2
., 67-12 are turned on at a time, and the respective light receiving units 61-1, 61-2, 61-3 are turned on at one time. The optical signals generated and stored in 61-12 are simultaneously and simultaneously charged at the same timing, and the charge storage units 66- provided in correspondence with the respective light receiving units 61-1, 61-2, 61-3,. 1, 66-2, 66-3, ... 66-1
Transferred to 2 and stored here.

Thereafter, in the periods t1 to t2, the signal charges accumulated in the first-stage charge accumulation units 66-1, 66-5, 66-9 are further transferred to the transfer path 63, and thereafter, the transfer paths 63 It moves inside and is output from the output unit 60D. Hereinafter, similarly, in the period t3 to t4, the second-stage charge storage units 66-2 and 66-2
6-6, 66-10, the signal charges accumulated in periods t5 to t
6, the signal charges stored in the third-stage charge storage units 66-3, 66-7, 66-11 are stored. During the period t6 to t7, the fourth-stage charge storage units 66-4, 66-8, 66- are stored. After the signal charges accumulated in the transfer unit 12 move in the transfer path 63, the output unit 60D
Output from

When the output of the signal charges of the first to fourth stages is completed, the process proceeds to the next cycle, and the drive pulse signal TG goes high again, and all the light receiving units 61-1 and 6-1
The signal charges generated and stored in 1-2,..., 61-12 are simultaneously transferred to the corresponding charge storage units 66-1, 66-2,. It is transferred to the path 63 and is transferred and output on the transfer path 63. Thereafter, this operation is repeatedly performed.

The operation of the line sensor 60 when the drive pulse signals φ1 to φ4 are supplied to the CCD transfer electrode of the line sensor 60 is the same as the operation of the line sensor 30 of the first embodiment. The description is omitted. As described above, in the line sensor 60, similarly to the line sensor 30 of the first embodiment, the optical signals obtained by the first-stage light receiving units 61-1, 61-5, and 61-9 are first used. Output, and then the second-stage light receiving sections 61-2, 61-6, 61-1
0, signal charges from the third-stage light receiving units 61-3, 61-7, 61-11 and the fourth-stage light-receiving units 61-4, 61-8, 61-12 are output as optical signals. Thus, the optical signals output from the line sensor 60 are rearranged by the asynchronous read / write memory and the rearrangement circuit (see FIG. 5) connected to the line sensor 60 to generate a desired image.

As described in detail above, the line sensor 60 according to the second embodiment includes light receiving portions 61-1, 61-2, 61-3.
.. At the same pitch as the pitches P4, P4,.
7-3 ... 67-12, charge storage units 66-1, 66-2, 66-3,
... 66-12, second transfer gate sections 65-1, 65-
2, 65-3,... 65-12, electrodes 64-1, 64-2, 64-3,
.. 64-12 are arranged, it is only necessary to make one electrode 64 correspond to one light receiving part 61, and therefore,
Compared to a conventional line sensor in which four electrodes are arranged for one light receiving section (FIG. 21) or a line sensor in which two electrodes are arranged on one side (FIG. 22), light receiving sections (pixels) are arranged at a higher density. Can be arranged. If the number of pixels is the same, the size of the line sensor can be reduced. When the size is reduced in this way, the transfer distance of the signal charge is shortened, and the transfer efficiency is improved.

Even if the width of the light receiving section 61 in the line direction is reduced, the light receiving section 61 is expanded in a direction perpendicular to the line direction (up and down direction in FIG. 8) so that the light receiving section has a desired area. be able to. The line sensor 60 according to the second embodiment includes light receiving units 61-1, 61-2, 61-3,.
-12, at the same timing (timing at which the drive pulse signal TG becomes the maximum potential VH2), the charge storage units 66-1, 66-2, 66- provided corresponding to each other.
, 66-12 are temporarily stored and then output for each stage via the transfer path 63. Therefore, when an image is generated by the image processing apparatus (see FIG. 5), .., 61-12 can be made the same, and a clear image can be obtained.

The highest potential VH2 of the drive pulse signal TG
May be set to the same value as the highest potential VH of the drive pulse signals φ1 to φ4. Also, the lowest potential VL2 of the drive pulse signal TG
May be set to the same value as the lowest potential VL of the drive pulse signals φ1 to φ4. Third Embodiment Next, a third embodiment of the present invention will be described with reference to FIGS. In addition, this third
Corresponds to claims 12 to 14.

Here, FIG. 11 is a plan view showing the layout of the light receiving sections 81,... Of the sensor section 80S which is a main part of the line sensor 80, FIG. 12 is a block diagram showing the entire configuration of the line sensor 80, and FIG. Output unit 80 of line sensor 80
14 is a circuit diagram showing a pulse generation circuit 88 of the line sensor 80. FIG.
FIG. 16 is a timing chart showing waveforms of various pulses input to the pulse generation circuit 88, and FIG. 17 is a circuit diagram showing the configuration of the circuit blocks N and D of the line sensor 80. 2,84-3, ... 84-12
Is a timing chart showing the waveforms of the drive pulse signals φ1 to φ12 supplied to the power supply. FIG. 18 shows potential wells W, W... Which move in the transfer path 83 when the drive pulse signals φ1 to φ12 shown in FIG. FIG.

As shown in FIG. 11, the line sensor (photoelectric conversion device) 80 of the third embodiment has a plurality of (twelve in the illustrated example) light receiving sections 81 (8) as shown in FIG.
1-1, 81-2, 81-3 ... 81-12) are the predetermined pitches P4, P
The transfer paths 83 are formed in the arrangement direction (line direction). On the transfer path 83, the electrodes 84 (84-1, 84-1,
, 84-12) are arranged, and a plurality of transfer gate portions 85 are provided between the light receiving portion 81 and the electrode 84.
(85-1, 85-2, 85-3... 85-12). Here, the transfer path 83 and the electrode 84 constitute a charge transfer section 82.

In this case, as in the first embodiment, the electrode 84 and the corresponding transfer gate portion 85 are formed of the same conductive layer (formed on a semiconductor substrate via a silicon oxide film). Formed polycrystalline silicon film). Then, the electrode 8 integrally formed
4-1, 84-2 ..., 84-12 and transfer gate section 8
.., 85-12 are respectively connected to the signal lines L1,
L2, L3, L4,.
8 is connected.

The pulse generating circuit 88 includes signal lines L1 to L
, 84-12 and the corresponding transfer gates 85-1, 85-2, 8
5-3... 85-12 are supplied with drive pulse signals φ1 to φ12.
Are three-valued drive pulse signals having an intermediate potential (first potential) VM, a highest potential (second potential) VH, and a lowest potential (third potential) VL at different timings (FIG. 17). ).

By the way, also in the third embodiment, the light receiving sections 81-1, 81-2, 81-3,.
Light receiving units 81-1, 81-5, 81-9 of the second stage, light receiving unit 8 of the second stage
1-2, 81-6, 81-10, third-stage light receiving section 81-3, 81-
7, 81-11, fourth stage light receiving section 81-4, 81-8, 81-12
In this way, it is divided into four stages, a first stage to a fourth stage. The drive pulse signals φ1 to φ12 output from the pulse generation circuit 88 rise from the lowest potential VL to the intermediate potential VM at the same timing for each stage (the drive pulse signals φ1, φ5, and φ9 are generated at the same timing). At the same timing, the driving pulse signals φ2, φ6, and φ10 have the same timing, the driving pulse signals φ3, φ7, and φ11 have the same timing, and the driving pulse signals φ4, φ8, and φ12 have the same timing at the intermediate potential VM).

In this case, the driving pulse signals φ1 to φ12
Is a drive pulse signal (four-phase drive pulse signal) that changes from the lowest potential VL to the intermediate potential VM at a different timing for each stage, and each of the light receiving sections 81-1, 81-2, 81-3,.
From the intermediate potential VM to the maximum potential VH at different timings
The driving pulse signal (12 kinds of driving pulse signals) rising to the above is superimposed on the driving pulse signal.

.., 84-12 and the corresponding transfer gate portions 85-1, 85-2, 85-3... 85 -1
This is because 2 and 1 are integrally formed. Then, actually, the transfer gate units 85-1, 85-2, 85-3 ... 8
When the drive pulse signals φ1 to φ12 (FIG. 17) are supplied to 5-12 and the electrodes 84-1, 84-2,..., 84-12, as shown in FIG. Are formed, and the potential wells W move in the transfer path 83 as the waveforms of the drive pulse signals φ1 to φ12 change with time.

As shown in FIG. 17, drive pulse signal φ1
To φ12 are transfer gate units 85-1, 85-2, 8
Since the highest potential VH is attained in the order of 5-3,.
.., 81-12.
The signal charge is output. As a result, when generating an image based on an optical signal, unlike the line sensor 30 of the first embodiment and the line sensor 60 of the second embodiment, it is not necessary to rearrange the optical signals.

Next, the overall configuration of the line sensor 80 will be described with reference to FIGS. As shown in FIG. 12, the line sensor 80 includes a sensor unit 80S, a pulse generation circuit 88, a reset circuit 80R, and an output unit 80D. Then, the output unit 80D includes FIG.
As shown in FIG. 3, a floating diffusion amplifier 89-1 is formed, to which a clamp circuit 89-2 and a sample hold circuit 89-3 are connected.

Next, a specific circuit configuration of the pulse generating circuit 88 for generating the driving pulse signals φ1 to φ12 will be described.
This will be described with reference to FIG. As shown in FIG. 14, the pulse generation circuit 88 includes a shift register 88A and two circuit blocks N and D. The start pulse ST and the clock pulse CLK are input to the shift register 88A.
8A, 12 types of pulse signals S1 to S12 falling sequentially for each of the light receiving sections 81-1, 81-2,.
Is output (FIG. 16).

Each of the light receiving sections 81-1, 81-2,.
Are provided in correspondence with the pulse signals S1 to S12 from the shift register 88A.
Gate pulse signal GT is input. .. From the circuit blocks N, N,.
... Pulse signals (first drive pulses) G1 to G12 rising at predetermined timings corresponding to 81-12 are output (FIG. 16).

The pulse signals G1 to G12 output from the circuit blocks N, N,.
... Circuit blocks D, D, and
Are input to one of the input terminals. The other input terminals of the circuit blocks D, D,... Receive four-phase external periodic signals V1 to V4. These external periodic signals V1 to V
4 is a four-phase drive pulse signal that falls from a high level to a low level at a predetermined timing (FIG. 16).

Here, the timing at which the external periodic signals V1 to V4 fall from the high level to the low level is the same as the timing at which the drive pulse signals φ1 to φ12 rise from the low level to the high level for each stage. The timing at which the signals V1 to V4 rise from the low level to the high level is the same as the timing at which the drive pulse signals φ1 to φ12 fall from the high level to the low level for each stage.

The above-mentioned circuit blocks D, D... Invert pulse signals (first drive pulses) G1 to G12 from the corresponding circuit blocks N, N. The driving pulse signals φ <b> 1 to φ <b> 12 are output by superimposing the resulting signal (second driving pulse) (FIG. 16). FIG. 15 is a circuit diagram showing a specific configuration of the circuit blocks N and D shown in FIG.

The pulse signal GT is input to the node n1 of the circuit block N. Further, pulse signals S1 to S12 are input to the node n2 from the shift register 88A.
Further, a constant voltage source (lowest potential VL) is connected to nodes n3, n4 and n5 of the circuit block N, and a constant voltage source (highest potential VH) is connected to nodes n6 and n7.

On the other hand, pulses V1 to V4 are input to the node n11 of the circuit block D for each stage,
12 is connected to a constant voltage source (lowest potential VL), a node n13 is connected to a constant voltage source (intermediate potential VM), and a node n14
Is connected to a constant voltage source (highest potential VH). As described above, in the circuit block N, the pulse GT and the pulse signal S1 from the shift register 88A are applied to the nodes n1 and n2.
To S12, the signal (pulse signal GT) input to the node n1 and the node n
Only when the signals (any one of the pulse signals S1 to S12) input to 2 are both low level, both the transistors Tr1 and Tr2 in the circuit block D are turned off and only the transistor Tr3 is turned on. That is, a signal for turning on the transistor Tr3 from the circuit block N (the signal G in FIG. 16).
1 to G12).

On the other hand, in the circuit block D, the node n11
, Four-phase external periodic signals V1 to V4 are input for each stage. As a result, the signal (V
1 to V4) is at a high level, a signal of the lowest potential VL is output from the output terminal OUT of the circuit block D.

Also, the signal (V1
To V4) is at a low level and the signal from the circuit block N (corresponding to any of the signals G1 to G12) is at a high level, the output terminal OU of the node circuit block D
T outputs a signal of the intermediate potential VM. Then, the signal (any of V1 to V4) input to the node n11
And a signal from the circuit block N (corresponding to any of the signals G1 to G12) is at a low level, a signal having the highest potential VH is output from the output terminal OUT of the node circuit block D.

As described above, from the circuit block D, the drive pulse signals of four layers having different timings of changing from the lowest potential VL to the intermediate potential VM for each stage, and the light receiving sections 81-1 and 81-1.
The driving pulse signals φ1 to φ12 superimposed with 12 types of pulse signals having different timings of reaching the highest potential VH for each of 81-2,. The drive pulse signals φ1 to φ12 are supplied from the respective circuit blocks D to the electrodes 84-1, 84-2,..., 84-12 corresponding to the respective light receiving sections 81-1 81-2, 81-3. , And transfer gate units 85-1, 85-2, 85-3,..., 85-12.

Next, the waveforms of the drive pulse signals φ1 to φ12 supplied to the sensor section 80S of the line sensor 80 having the above configuration and the potential wells W and
The signal charges transferred to W,.
This will be described with reference to FIG. Sensor unit 80S of line sensor 80
., 85-12 provided at the first stage, the second stage, the third stage, and the fourth stage, the timing at which the intermediate potential VM2 is attained. Are supplied via signal lines L1 to L12.

In the sensor section 80S receiving the driving pulse signals φ1 to φ12, a plurality of potential wells W,
(Three in the illustrated example) are formed, and the plurality of potential wells W, W,.
Move in 3. In this case, in the period t1, the signal charge of the first light receiving unit 81-1 is transferred to the potential well W, and is output from the output unit 80D by the next period t1 '.

Then, the potential well W capturing the signal charge of the first light receiving section 81-1 has passed, and the next empty potential well W is the transistor corresponding to the light receiving section 81-2 on the second surface. When adjacent to the gate section 85-2 (period t2), the signal charges accumulated in the light receiving section 81-2 are transferred to the empty potential well W, and then transferred to the output section 80D.

Thereafter, in the period t3, the third light receiving section 81
In the period t4, the signal charges are sequentially transferred to the empty potential well W in the transfer path 83, such as the signal charges stored in the fourth light receiving portion 81-4 in the period t4. ,
Thereafter, the light is output from the output unit 80D as an optical signal.

Then, the last (twelfth) light receiving section 81-1
2 is transferred to the potential well W, and the potential well W
However, after passing through the transistor gate unit 85-1 corresponding to the first light receiving unit 81-1, the process moves to the next cycle after waiting for this, and the signal charge of the first light receiving unit 81-1 again becomes It is transferred to the next empty potential well W, and thereafter, the second light receiving unit 8
Each of the light receiving sections 8 is referred to as 1-2, third light receiving section 81-3.
The signal charges in 1 are output from the output unit 80D in the arrangement order.

As described in detail above, the line sensor 80 according to the third embodiment includes light receiving sections 81-1, 81-2, 81-3.
., 84-12 are arranged at the same pitch as the pitches P4, P4,... At which 81-12 are arranged, and these light receiving sections 81-1, 81-2, 81 are arranged. -3 ... 81-12
, 84-12, and electrodes 84-1, 84-2, 84-3,.
Since the transfer gate portions 85-1, 85-2, 85-3,... 85-12 are arranged at the same pitch as the pitches P4, P4,.
4 only needs to correspond to each other, which is higher than that of a conventional line sensor (FIG. 19) in which four electrodes are arranged for one light receiving unit or a line sensor (FIG. 20) in which two electrodes are arranged on one side. Light receiving portions (pixels) can be arranged at the density. If the number of pixels is the same, the size of the line sensor can be reduced. When the size is reduced in this way, the transfer distance of the signal charge is shortened, and the transfer efficiency is improved.

Regarding the light receiving section 81, even if the width in the line direction becomes short, the light receiving section 81 is expanded in a direction perpendicular to the line direction (up and down direction in FIG. 11) to make the light receiving section a desired area. be able to. Also, different driving pulse signals φ1 to φ12 are supplied from the pulse generation circuit 88 to each of the light receiving sections 81-1 to 81-2... 81-12. Light receiving units 81-1, 81-2, 8
Transfer gate part 85- corresponding to 1-3 ... 81-12
1, 85-2, 85-3,... 85-12, the maximum potential V
Since H is output, an optical signal is output from the line sensor 80 in accordance with the arrangement of the light receiving units 81-1, 81-2, 81-3,. Therefore, unlike the line sensors 30 and 60 of the first and second embodiments, an asynchronous read / write memory and a rearrangement circuit are not required, and the entire device can be simplified.

(Fourth Embodiment) Next, a fourth embodiment of the present invention will be described with reference to FIGS.
This fourth embodiment is described in claims 15 to 18.
Corresponding to Here, FIG. 19 is a plan view showing a layout of the line sensor 90, and FIG.
Pulse signal T supplied to the transistor gate portion 97, the electrode 94, and the second transfer gate portion 95 of FIG.
G is a timing chart showing waveforms of drive pulse signals φ1 to φ12.

The line sensor 90 of the fourth embodiment
Is different from the line sensor 80 of the third embodiment in that a charge storage unit 96 is provided between the light receiving unit 91 and the transfer path 93. That is, as shown in FIG. 19, the line sensor (photoelectric conversion device) 90 of the fourth embodiment includes a plurality of (for example, 12) light receiving units 91-1, 91-2, and 91-3.
.. 91-12 are arranged at predetermined pitches P4, P4,..., And each of the light receiving sections 91-1, 91-2, 91-3,. , 96-2,96
-3,..., 96-12 are provided correspondingly.
A transfer path 93 is provided along the arrangement direction of 6-1, 96-2, 96-3,.

Further, a pitch equal to the predetermined pitches P4, P4,...
The first transfer gate units 97-1, 97-2, 97-3 ...
97-12 are provided. Also, on the transfer path 93, the electrodes 94- are arranged at the same pitch as the predetermined pitches P4, P4,... Corresponding to the charge storage sections 96-1, 96-2, 96-3,. , 94-12 are arranged.

Then, the charge storage sections 96-1, 96-2, 96
-3,... 96-12 and the corresponding electrodes 94-1 and 94-2
, 94-12, the second transfer gate section 9
5-1, 95-2, 95-3,... 95-12 are provided.
Also in the line sensor 90, the transfer path 93 is arranged adjacent to the second transfer gate sections 95-1, 95-2, 95-3,..., 95-12 in the arrangement direction (horizontal direction in FIG. 8).
Are formed. The electrodes 94-1, 94 are arranged on the transfer path 93 at a pitch equal to the predetermined pitch P4, P4.
, 94-12 are arranged to form the charge transfer section 92.

In this line sensor 90, the electrode 9
., 94-12 and second transfer gate sections 95-1, 95-2, 95-3,.
Is formed integrally with the same conductive layer (for example, a polycrystalline silicon film). Also, the light receiving sections 91-1, 91-2, 91-3 ...
91-12 are divided into four stages (first to fourth stages) alternately in the arrangement order.
91-5, 91-9 are the first stage, and the light receiving units 91-2, 91-6, 91
-10 is the second stage, light receiving units 91-3, 91-7, 91-11 are the third stage
The stage, the light receiving units 91-4, 91-8, and 91-12 are the fourth stage.

Further, the light receiving section 91-1 divided into four stages,
91-2, 91-3,.
94-2..., 94-12 and the second transfer gate section 9
.., 95-12 are correspondingly divided into four stages (first to fourth stages). .., 94-12 and the second transfer gate portions 95-1, 95-2, 95-3,..., 95-12 are respectively connected to the signal lines L1, L2, L3, A pulse generation circuit 98 is connected via L4 to L12.

The first transfer gates 97-1, 97-2, 97-3... 97-12 are actually integrally formed of the same conductive layer (for example, a polycrystalline silicon film). It is connected to a signal line L16 for supplying a drive pulse signal TG from a pulse generation circuit (not shown).

.., 94-12 are supplied from the pulse generation circuit 98 to the driving pulse signals φ1 to φ1 respectively.
φ12 is supplied. These drive pulse signals φ1 to φ1
Reference numeral 2 denotes a ternary drive pulse signal having a maximum potential (first potential) VH, an intermediate potential (second potential) VM, and a minimum potential (third potential) VL.

The drive pulse signal TG supplied from the pulse generation circuit (not shown) to the first transfer gate sections 97-1, 97-2, 97-3,... 97-12 has the highest potential (fourth potential). ) This is a binary drive pulse signal that becomes VH2 and the lowest potential (fifth potential) VL2. Note that the drive pulse signals φ1 to φ
The configuration of the pulse generation circuit 98 that generates the signal 12 is the same as that of the pulse generation circuit 88 of the third embodiment, and a detailed description thereof will be omitted.

The other components such as the output section 90D of the line sensor 90 are the same as those of the line sensor 80 shown in FIGS. 12 and 13, and the description thereof is omitted. In the line sensor 90 having such a configuration, when the drive pulse signal TG reaches the maximum potential VH, the first transfer gate sections 97-1, 97-2, 97-3,. Then, the signal charges corresponding to the incident light generated and stored in the respective light receiving units 91-1, 91-2, 91-3... 91-12 are simultaneously stored in the charge storage units 96-1, 96-2, 96. -3, ... transferred to 96-12.

In one charge transfer section 92, the electrodes 94-1 and 94-1
., 94-12, drive pulse signals φ1 to φ12 having the intermediate potential VM at different desired timings are supplied to the respective stages, and are independently provided in the transfer path 93. Are formed, and as the potentials of the drive pulse signals φ1 to φ12 change with time, like the line sensor 30 of the third embodiment, the plurality of potential wells W, W. The potential wells W move within the transfer path 93 while being independent of each other.

That is, in the period from t01 to t03 in FIG. 20, the first transfer gate units 97-1, 97-2,
When the driving pulse signal TG supplied to 97-3... 97-12 rises to the maximum potential VH2, all the first transfer gate units 97-1, 97-2, 97-3. , 91-1, 91-2, 91-3,.
The storage period of the signal charge in 2 becomes the same.

The charge storage units 96-1, 96-2,..., 9
The signal charges accumulated in 6-12 correspond to the driving pulse signals φ1 to φ1.
φ12 is sequentially transferred to the transfer path 93 at the timing of sequentially rising to the highest potential VH, similarly to the case of the line sensor 80 of the third embodiment, and is transferred by the transfer path 93, and then output from the output unit 90D. Is done. In this case, the period t
1, the signal charge of the first light receiving section 91-1 is transferred to the potential well W, and output from the output section 90D by the next period t1 '.

Next, in the period t2, the empty potential well W is set to the transistor gate portion 95 corresponding to the light receiving portion 91-2 on the second surface.
-2, the signal charges accumulated in the light receiving section 91-2 are transferred to the empty potential well W. Thereafter, in the period t3, the signal charges accumulated in the third light receiving section 91-3 are transferred. In the period t4, the signal charges of the respective light receiving units 91 are sequentially transferred to the empty potential well W in the transfer path 93, such as the signal charges accumulated in the fourth light receiving unit 91-4. The light is output from the output unit 90D as an optical signal.

The signal charge of the last (twelfth) light receiving section 91-12 is transferred to the potential well W, and the next empty potential well W
Is adjacent to the transistor gate section 95-1 corresponding to the first light receiving section 91-1. At this timing, the next cycle is started, and the signal charges of the first light receiving section 91-1 again become empty. Transferred to the potential well W, and thereafter, the second light receiving section 91
-2, the third light receiving section 91-3, etc.
Are output from the output unit 90D in the arrangement order.

As described in detail above, the line sensor 90 according to the fourth embodiment includes light receiving sections 91-1, 91-2, 91-3.
... at a pitch equal to the pitches P4, P4 ... at which 91-12 are arranged, and transfer gate portions 95-1, 95-2, 95-3,.
... 95-12 are arranged, and the pitches P4, P4
The electrodes 94-1, 94-2, 94-3,... 9 at the same pitch as.
Since 4-12 are arranged, one electrode 94 may be made to correspond to one light receiving unit 91. A line sensor in which four electrodes are arranged for one light receiving unit (FIG. 21)
Or a line sensor in which two electrodes are arranged on one side (Fig. 2
The light receiving units (pixels) can be arranged at a higher density than in 2). If the number of pixels is the same, the size of the line sensor can be reduced. When the size is reduced in this way, the transfer distance of the signal charge is shortened, and the transfer efficiency is improved.

Regarding the light receiving section 91, even if the width in the line direction is reduced, the light receiving section 91 is expanded in a direction perpendicular to the line direction (vertical direction in FIG. 19) so that the light receiving section has a desired area. be able to. The drive pulse signals φ1 to φ12 supplied from the pulse generation circuit 99 are supplied to the second transfer gate units 95-1, 95-2, 95-3,.
The light receiving units 91-1, 91-2, 91-3,.
An optical signal is output from the output unit 90D according to the 1-12 arrangement.

Further, the line sensor 9 of the fourth embodiment
0 indicates that signal charges from the respective light receiving sections 91-1, 91-2, 91-3... 91-12 are provided corresponding to each other at the same timing (timing at which the drive pulse signal TG becomes the maximum potential VH2). The charge storage units 96-1, 96-2, 96-3,.
-12, and then transferred to the potential wells W, W... In the transfer path 93 for each stage. Therefore, when one image is generated, each light receiving unit 91-1 is generated. , 91
-2, 91-3... 91-12, the same charge accumulation period can be used, and a clear image can be obtained.

The maximum potential VH2 of the drive pulse signal TG
May be set to the same value as the highest potential VH of the drive pulse signals φ1 to φ12. Also, the lowest potential VL of the drive pulse signal TG
2 may have the same value as the lowest potential VL of the drive pulse signals φ1 to φ12.

In the first to fourth embodiments, the light receiving portions 31, 61, 81, and 91 are formed by forming the n-type diffusion layer on the p-type semiconductor substrate. May be formed in the opposite manner. In this case, the charges 34, 6
4, 84, 94, the drive gate signals supplied to the transistor gate portions 35, 85 and the second transistor gate portions 65, 95 have waveforms of high level and low level with respect to the waveform of the above-described embodiment. May be reversed.

In the second and fourth embodiments, an n-type diffusion layer is formed on a p-type semiconductor substrate to form charge storage sections 66 and 9.
Although the structure 6 is used, these conductivity types may be reversed. In this case, the first transistor gate portions 67 and 9
The drive pulse signal supplied to 7 may have a waveform obtained by reversing the high level and the low level with respect to the waveform of the above-described embodiment.

In the first to fourth embodiments,
Although a line sensor in which light receiving units are arranged one-dimensionally has been described as an example, the present invention can be applied to a solid-state imaging device or the like in which light receiving units are arranged two-dimensionally in a matrix. In this case, it is possible to increase the density of the arrangement of the light receiving units in at least one direction.

[0139]

As described above, according to the first to fourth aspects of the present invention, one electrode and one transfer gate are provided for each light receiving section, and each light receiving section is provided by the driving means. By making the timings at which signal charges are transferred from the unit to the transfer path different from each other, the number of light-receiving portions where the signal charges are transferred to the transfer path at the same timing can be reduced. Then, the number of potential wells formed in the transfer path can be reduced, and by setting the number of electrodes to be arranged for one light receiving portion to one, one width (width in the line direction) of the light receiving portion 1
About the width of one electrode. As a result, the number of light receiving sections that can be arranged per unit length can be increased, and high resolution can be achieved by increasing the density of the light receiving sections. Further, the size of the photoelectric conversion device can be reduced.

According to a fifth aspect of the present invention, in the solid-state imaging device using the photoelectric conversion device according to any one of the first to fourth aspects, an optical signal from the photoelectric conversion device is transmitted to a light receiving section. Even if the light signals are not output in the arrangement order, these optical signals can be easily rearranged in the arrangement order of the light receiving sections, and a desired image can be obtained. According to the invention, the charge transfer section is provided between the light receiving section and the transfer path, and the first transfer provided between the light receiving section and the charge storage section. By turning on the gate unit at a desired timing by the driving unit, the charge accumulation period in each light receiving unit can be adjusted. Then, the second transfer gate section between the charge storage section and the transfer path is turned on by the driving means, and the timing at which the signal charges are transferred from the charge storage section to the transfer path is made different from each other. In addition, the number of light receiving sections in which signal charges are transferred to the transfer path at the timing can be reduced. Also in this case, since the number of potential wells formed in the transfer path can be reduced, the number of electrodes to be arranged for one light receiving unit can be set to one, and the width of the light receiving unit can be set to about the width of one electrode. . As a result, the number of light receiving sections that can be arranged per unit length is increased, and high resolution can be achieved by increasing the density of the light receiving sections. Further, the size of the photoelectric conversion device can be reduced.

In particular, according to the invention described in claim 8, a clear image can be obtained by keeping the timing of transfer from each light receiving section to the charge storage section constant. According to the eleventh aspect, in the solid-state imaging device using the photoelectric conversion device according to any one of the sixth to tenth aspects, an optical signal from the photoelectric conversion device is output in the arrangement order of the light receiving units. Even if it is not necessary, these optical signals can be easily rearranged in the arrangement order of the light receiving sections to obtain a desired image.

According to the twelfth to fourteenth aspects of the present invention, one electrode and one transfer gate are provided for each light receiving section, and the signal charges are transferred to the transfer path by the driving means. Can be made different for each light receiving unit, so that the potential wells independent of each other in the transfer path can transfer the signal charge to the potential well at a timing adjacent to the light receiving unit in the arrangement order. it can. Therefore, the number of electrodes to be arranged for one light receiving unit can be set to one, and the width of the light receiving unit can be set to about the width of one electrode. As a result, it is possible to increase the number of light receiving units that can be arranged per unit length, and achieve high resolution by increasing the density of the light receiving units. Further, the size of the photoelectric conversion device can be reduced.

According to the present invention, the signal charges from the light receiving section can be transferred to the charge storage section provided between the light receiving section and the transfer path at a desired timing. Therefore, the charge accumulation period can be adjusted. Then, the timing of transferring the signal charges stored in the charge storage unit to the transfer path by sequentially turning on the second transfer gate unit can be made different from each other, so that the number of potential wells formed in the transfer path is reduced. As a result, the number of electrodes to be arranged for one light receiving unit is set to one, and the width of the light receiving unit can be reduced to about the width of one electrode. As a result, the number of light receiving sections that can be arranged per unit length can be increased, and high resolution can be achieved by increasing the density of the light receiving sections. Further, the size of the photoelectric conversion device can be reduced.

In particular, according to the sixteenth aspect of the present invention, a clear image can be obtained by keeping the charge accumulation period in each light receiving section constant.

[Brief description of the drawings]

FIG. 1 is a plan view showing a layout of a line sensor 30. FIG.

FIG. 2 is a sectional view taken along the line II-II of FIG.

FIG. 3 is a sectional view taken along the line III-III in FIG. 1;

FIG. 4 is a sectional view showing an output unit 30D of the line sensor 30.

FIG. 5 is a block diagram illustrating an overall configuration of a solid-state imaging device 50 using a line sensor 30.

FIG. 6 shows CCD transfer electrodes 39-1 to 3-3 of the line sensor 30.
9 is a timing chart showing waveforms of drive pulse signals φ1 to φ4 supplied to 9-4.

7 is an explanatory diagram showing potential wells W, W... Which move within the transfer path 33 when the drive pulse signals φ1 to φ4 shown in FIG. 6 are supplied.

FIG. 8 is a plan view showing a layout of the line sensor 60.

FIG. 9 is a sectional view taken along line IX-IX in FIG. 8;

FIG. 10 shows CCD transfer electrodes 69-1 to 69-2 of the line sensor 60;
6 is a timing chart showing waveforms of drive pulse signals φ1 to φ4 and a drive pulse signal TG supplied to 69-4.

FIG. 11 shows a sensor unit 80 which is a main part of the line sensor 80.
FIG. 9 is a plan view showing a layout of S light receiving units 81,.

FIG. 12 is a block diagram showing an overall configuration of a line sensor 80.

FIG. 13 is a circuit diagram showing an output unit 80D of the line sensor 80.

FIG. 14 is a circuit diagram showing a pulse generation circuit 88 of the line sensor 80.

FIG. 15 is a circuit diagram showing a configuration of a circuit block N and a circuit block D of the pulse generation circuit 88.

FIG. 16 is a timing chart showing waveforms of various pulses input to the pulse generation circuit 88.

FIG. 17 shows the electrodes 84-1, 84-2,
84-3,... 84-12 supplied to the drive pulse signals φ1 to
6 is a timing chart showing a waveform of φ12.

18 shows a potential well W, which moves within the transfer path 83 when the driving pulse signals φ1 to φ12 shown in FIG. 17 are supplied.
It is explanatory drawing which shows W ....

FIG. 19 is a plan view showing a layout of the line sensor 90.

FIG. 20 shows a first transistor gate section 97, an electrode 94, and a second transfer gate section 9 of the line sensor 90.
5, the driving pulse signal TG and the driving pulse signal φ
6 is a timing chart showing waveforms 1 to 12;

FIG. 21 is a diagram showing a layout of a conventional four-phase drive line sensor.

FIG. 22 is a diagram showing a layout of a conventional line sensor provided with two charge transfer units on both sides of a light receiving unit.

[Explanation of symbols]

 30, 60, 80, 90 Line sensor 31, 61, 81, 91 Light receiving section 32, 62, 82, 92 Charge transfer section 33, 63, 83, 93 Transfer path 34, 64, 84, 94 Electrode 35, 85 Transistor gate Part 51 pulse generating circuit (driving means) 65, 95 second transistor gate part 66, 96 charge storage part 67, 97 first transistor gate part 88 pulse generating circuit (driving means)

Claims (18)

[Claims] 1. A plurality of light receiving units arranged at a predetermined pitch, a plurality of transfer gate units individually adjacent to the plurality of light receiving units and arranged at a pitch equal to the predetermined pitch, and the plurality of transfer gates A transfer path provided along the arrangement direction of the sections, and a charge transfer section including a plurality of electrodes arranged on the transfer path at a pitch equal to the predetermined pitch, the plurality of transfer gate sections and the plurality of A driving means for selectively supplying drive pulses to the plurality of transfer gate portions and the plurality of electrodes at desired timings, is connected to the electrodes. 2. The transfer gate portion and the electrode corresponding to the transfer gate portion are integrally formed, and the transfer gate portion and the electrode formed integrally with the transfer gate portion are provided with the electrode from the driving unit. Ternary drive pulses of a first potential for forming a potential well below the gate electrode, a second potential for turning on the transfer gate portion, and a third potential for forming no potential well below the electrode are selectively applied. To
The photoelectric conversion device according to claim 1, wherein the photoelectric conversion device is supplied at a desired timing. 3. The plurality of light receiving units are divided into three or more stages in the order of arrangement and alternately, and the transfer gate unit adjacent to each of the light receiving units in each stage and the electrode corresponding thereto are: A drive pulse which is connected to an individual signal line for each stage and which has a different phase for each stage from the drive means via the signal line is supplied to the transfer gate section and the electrode. The photoelectric conversion device according to claim 1. 4. The plurality of light receiving units are divided into four stages, and the plurality of transfer gate units and the plurality of electrodes are supplied with four-phase driving pulses having different phases for each stage from the driving unit. The photoelectric conversion device according to claim 3, wherein: 5. A solid-state imaging device using the photoelectric conversion device according to claim 1, wherein the solid-state imaging device includes a plurality of transfer gate units and a plurality of electrodes. The driving unit that supplies a driving pulse; a storage unit that stores the optical signals sequentially output from the photoelectric conversion device from each of the light receiving units; and the optical signals stored in the storage unit are rearranged to obtain image information. A solid-state imaging device, comprising: an image generation unit configured to generate an image. 6. A plurality of light receiving sections arranged at a predetermined pitch, a plurality of first transfer gate sections respectively adjacent to the plurality of light receiving sections and arranged at a pitch equal to the predetermined pitch, and A plurality of charge storage portions respectively adjacent to the first transfer gate portion, and a plurality of second transfer gate portions individually adjacent to the plurality of charge storage portions and arranged at a pitch equal to the predetermined pitch. A transfer path provided along the direction of arrangement of the plurality of second transfer gate sections, and a charge transfer section including a plurality of electrodes arranged on the transfer path at a pitch equal to the predetermined pitch, The plurality of first transfer gate units, the plurality of second transfer gate units, and the plurality of electrodes are provided with the plurality of first transfer gate units, the plurality of second transfer gate units, respectively. Over the isolation portions and selectively a driving pulse to the plurality of electrodes, and a photoelectric conversion device characterized by being connected to driving means for supplying at a desired timing. 7. The second transfer gate portion and the electrode corresponding to the second transfer gate portion are integrally formed, and the second transfer gate portion and the electrode are formed integrally with each other. A first potential for forming a potential well below the electrode, a second potential for turning on the second transfer gate portion, and a second potential for forming no potential well below the electrode. 7. The photoelectric conversion device according to claim 6, wherein three drive pulses of three potentials are supplied selectively and at a desired timing. 8. The plurality of first transfer gate units are provided with the first transfer gate unit at the same timing from the driving unit.
8. The photoelectric conversion device according to claim 6, wherein a drive pulse having a fourth potential for turning on the transfer gate section is supplied. 9. The plurality of light receiving units are divided into three or more stages in the order of arrangement and alternately, and the second transfer gate unit and the electrode corresponding to each of the light receiving units in each stage are each Each stage is connected to an individual signal line, and a driving pulse having a different phase for each stage is supplied to the second transfer gate unit and the electrode from the driving unit via the signal line. Claim 7
Or the photoelectric conversion device according to claim 8. 10. The plurality of light receiving units are divided into four stages, and the plurality of second transfer gate units and the plurality of electrodes are provided with four-phase driving pulses having different phases for each stage from the driving unit. 10. The photoelectric conversion device according to claim 9, wherein is supplied. 11. A solid-state imaging device using the photoelectric conversion device according to claim 6, wherein the solid-state imaging device includes: the plurality of first transfer gate units; A second transfer gate unit, the driving unit that supplies the driving pulse to the plurality of electrodes, and a storage unit that stores optical signals from the respective light receiving units sequentially output from the photoelectric conversion device, A solid-state imaging device comprising: an image generation unit that rearranges optical signals stored in the storage unit to generate image information. 12. A plurality of light receiving portions arranged at a predetermined pitch, a plurality of transfer gate portions individually adjacent to the plurality of light receiving portions and arranged at a pitch equal to the predetermined pitch, and the plurality of transfer gates A charge transfer section including a transfer path provided along the arrangement direction of the sections, and a plurality of electrodes arranged at a pitch equal to the predetermined pitch on the transfer path; and at least a plurality of transfer gate sections and individual signals. Connected by a line, and selectively apply a drive pulse to the plurality of transfer gate units and the plurality of electrodes, and
Driving means for supplying at a desired timing, the driving means distributes two or more kinds of second driving pulses having a first potential to the plurality of electrodes at different timings from each other, and A plurality of independent potential wells are formed, and a timing at which the distributed second drive pulse becomes the first potential is adjusted to sequentially move the plurality of independent potential wells in the transfer path. In addition, a first drive pulse having a second potential at a timing when the transfer gate portion and the sequentially moving empty potential well are adjacent to each other in the arrangement order of the plurality of transfer gate portions is transmitted to the individual signal line. A signal charge stored in the light receiving unit and sequentially transferred to the empty potential well by turning on the transfer gate unit. 13. The plurality of light receiving units are divided into three or more stages alternately in the order of arrangement, and the driving unit is configured to apply at least one of the electrodes to each of the electrodes corresponding to each of the light receiving units in each of the stages. The photoelectric conversion device according to claim 12, wherein the second drive pulse that becomes the first potential is supplied at a different timing every time. 14. The transfer gate portion, which is adjacent to each of the plurality of light receiving portions, and the electrode corresponding to the transfer gate portion are integrally formed, and the driving means includes: 14. The photoelectric conversion device according to claim 13, wherein a third drive pulse in which the first drive pulse and the second drive pulse are superimposed is supplied to a gate unit and the electrode. 15. A plurality of light receiving units arranged at a predetermined pitch, a plurality of first transfer gate units respectively adjacent to the plurality of light receiving units and arranged at a pitch equal to the predetermined pitch, and A plurality of charge storage units individually adjacent to the first transfer gate unit, and a plurality of second transfer gate units individually adjacent to the plurality of charge storage units and arranged at a pitch equal to the predetermined pitch. A charge transfer unit including a transfer path provided along an arrangement direction of the plurality of second transfer gate units, and a plurality of electrodes arranged on the transfer path at a pitch equal to the predetermined pitch; The plurality of second transfer gates are connected to the plurality of second transfer gates by individual signal lines, and drive pulses are selectively and selectively applied to the plurality of second transfer gates and the plurality of electrodes. Driving means for supplying at least two kinds of second driving pulses having a first potential to the plurality of electrodes at different timings from each other, and mutually driving the plurality of electrodes under the electrodes. Forming a plurality of independent potential wells, adjusting the timing at which the distributed second drive pulse becomes the first potential, sequentially moving the independent potential wells in the transfer path, and In the order of arrangement of the plurality of second transfer gate units, the first drive pulse which becomes the second potential at a timing when the second transfer gate unit and the sequentially moving empty potential well are adjacent to each other is transmitted to the individual drive gates. The signal charges are supplied via a signal line, the second transfer gate is turned on, and the signal charges respectively stored in the charge storage unit from the light receiving unit via the first transfer gate unit Are sequentially transferred to the empty potential well. 16. The driving unit supplies a driving pulse having a fourth potential to turn on the first transfer gate unit to the plurality of first transfer gate units at the same timing. The photoelectric conversion device according to claim 15, wherein: 17. The method according to claim 17, wherein the plurality of light receiving units are divided into at least three or more stages in accordance with an arrangement order, and the driving unit applies at least the electrodes respectively corresponding to the light receiving units of each stage to each of the plurality of stages. 17. The photoelectric conversion device according to claim 15, wherein the second drive pulse that becomes the first potential is supplied at different timings. 18. The transfer gate unit and the electrode, wherein the second transfer gate unit and the electrode respectively corresponding to each of the plurality of light receiving units are integrally formed, and the driving unit is configured such that the transfer gate unit and the electrode are integrally formed. 18. The photoelectric conversion device according to claim 17, wherein a third drive pulse in which the first drive pulse and the second drive pulse are superimposed is supplied.