JPH10335491A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To accurately obtain a desired resistance after completion for such resistance element as an SRAM device. SOLUTION: A semiconductor device is laminated on a semiconductor substrate 1 at least via an insulation film and has a resistance layer 10 consisting of a semiconductor material where resistance is set according to the amount of introduced impurity and a flattening film (for example, O3 -TEOS film 17) including water being laminated at the upper-layer side of the resistance layer 10. A desired impurity is introduced to the resistance layer 10 so that resistance becomes a desired value after fluctuation by laminating the flattening film 17 at the upper-layer side. In an actual manufacturing process, the amount of fluctuation in resistance of the resistance layer 10 being generated due to the presence or absence of the flattening film 17 is preestimated and the impurity is introduced based on it. The resistance can be adjusted by changing at least either the pattern shape of the resistance layer 10 or thickness.

Description

DETAILED DESCRIPTION OF THE INVENTION TECHNICAL FIELD OF THE INVENTION

The present invention relates to an SRA having a high resistance load element made of, for example, conductive polysilicon in a memory cell.
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a resistance layer such as an M device and a method of manufacturing the same, and more particularly, to setting a resistance value of the resistance layer to ensure stable operation.

[0002]

2. Description of the Related Art As a resistance element of a semiconductor memory device, in addition to an impurity diffusion layer in a semiconductor substrate, a resistance layer obtained by patterning polycrystalline polysilicon or the like after making it conductive may be used. For example, in an SRAM device, a resistive load type cell using conductive polysilicon as a load element in a memory cell is currently the mainstream, whereby an extremely high (〜TeraΩ) load resistance can be realized in a relatively small area. Also, by adopting a multi-layer polysilicon structure in which this high resistance load element is arranged above the driver transistor of the cell, a memory cell with high integration and a small data holding current has been achieved.

In this SRAM device of a resistive load type cell,
In order to quickly stabilize the potential of the storage node of a memory cell within a limited operation time and to reliably write or read stored data, the resistance of a high-resistance load element is very important. In order to ensure the performance, it is necessary to accurately set the load resistance value to a target value.

[0004]

The resistance value of the high resistance load element is determined by precisely removing impurities such as phosphorus (P) during or after the formation of the polysilicon film in the manufacturing process of the SRAM device. Achieved by introduction into a membrane.

However, despite the fact that a desired resistance value (design value) has been obtained immediately after the polysilicon film is made conductive, the resistance value fluctuates in the subsequent manufacturing process, so that the completed high resistance The resistance value of the load element may deviate from an intended design value. When the load resistance value fluctuates, a cell operation margin is narrowed, and therefore, a high-speed and stable cell operation cannot be guaranteed and a malfunction is caused.

An object of the present invention is to provide a semiconductor device capable of accurately obtaining a desired load resistance after completion, and a method of manufacturing the same.

[0007]

SUMMARY OF THE INVENTION In view of the above problems,
The present inventor has conducted various studies to find the cause of the variation in the load resistance value. As a result, as a flattening film on the interlayer insulating layer of the metal wiring, for example, C
When depositing a VD silicon oxide film (hereinafter referred to as an O ₃ -TEOS film), it was found that the load resistance value fluctuated thereafter. And this phenomenon is caused by O ₃ -TEO
It has been found that hydrogen from the flattened film containing moisture such as the S film has some effect on the high resistance load element.

The present invention has been devised in view of such circumstances, and sets the impurity concentration in the resistance layer in advance in consideration of the fluctuation range of the load resistance value. That is, the semiconductor device according to the present invention, a resistance layer formed of a semiconductor material having a resistance value that is stacked on a semiconductor substrate via at least an insulating film and whose resistance value is set according to the amount of introduced impurities,
A planarization film containing moisture laminated on an upper layer side of the resistance layer, wherein the resistance layer has a resistance after changing by laminating the planarization film on the upper layer side. A predetermined amount of impurity is introduced so that the value becomes a desired value.

Specifically, when the conductivity type is n-type, the amount of impurities introduced into the resistance layer is smaller than the amount of impurities having the desired resistance value in the absence of the flattening film. It is common when the conductivity type is p-type.

On the other hand, the adjustment of the resistance value can be achieved by changing the shape or thickness of the resistance layer, in addition to the case of adjusting the impurity concentration. In this case, the resistive layer has at least one of a pattern shape and a thickness determined so that a resistance value after changing by laminating the planarizing film on the upper layer side becomes a desired value. I have.

In the method of manufacturing a semiconductor device according to the present invention, a semiconductor film is formed on a semiconductor substrate via at least an insulating film, and a predetermined amount of impurities is added to the semiconductor film during or after the formation of the semiconductor film. After resistance by introducing,
A method for manufacturing a semiconductor device, comprising: forming a resistance layer by patterning a semiconductor film after resistance formation into a predetermined shape; and thereafter, laminating a planarization film containing moisture on an upper layer side of the resistance layer, By estimating in advance the amount of change in the resistance of the resistive layer caused by the presence or absence of the planarization film, and introducing the impurity into the semiconductor film in an amount that offsets the estimated amount of change in the resistance during the impurity introduction. A desired resistance value is obtained after laminating the planarization film on the resistance layer.

In such a semiconductor device and a method of manufacturing the same according to the present invention, the resistance of the resistance layer is determined in advance by taking into account the fluctuation of the resistance value of the resistance layer due to the lamination of the planarization film. In the semiconductor device described above, the resistance value of the resistance layer is a desired value or extremely close to the desired value.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a semiconductor device according to the present invention and a method for manufacturing the same will be described in detail with reference to the drawings. As described above, the present invention can be applied to various semiconductor devices having a resistive layer formed by introducing impurities and a planarizing film containing moisture in a stacked structure on a semiconductor substrate.
Here, an embodiment of the present invention will be described by taking an SRAM device in which the influence of a resistance value variation is considered to be one of the largest in circuit operation as an example.

FIG. 1 is a sectional view showing a schematic configuration of a memory cell of an SRAM device. In FIG. 1, reference numeral 1 denotes a semiconductor substrate such as a silicon wafer, and reference numeral 2 denotes a P-type well (p-well) formed on a front surface side in the semiconductor substrate.

The surface of the p well 2 has a field insulating film 3
Is appropriately separated by insulation. Field insulating film 3
, The drive transistor 4a of the SRAM cell and the select transistor 4b for selectively connecting the drain of the drive transistor 4a to the bit line selected according to the voltage applied to the gate electrode (word line). Is formed. These MOS transistors 4a, 4b
Have the same conductive layer laminated via a gate oxide film (not shown), for example, a laminated structure of a polysilicon layer and a WSi layer. In this polycide structure, for example, both the polysilicon layer and the WSi layer have a thickness of 70 nm to 150 nm.
It is made of a film of about nm.

A first interlayer insulating layer 5 and an etching stop film 6 are formed on the entire surface of these MOS transistors 4a and 4b.
Are formed. The first interlayer insulating layer 5 is made of, for example, silicon oxide (SiO ₂ ) by a normal pressure CVD method,
The etching stopper film 6 is made of, for example, silicon nitride (SiN).
Consists of These film thicknesses are, for example, the first interlayer insulating film 5.
Is about 100 nm, and the etching stopper film 6 is
It is about 00 nm. A bit contact hole 5a and a contact hole 5b for a high resistance load element are formed in the first interlayer insulating film 5 and the etching stopper film 6, respectively.

A bit line extraction electrode layer 7 is formed from inside the bit contact hole 5a to above the select transistors 4b, 4b on both sides. Bit line extraction electrode layer 7
Has a polycide structure and comprises, for example, a polysilicon film made conductive by arsenic (As) introduction and a WSi layer, and both have a film thickness of about 50 nm to 100 nm. The bit line extraction electrode layer 7 is connected to one of the source / drain regions shared by the select transistors 4b, 4b via the bit contact hole 5a.
Above the driving transistor 4a of the SRAM cell, a G made of the same conductive layer as the bit line extraction electrode layer 7 is formed.
The ND wiring layer 8 is wired.

A high resistance load element 11 of a polysilicon layer 10 is arranged on the GND wiring layer 8 with a second interlayer insulation layer 9 interposed therebetween. High resistance load element contact hole 5b of layer 5
Through the contact of the second interlayer insulating layer 9 communicating with
The other source / drain region of the selection transistor 4b is connected to the gate electrode of the driving transistor 4a of the SRAM cell. The second interlayer insulating layer 9 is made of, for example, SiO ₂ and has a thickness of 100 nm to 200 n.
m.

In the polysilicon layer 10, a portion above the GND wiring layer 8 is increased in resistance (low-concentration ion implantation) from there except for the connection portion to the MOS transistors 4 a and 4 b, forming the high resistance load element 11. The region connecting the cells outside of this region is reduced in resistance (high-concentration ion implantation) to form the supply line 12 for the power supply voltage V _DD . Also, the connection points with the MOS transistors 4a and 4b are similarly reduced in resistance. It is necessary to prevent the resistance change of the high resistance load element 11 in the SRAM device. For example, the SiN film 10a on the upper surface of the second interlayer insulating layer 9 and the SiN film on the polysilicon layer 10 are used as a film for preventing the intrusion of moisture, particularly hydrogen. A laminated structure sandwiching the upper and lower portions of the polysilicon layer 10 with a thin protective film such as 10b is employed. The high resistance load element 1
The introduced impurity concentration of 1 will be described later.

On the high resistance load element 11, a third interlayer insulating layer 13 is formed. The third interlayer insulating layer 13, the lower SiN film 10b and the second interlayer insulating layer 9 A metal plug 14 is buried so as to be connected to the upper surface of the bit line extraction electrode layer 7. The third interlayer insulating layer 13 is
For example, the metal plug 14 is made of BPSG (boro-phosphosillcate glass), and is formed of a thin adhesive layer made of TiN / Ti or the like in contact with the inner wall and bottom surface of the contact, and a filled metal material such as tungsten (W). On the third interlayer insulating layer 13, a first metal wiring layer 15 is wired so as to be connected to the metal plug. The first metal wiring layer 15 is provided above and below the main wiring metal (Al) film, respectively.
It has a barrier metal such as iN and forms a three-layer laminated structure. The barrier metal is interposed in order to improve the high-temperature resistance between Al and W.

On the first metal wiring layer 15, an interlayer insulating layer having a multilayer structure is laminated. Specifically, in the SRAM device illustrated in FIG. 1, an interlayer insulating layer having a multilayer structure on the first metal wiring layer 15 is formed by TEOS-O ₂ or TEOS covering the first metal wiring layer 15 by thermal decomposition. Silicon oxide film of plasma CVD (hereinafter, P-TEOS film) 1
6. O ₃ -TEOS film 17 buried in the recess by P-TEOS film 16 to planarize the surface, P-TEOS film 1
8. SOG (Spin on Glass) film 19, P-TEOS film 2
0 are stacked in this order. Where O ₃ -TEOS
The film 17 is made of TEOS (Tetraethyloxysilane or Tetraeth
ylorthosilicate, Si (OC ₂ H ₅ ) ₄ ), and a silicon oxide film deposited by a normal pressure plasma CVD method using O ₃ as a source gas and oxidation of TEOS by O ₃ .

One of the features of the semiconductor device according to the present invention is that
That is, a planarizing film containing water is provided on the upper layer side of the high resistance load element. As the flattening film, any film may be used as long as it is a film having good step coverage containing water, and for example, O ₃ -TE
OS film, SOG (Spin on Glass) film, FOX (Flowable
Oxide) film and the like. In the SRAM device according to the present embodiment, the O ₃ -TEOS film 17 provided in the interlayer insulating layer having a multilayer structure on the first metal wiring layer 15 corresponds to the planarizing film containing water of the present invention. I do. In addition, as the planarizing film containing water of the present invention, for example, the third interlayer insulating layer 13 immediately above the high-resistance load element 11 is formed of O ₃ −.
It may be composed of a film containing moisture such as TEOS.

The surface step caused by the first metal wiring layer 15 is flattened by the interlayer insulating layer having the multilayer structure having the above-described structure, and the uppermost layer (P-TEOS film 20) is
Other metal wiring layers are laminated as necessary. FIG.
Is a case where one more metal wiring layer is provided, in which a second metal wiring layer 21 having the same three-layer structure as the first metal wiring layer 15 is formed. Further, the entire surface is covered with an overcoat 22, and a PIX film 23 is formed only on the memory array to prevent a soft error.

Next, the impurity concentration introduced into the high resistance load element will be described.

FIG. 2 shows the resistance value of the high resistance load element (hereinafter referred to as the resistance value).
The HR resistance is adjusted to a leveling film containing water (O ₃ -T) in a wide range of impurity concentration of N-type and P-type impurities.
It is a graph which shows the result of having investigated before and after formation of the EOS film 17). FIG. 2 shows the doses of the N-type impurity ions (P ⁺ ) and the P-type impurity ions (B ⁺ ) on the horizontal axis, and shows the H amount on the vertical axis.
The R resistance value is shown. In addition, the measurement of the HR resistance value
During the wafer manufacturing process of the AM device, the measurement was performed using a measurement pattern in a TEG (Test Elements Group) provided in the same wafer.

As shown in FIG. 2, O ₃ −
By forming the TEOS film 17, the curve indicating the HR resistance value is shifted in the direction in which the dose of the P-type impurity is increased as a whole (to the left in FIG. 2). Regarding this resistance value shift, the flattening film is made of another material (SOG, FOX).
, Etc.), it has been confirmed that the same behavior is exhibited as long as the material contains a large amount of moisture. Although the details of the cause of the resistance value shift are not completely clear, it is considered that the moisture from the flattening film has some influence. For example, Si
Passivation in which impurities do not function as donors or acceptors due to the incorporation of hydrogen from the flattening film into dangling bonds on the surface or point defects (vacancies and interruptions) in Si causes incorporation. It is considered that this passivation causes the resistance value of the high resistance load element to fluctuate.

For this reason, in a process in which a flattening film containing a large amount of water needs to be formed on the upper layer side, if the impurity dose of the resistance layer is set in the same manner as in a normal case where the flattening film is not formed, In the case of an N-type impurity, the HR resistance value becomes smaller than a desired value. Therefore, in order to obtain a desired HR resistance value, the dose at the time of ion implantation must be smaller than usual. Conversely, in the case of a P-type impurity, the HR resistance value becomes larger than a desired value unless the dose at the time of ion implantation is made larger than usual.

In the semiconductor device of the present invention, as one method of canceling the resistance value fluctuation of the high resistance load element, when introducing the impurity, the amount of the resistance value fluctuation is preliminarily recorded (that is, obtained at the time of setting the process conditions). It is decided to adjust the introduction amount. For example, in the SRAM device of this example shown in FIG. 1, if the impurity introduced into the high resistance load element 11 is N-type and its target HR resistance is 1 TΩ, the conventional 1.2 × 10 ¹⁴ atoms / 0.8 × 10 ¹⁴ at cm ²
By pre-reducing the dose to oms / cm ²
The HR resistance value after completion is close to the target value.

On the other hand, as another method for canceling the resistance value fluctuation in the present invention, there is a method of changing the pattern shape or the thickness of the high resistance load element. For example, if the HR resistance value is reduced by one digit by forming the flattening film, the thickness of the polysilicon forming the high resistance load element is reduced to about 1/10 in advance. If the HR resistance value is increased to about 10 times by changing the pattern of the above to be elongated or changing both the pattern shape and the thickness, the HR resistance value after completion can be made closer to the target value.

In the SRAM device having such a configuration, the amount of impurities introduced into the high resistance load element 11 (or at least one of the pattern shape and the thickness) is adjusted in advance.
Since the resistance value variation due to the presence or absence of the flattening film 17 is canceled, a target value or a value very close to the target value is obtained as the resistance value of the completed high-resistance load element 11 after completion. For this reason, the potential of the storage node of the memory cell is stabilized, and the cell operation margin is not narrowed unlike the related art, so that high-speed and stable cell operation is guaranteed.

Next, a method for manufacturing a semiconductor device according to the present invention will be described with reference to FIGS.
This will be described with reference to FIG.

First, as shown in FIG. 3, a semiconductor substrate 1 such as a silicon wafer is prepared.
The field insulating film 3 having a thickness of about 400 nm is selectively formed by using the COS method. In order to form the field insulating film 3, although not particularly shown, first, an oxide film for a pad and an oxidation prevention film such as a silicon nitride film are laminated in this order, these are processed into a predetermined pattern by dry etching, and then LOCOS oxidation is performed. Do. A predetermined resist pattern is formed in a state where the oxidation preventing film is removed and the thin pad oxide film remains, and a P-type impurity such as boron (B) is selectively ion-implanted into the semiconductor substrate 1 using the resist pattern as a mask. . As a result, the p-well 2 is formed at least on the surface of the substrate including the memory array.

Subsequently, a MOS transistor having an LDD structure is formed. First, the formation of this MOS transistor
After forming a gate oxide film (not shown), the polysilicon layer is
After the introduction of impurities, a silicide layer of WSi or the like is formed to a thickness of 70 nm to 150 nm.
A film is formed by sputtering method or the like, and the laminated film is patterned into a predetermined shape by using a photolithography processing technique. Using these gate electrode and field insulating film 3 as a mask, arsenic (As) is ion-implanted into N
A low-concentration impurity region (LDD region) of a type is selectively formed on the surface of p well 2. Further, a sidewall film material made of SiO ₂ or the like is formed on the entire surface, a sidewall is formed on the side wall of the gate electrode by anisotropic etching such as RIE, and then the sidewall, the gate electrode and the field insulating film 3 are masked. Then, high-concentration As is ion-implanted to form N-type source / drain regions. Thus, the driving transistor 4a and the selection transistor 4b of the SRAM cell are obtained.

In the step shown in FIG. 4, over the formed MOS transistors 4a and 4b, a SiO ₂ film, for example, of about 100 nm as a first interlayer insulating layer 5, and a SiN film, for example, as an etching stopper film 6, are formed. 20nm
It is deposited by a CVD method in order of about 100 nm. For the deposited first interlayer insulating layer 5 and the etching stopper film 6, a bit contact hole 5a opening at a predetermined position (above one source / drain region common to the select transistors 4b, 4b) is formed by photolithography. It is formed by using.

Subsequently, the bit line extraction electrode layer 7 and the GND wiring layer 8 are formed simultaneously. Specifically, first, the polysilicon layer is formed to a thickness of, for example, 50 nm to 100 nm so as to block the exposed surface of the source / drain region by the bit contact hole 5a.
It is deposited by a CVD method to a thickness of about nm. After arsenic (As) is ion-implanted into the entire surface of the deposited film to make it conductive, light etching with dilute hydrofluoric acid is performed, and a silicide layer of WSi or the like is immediately formed by, for example, a CVD method of about 50 nm to 100 nm. The light etching using the diluted hydrofluoric acid is performed to remove a natural oxide film on the surface of the polysilicon layer. However, since the etching stopper film 6 is interposed under the polysilicon layer, the light etching is sufficiently performed. Does not cause a hole in the first interlayer insulating layer 5 on the lower layer side to cause insulation failure with respect to the gate electrode of the MOS transistor.

Thereafter, the laminated film having the polycide structure is
When patterning into a predetermined shape using photolithography processing technology with the underlying etching stopper film 6 as a stopper, the bit line extraction electrode layer 7 becomes a bit contact hole 5a.
Is formed over the select transistors 4b, 4b, and the GND wiring layer 8 is formed above the drive transistor 4a of the SRAM cell.

In the step shown in FIG. 5, the second interlayer insulating layer 9 is formed.
For example, about 100 nm to 200 nm, and the SiN film 1
Oa is deposited by, for example, about 5 nm to 30 nm by a CVD method. Then, the SiN film 10a, the second interlayer insulating film 9, the etching stopper film 6, and the first interlayer insulating layer 5 are sequentially etched by using a photolithography technique, and the other source / source of the select transistor 4b of the memory cell is etched. A high resistance load element contact hole 5b opening on the drain region is formed.

Subsequently, as shown in FIG. 6, a high resistance load element 11 is formed by a polysilicon layer. Specifically, first, for example, a polysilicon film 10 of about 100 nm is formed.
Is formed by a CVD method, and the polysilicon film 10 is made conductive by mixing an impurity introduction gas during the film formation or by ion implantation after the film formation. At this time, the amount of the introduced impurities is determined by a calibration curve previously checked (for example, see FIG. 2).
Determined based on the The determined amount of introduced impurities is
In the case of the N-type impurity, the amount is smaller than usual in consideration of the decrease in the resistance value due to the presence or absence of the flattening film on the upper layer described above. In FIG. 2, if a specific numerical value is shown as an example, the target HR resistance value is 1 TΩ.
Then, while the P ⁺ dose amount in a normal case without considering the variation in resistance value is 1.2 × 10 ¹⁴ atoms / cm ² , the dose amount in this case is 0.8 × 10 ¹⁴ atoms / cm ^2. Smaller. Similarly, the target HR resistance value is set to 5
Assuming 00 GΩ, the normal 1.4 × 10 ¹⁴ atoms / cm
^The dose is reduced from ² to 1.0 × 10 ¹⁴ atoms / cm ² .

Next, an impurity is additionally introduced into a region connecting the cells other than the high resistance load element 11 by, for example, a selective ion implantation method using a resist pattern as a mask. The supply wiring 12 for the power supply voltage V _DD is formed. At this time, impurities are additionally introduced into the connection region around the high resistance load element contact hole 5b at the same time to lower the resistance. Subsequently, the polysilicon film 1
0 is patterned using the photolithography processing technique together with the underlying SiN film 10a. Thereby, the high-resistance load element 11 is placed on the second interlayer insulating layer 20 through the high-resistance element contact hole 5b.
b and the drive transistor 4a. The patterning of the polysilicon film 10 is performed by introducing impurities (ion implantation) based on a calibration curve.
May be performed prior to

In the step shown in FIG. 7, first, SiN
The film 10b is formed by the CVD method, and the high resistance load element 11 is formed.
And the supply wiring 12 for the power supply voltage V _DD is coated. This S
The iN film 10b is a film for protecting the polysilicon film 10 together with the underlying SiN film 10a. Also, CVD
A third interlayer insulating layer 13 is formed on the entire surface by, for example, B
A PSG film is deposited thick and reflowed to flatten the surface.

Next, a contact hole reaching the bit line extraction electrode layer 7 from the surface of the formed third interlayer insulating layer 13 is formed by using a usual photolithography processing technique.
A metal plug 14 made of tungsten (W) or the like is formed by filling the contact hole. Specifically, a W film is formed thicker by the CVD method following the adhesion layer of TiN / Ti or the like, and when these films are etched back, a metal plug 14 connected to the bit line extraction electrode layer 7 is formed. You. Then, an Al wiring layer having a three-layer structure including a barrier metal on the upper and lower sides and containing Cu or the like on an intermediate Al layer is formed, and the Al wiring layer is patterned by using a photolithography processing technique. Thus, the first metal wiring layer 15 is formed.

In the step shown in FIG. 8, first, P-TEOS
After covering the first metal wiring layer 15 with the film 16, the O ₃ -TEOS film 17 corresponding to the flattening film of the present invention is changed to a P-TEO film.
It is formed in such a manner as to be buried in a concave portion on the surface of the S film 16. This flattening method may be another method such as a chemical mechanical polishing method, but here, a so-called dummy pattern process is used. In the dummy pattern process, although not particularly shown, a resist dummy pattern is formed at a place where the space width of the Al wiring layer is equal to or more than a certain value, UV curing is performed, a second resist is applied, and etching of the two-layer resist is performed. TEO of the base by etch back using the difference in speed
This is a method of flattening the S film.

Thereafter, as shown in FIG.
After the S film 18 is formed, the SOG film 19 is spin-coated and etched back, and another P-TEOS film 20 is deposited, so that the interlayer insulating layer is added while flattening during the formation. Then, a contact hole (not shown) is appropriately formed in each of the films 16 to 20 constituting the interlayer insulating layer, and connected to the lower first metal wiring layer 15 through the contact hole. To form a second metal wiring layer 21 composed of a second Al wiring layer. Further, a SiN film, for example, is coated as the overcoat film 22 over the entire surface by plasma CVD. Thereafter, although not particularly shown, the SRAM device is completed through a pad windowing step for the overcoat film 22 and a step of forming a PIX film 23 for preventing soft errors only in the memory array.

In this method of manufacturing the SRAM device, the O ₃ − − containing high moisture in the upper layer side of the high load resistance element 11.
The resistance variation caused by the presence or absence of the TEOS film 17 is estimated in advance in a predetermined impurity concentration range as two different calibration curves (HR resistance curves in FIG. 2), and the polysilicon film 10 constituting the high load resistance element is estimated. (Resistance layer)
When the impurities are introduced into the semiconductor device, the amount thereof is adjusted to offset the accumulated amount of change in the resistance value, so that the completed resistance value can be made a desired value or extremely close to the desired value. The resistance value can be adjusted by changing at least one of the pattern shape and the thickness of the resistance layer. Either of these methods has the advantage that the present invention does not require any additional steps, so that the operation of the memory cell can be easily stabilized, and a high-speed and highly reliable SRAM device can be realized.

[0045]

According to the semiconductor device of the present invention, the amount of impurities (or at least one of the pattern shape and the thickness) introduced into the resistive layer detects a change in resistance in a subsequent step such as formation of a flattening film. Since the resistance value after completion is adjusted to a desired value or very close to the desired value, the characteristics and operation performance involving the resistance of the resistive layer are good. For example, in the case of an SRAM device, since the potential of the storage node of the memory cell is stabilized and the cell operation margin is not narrowed unlike the related art, high-speed and stable cell operation is guaranteed.

In the method of manufacturing a semiconductor device according to the present invention, the above-mentioned good characteristics and operational performance can be obtained without estimating the amount of resistance variation in advance and without any additional steps during the normal manufacturing steps to be repeated. Can be easily obtained.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a schematic configuration of a memory array of an SRAM device according to an embodiment of the present invention.

FIG. 2 shows the resistance of the high-resistance load element of FIG. 1 before and after the formation of a planarizing film containing water (O ₃ -TEOS film) in a wide range of impurity concentrations of N-type and P-type impurities. It is a graph which shows a result.

FIG. 3 shows an embodiment of the present invention (a manufacturing method);
FIG. 4 is a cross-sectional view showing a process of manufacturing the RAM device, which shows steps up to the formation of a MOS transistor.

FIG. 4 is a cross-sectional view showing up to formation of a bit line extraction electrode layer and a GND wiring layer in a manufacturing process following FIG. 3;

FIG. 5 is a cross-sectional view showing up to the formation of a contact hole for a high-resistance load element in a manufacturing process following FIG. 4;

FIG. 6 is a cross-sectional view showing up to the formation of a high-resistance load element in a manufacturing process following FIG. 5;

FIG. 7 is a cross sectional view showing the process of forming the first metal wiring layer in the manufacturing process following FIG. 6;

FIG. 8 is a cross-sectional view showing a process of flattening a step above a first metal wiring layer by an O ₃ -TEOS film in a manufacturing process following FIG. 7;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... p well, 3 ... field insulating film, 4a ... SRAM cell drive transistor, 4
b ... Selection transistor of SRAM cell, 5 ... First interlayer insulating layer, 5a ... Bit contact hole, 5b ... Contact hole for high resistance load element, 6 ... Etching stop film, 7 ... Bit line extraction electrode layer, 8 ... GND Wiring layer, 9: second interlayer insulating layer, 10: conductive polysilicon film (resistance layer), 10
a, 10a: SiN film, 11: high resistance load element, 12:
Supply wiring for power supply voltage V _DD , 13... Third interlayer insulating layer, 1
4 metal plug, 15 first metal wiring layer, 16, 1
8, 20 ... P-TEOS film, 17 ... O ₃ -TEOS film (planarizing film), 19 ... SOG film, 21 ... second metal wiring layer, 22 ... overcoat, 23 ... PIX film.

Claims (8)

[Claims] A resistive layer formed of a semiconductor material having a resistance value set according to an amount of introduced impurities, the resistive layer being laminated on a semiconductor substrate at least via an insulating film, and being laminated on an upper layer side of the resistive layer; A planarizing film containing moisture, wherein the resistance layer has a desired value such that a resistance value after changing by laminating the planarizing film on the upper layer side becomes a desired value. A semiconductor device into which a fixed amount of impurities has been introduced. 2. The method according to claim 2, wherein the impurity introduced into the resistance layer is:
The conductivity type is n-type, and the amount of the n-type introduced impurity is smaller than the amount of impurity that has the desired resistance value when the flattening film is not provided.
3. The semiconductor device according to claim 1. 3. The method according to claim 1, wherein the impurity introduced into the resistance layer is:
2. The semiconductor device according to claim 1, wherein the conductivity type is p-type, and the amount of the p-type introduced impurities is larger than the amount of impurities having the desired resistance value when the planarization film is not provided. 4. The semiconductor device according to claim 1, wherein said flattening film comprises a silicon oxide film deposited by a chemical vapor deposition method utilizing oxidation of TEOS by ozone. 5. The semiconductor device according to claim 1, wherein said flattening film comprises a coating film of silicon oxide formed by a spin coating method. 6. The semiconductor device according to claim 1, wherein said semiconductor device is an SRAM device including a high resistance load element made of high resistance polysilicon as said resistance layer in a memory cell. 7. A resistive layer made of a semiconductor material having a resistance value set in accordance with an amount of introduced impurities and laminated on a semiconductor substrate with at least an insulating film interposed therebetween, and a resistive layer laminated on an upper layer side of the resistive layer. A planarization film containing water, wherein the resistance layer is patterned so that the resistance value after changing by laminating the planarization film on the upper layer side becomes a desired value. A semiconductor device in which at least one of a shape and a thickness is determined. 8. After a semiconductor film is formed over a semiconductor substrate with at least an insulating film interposed therebetween, and after a predetermined amount of impurities are introduced into the semiconductor film during or after the formation of the semiconductor film, resistance is changed. A method for manufacturing a semiconductor device, comprising: forming a resistance layer by patterning a semiconductor film after resistance formation into a predetermined shape; and thereafter, laminating a planarization film containing moisture on the upper side of the resistance layer, Estimating in advance the amount of change in the resistance value of the resistive layer caused by the presence or absence of the flattening film, and introducing the impurity into the semiconductor film in an amount that offsets the estimated amount of change in the resistance value during the impurity introduction. A method of manufacturing a semiconductor device that obtains a desired resistance value after laminating the flattening film on the resistance layer.