JPH10333875A - Memory access device and its recording medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it possible to fast display an image in the vertical direction with a simple constitution, by adding an address having no corresponding data to other end of every line. SOLUTION: A 1st address generator 103a generates the address numbers to store only the data corresponding to the odd addresses of a display memory to a 1st DRAM 102a, and a 2nd address generator 103b generates the address numbers to store only the data corresponding to the even addresses of the display memory to a 2nd DRAM 102b respectively. The generator 103a has a 1st dummy area insertion part 104a to add 1 to the number of set pitches, and the generator 103b has a 2nd dummy area insertion part 104b to add 1 to the number of set pitches respectively. In such a constitution, the writing operations can be simultaneously performed to both DRAM 102a and 102b in a vertical access mode.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory access device such as a graphics accelerator for accessing a display memory used for displaying an image.

[0002]

2. Description of the Related Art Image data processed by a graphics accelerator is stored in a display memory. At this time, each pixel of the display device is assigned an address of a display memory as shown in FIG. 4, and the display device displays an image according to data stored at each address of the display memory.

FIG. 4 is a diagram showing a conventional relationship between a display device and an address of a display memory. In FIG. 4, a concept called Pitch is used to display a two-dimensional image in accordance with the contents of a display memory in which data is stored one-dimensionally. Pitch (pitch) indicates the number of data of one line of the display device 206, and the data is 32b.
In the case of it, 640 dots / 32 bits = 20.
That is, one line is composed of 20 data.

Next, taking a graphics accelerator as an example, a conventional memory access device will be described with reference to FIGS.
This will be described with reference to FIG.

FIG. 5 is a block diagram showing a configuration of a graphics accelerator which is an example of a conventional memory access device. FIG. 6 is a diagram showing addresses of data stored in the first DRAM and the second DRAM shown in FIG. In FIG. 5, graphics accelerator 2
Reference numeral 01 includes an address generator 203 for designating an address of a display memory to be accessed, and a data output unit 205 for outputting processed image data. Currently, the display memory has a 4 Mbit (256K × 16 bit) DRA.
M is used as a memory element as standard, and data output from the data output unit 205 is 32 bi as shown in FIG.
In the case of t, the display memory has two DRAMs (the first DR).
An AM 202a and a second DRAM 202b) are used. At this time, the graphics accelerator 201 simultaneously accesses the first DRAM 202a and the second DRAM 202b, writes the upper 16-bit data into the first DRAM 202a,
The lower 16 bits of data are written in 2b.

[0006] In such a configuration, the graphics accelerator 201 outputs the data output from the data output unit 205 to the first D specified by the address generator 203.
The data is written to the addresses of the RAM 202a and the second DRAM 202b, respectively. At this time, as shown in FIG. 6, the addresses of the first DRAM 202a and the second DRAM 202b correspond to the addresses of the display memory 202 assigned to each pixel of the display device 206 shown in FIG. doing.

Therefore, the display device 206 shown in FIG.
When the graphics accelerator 201 displays a straight line in the vertical direction on the first DRAM 202a, for example,
And address 0 → 20 → 40 of the second DRAM 202b
Data was written in order to each address, and a straight line was displayed.

[0008]

However, in the conventional memory access device described above, there is only one address generator, and data is written by accessing the display memory in units of two words (32 bits). However, when an image is displayed on the LCD, the access to the same memory element is repeated, and the access in the vertical direction becomes slow.

[0009] As a method of solving such a problem, a tile mapping method as shown in FIG. 7 has been proposed. FIG. 7 is a diagram showing a relationship between a display device and a display memory for explaining a tile mapping method of the graphics accelerator shown in FIG.

As shown in FIG. 7, the tile mapping method is, for example, 128 dots in the horizontal direction / 32 dots in the vertical direction.
Data for each line (512 bytes) is written as one unit (hereinafter referred to as one tile) for each unit. At this time, since the display memory can be continuously accessed within one tile 301, an oblique straight line or the like can be displayed at high speed.

However, in order to display on the display device, as shown in FIG. 4, scanning is performed continuously from the upper left pixel to the lower right pixel of the display device.
The addresses in the display memory must be consecutive numbers from left to right. Therefore, in the tile mapping method, data reading processing always occurs at a boundary called a tile boundary (see FIG. 7). For example, if the number of dots in the horizontal direction of the display device is 640 dots as shown in FIG. 5, and if the number of bits in the horizontal direction of one tile is 128 bits, five tiles are arranged in the horizontal direction as shown in FIG. In other words, the graphics accelerator has to perform data reading processing at the boundary of four tiles, and thus there is a problem that the total performance is not improved.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art, and has been made in consideration of a memory access such as a graphics accelerator capable of displaying an image in a vertical direction at a high speed with a simple configuration. It is intended to provide a device.

[0013]

In order to achieve the above object, a memory access device according to the present invention is arranged such that an arbitrary continuous address is divided for each predetermined even number, and the predetermined even number of addresses is one end in the horizontal direction. In a two-dimensional address arrangement in which a plurality of lines continuously arranged from the first to the other end are provided in the vertical direction, data corresponding to the address is transferred to the first memory element and the second memory element. A first address generator for generating an address number for writing data corresponding to an odd address among said addresses in said first memory element in a memory access device for writing data to a data storage device comprising a memory element. A second address for generating an address number for writing data corresponding to an even address of the addresses to the second memory element. And less generator, the other end of the line, and a dummy region insertion portion adding one address with no corresponding data respectively, characterized in that it has a to.

Further, in the recording medium of the present invention, an arbitrary continuous address is divided for each predetermined even number, and the predetermined even number addresses are continuously arranged in the horizontal direction from one end to the other end. In a two-dimensional address arrangement in which a plurality of lines are provided in the vertical direction, data corresponding to the addresses is written to a data storage device including a first memory element and a second memory element. A first address generator for generating an address number for writing data corresponding to an odd address among the addresses in the first memory element, the recording medium having a program to be executed by a memory access device recorded thereon. Processing,
A second address generation process for generating an address number for writing data corresponding to an even address among the addresses in the second memory element; And a program for causing the memory access device to execute a dummy area insertion process for adding two addresses.

The memory access device configured as described above writes data corresponding to an odd address into the first memory element and writes data corresponding to the even address into the second memory element. Also, by adding one address having no corresponding data to the other end of the line by the dummy area insertion unit, the number of addresses of each line becomes odd.

Here, when the memory access device accesses an arbitrary one column address in the vertical direction with respect to the two-dimensional address arrangement, the first memory element and the second memory element are alternately accessed. Will have access.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described in detail with reference to the drawings.

In the following, the memory access device of the present invention will be described using a graphics accelerator as an example as in the prior art.

FIG. 1 is a block diagram showing a configuration of a graphics accelerator which is an example of a memory access device according to the present invention. FIG. 2 is a diagram showing addresses of data stored in the first DRAM and the second DRAM shown in FIG.

In FIG. 1, a graphics accelerator 101 according to the present embodiment has a first D serving as a display memory.
A first address generator 103a for generating an address number for accessing the RAM 102a and a second address generator 102 for generating an address number for accessing a second DRAM 102b also serving as a display memory
b and a data output unit 1 for outputting processed image data
05. The first address generator 103a has a first dummy area insertion unit 104a for adding 1 to the set number of Pitches, and the second address generator 104b also has the same number of Pitches as the set Pitch. It has a second dummy area insertion section 104b for adding one.

In such a configuration, as shown in FIG. 2, the first address generator 103a is connected to the first DRAM 1
02a for the odd address of the display memory (address 1, 3
..) Are generated, and the second address generator 103b corresponds to the even addresses (addresses 0, 2,...) Of the display memory for the second DRAM 102b. Generates an address number for storing only data.

The graphics accelerator 101 writes only 16-bit data corresponding to an odd address of the display memory into the first DRAM 102a among the data output from the data output unit 105,
102b corresponds to 16 corresponding to the even address of the display memory.
Write only bit data.

At this time, the first address generator 103a
The second address generator 103b simultaneously performs an address generation operation, and the graphics accelerator 101 simultaneously accesses the first DRAM 102a and the second DRAM 102b (ie, accesses in units of two words).

Each pixel of the display device is assigned an address of the display memory 102 as shown in FIG. Here, at the end of each line, the first dummy region insertion unit 104a and the second dummy region insertion unit 104
A dummy address having no corresponding data is added by b.

FIG. 3 is a diagram showing the relationship between display memory addresses set by the graphics accelerator shown in FIG. 1 with respect to the display device.

The resolution of the display device 106 is 640 dots ×
When the data of each pixel is 16 bits (one word) in 480 lines, Pitch is 640/16 = 40.
Becomes However, as shown in FIG. 3, the first address generator 103a and the second address generator 103b
Is set to a value obtained by adding 1 to the number of Pitches by the respective dummy area insertion units. That is, the graphics accelerator 101 outputs an address with Pitch = 41.

Here, the dummy addresses added by the respective dummy area insertion portions are alternately present in the first DRAM 102a and the second DRAM 102b.

By providing such a dummy memory area,
In order to display a vertical straight line on the display device 106,
For example, address 0 in the display memory → address 41 → address 82 → 1
When accessing addresses 23,..., The data at addresses 0, 82,.
Data at addresses 1, 123,...
a, the graphics accelerator 101 stores addresses 0 and 41 and addresses 82 and 123
Addresses can be accessed simultaneously.

Therefore, by providing a dummy area of one word for each line, it is possible to write data to two DRAMs at a time when accessing in the vertical direction. ), The access in the vertical direction can be performed at twice the speed of the related art. Therefore, it is possible to access the display memory at a higher speed than the conventional memory access device.

The processing executed by the graphics accelerator of the present embodiment may be executed by an arithmetic unit having a CPU. In that case, the arithmetic unit has a recording medium (not shown) in which a program for performing the above-described processing is recorded, and the above-described processing is executed according to a processing program recorded in the recording medium. Here, the recording medium may be a semiconductor memory or another recording medium.

[0031]

Since the present invention is configured as described above, the following effects can be obtained.

A first address generator for generating an address number for writing data corresponding to an odd address to a first memory element, and an address for writing data corresponding to an even address to a second memory element By providing a second address generator for generating a number and a dummy area insertion unit for adding one address having no corresponding data to the other end of the line, a two-dimensional address arrangement is provided in a vertical direction. When each of the addresses in the arbitrary one column is accessed, the first memory element and the second memory element respectively store data in units of one word, and the memory access device stores the data in the first memory element and the second memory unit in units of two words. Assuming that two memory elements are accessed,
Writing can be performed to two memory elements at a time. Therefore, it is possible to access the data storage device at a higher speed than the conventional memory access device.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a graphics accelerator which is an example of a memory access device of the present invention.

FIG. 2 shows a first DRAM and a second DRA shown in FIG. 1;
FIG. 3 is a diagram showing addresses of data stored in M.

FIG. 3 is a diagram illustrating a relationship between addresses of a display memory set by the graphics accelerator illustrated in FIG. 1 with respect to the display device.

FIG. 4 is a diagram showing a conventional relationship between a display device and an address of a display memory.

FIG. 5 is a block diagram showing a configuration of a graphics accelerator as an example of a conventional memory access device.

FIG. 6 shows a first DRAM and a second DRA shown in FIG. 5;
FIG. 3 is a diagram showing addresses of data stored in M.

FIG. 7 is a diagram illustrating a relationship between a display device and a display memory for explaining a tile mapping method of the graphics accelerator illustrated in FIG. 5;

[Explanation of symbols]

 Reference Signs List 101 graphics accelerator 102 display memory 102a first DRAM 102b second DRAM 103a first address generator 103b second address generator 104a first dummy area insertion unit 104b second dummy area insertion unit 105 data output unit 106 display device

Claims (2)

[Claims] 1. An arbitrary continuous address is divided for each predetermined even number, and a line in which the predetermined even number addresses are continuously arranged in a horizontal direction from one end to the other end is a vertical line. A memory access device that writes data corresponding to the address into a data storage device including a first memory element and a second memory element, respectively, for a two-dimensional address arrangement provided in a plurality of memory devices. A first address generator for generating an address number for writing data corresponding to an odd address of the addresses to one memory element; and an even address of the addresses to the second memory element. A second address generator for generating an address number for writing the corresponding data, one having no corresponding data at the other end of the line Memory access apparatus characterized by having a dummy area inserting unit to apply each address. 2. An arbitrary continuous address is divided for each predetermined even number, and a line in which the predetermined even number addresses are continuously arranged in the horizontal direction from one end to the other end is a vertical line. A program executed by a memory access device for writing data corresponding to the address into a data storage device including a first memory element and a second memory element, for a two-dimensional address arrangement provided in plurality A first address generating process for generating an address number for writing data corresponding to an odd address among the addresses in the first memory element; and A second address generation process for generating an address number for writing data corresponding to an even address among the addresses to the memory element; The other end of the line, a recording medium recording a program for executing a dummy region insertion process of adding a single address with no corresponding data, respectively, to the memory access device.