JPH103324A - Information processor having high reliability clock - Google Patents

Abstract

PROBLEM TO BE SOLVED: To detect a clock stop where an unstable operation due to power source supply is a main cause and to surely change-over a clock by selecting one clock as a system clock only when the other clock is abnormal. SOLUTION: The counter A102 of a clock change-over circuit 101 counts-up in the rising edge of the clock A110 and an output 112 becomes a high level in a count N. The counter B counts-up in the rising edge of the clock B111 and the output 113 becomes the high level in the count M(M>N). The counter B 103 is reset when an R terminal becomes the high level. A clock A abnormality judging circuit 104 recognizes that the clock A is abnormal when an input 113 becomes the high level and permits the output 114 to be the high level. A selector 105 selects the clock A110 when the output 114 is the low level, selects the clock B111 when the output 114 is the high level and permits the clock to be the system clock 115.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus which operates in synchronization with a clock, and more particularly to an information processing apparatus having a highly reliable clock suitable for use in a control field requiring high reliability. .

[0002]

2. Description of the Related Art Control fields such as traffic and automobiles are important technologies that play a key role in society and require high reliability. In these control fields, it is generally controlled by a computer using a digital circuit synchronized with a clock. As a technique for increasing the reliability of a computer, there is a technique such as a multiplex system or a fault-tolerant computer that continues to operate even after failure. On these computers,
Consideration has also been given to increasing the reliability of clocks, and clock switching circuits that multiplex clocks and guarantee the continuity of clocks against clock failure during operation have been proposed.

[0003] As a conventional example of high clock reliability, for example, as described in Japanese Patent Application Laid-Open No. 4-241010,
There is a method for non-stop clock switching for a fault-tolerant computer. In this clock switching method, a timing polarity matching circuit for switching the clock after adjusting the phase of the clock when a clock abnormality is detected is provided, and the continuity of the clock is assured to a device to which the clock is supplied. Therefore, the device to which the clock is supplied can continue normal operation.

[0004]

The above prior art guarantees continuity with respect to a clock abnormality during operation of the information processing apparatus, and aims at non-stop of the entire information processing apparatus like a fault-tolerant computer. There are things.
However, in the field of low-cost control, the cost is too high and cannot be applied as it is.

Japanese Patent Laid-Open No. 1-280820 discloses a system in which a clock A and an auxiliary clock B are provided, and the clock A is switched to the clock B only while the clock A is stopped. Has been proposed. In this case, the clock frequencies of the clock A and the clock B are different from each other, and therefore, the clock frequency cannot be applied to the control field requiring high reliability to which the present invention is applied. In particular, in the control field, once the stopped clock A is recovered, the clock A is immediately returned to the clock A.
The No. 0 system tends to cause a problem in terms of clock continuity.

Further, Japanese Patent Application Laid-Open No. Sho 62-138914 discloses that clocks of each other are monitored by a clock disconnection detecting and holding circuit.
A clock circuit that selects a clock from one of the clock sources according to the result and outputs the clock in a divided form is shown. However, there is no specific disclosure about the detection of clock loss.

In order to increase the reliability even in a small and low-priced control field, it is important to reduce the size of a portion where a failure frequently occurs and to increase the reliability. From the experience of the clock failure event, the timing at which the most unstable operation occurs is
It is known that the power is turned on. In the above conventional example, clock failure during clock stable operation is assumed, and consideration is given to shortening the clock disconnection time in that case.However, prevention of malfunction due to unstable operation at power-on is particularly considered. Not.

SUMMARY OF THE INVENTION An object of the present invention is to provide an information processing apparatus having a highly reliable clock provided with means for detecting a clock abnormality caused by unstable operation due to power on or a clock stop caused by an initial failure and reliably switching the clock. It is.

[0009]

According to the present invention, there is provided an information processing apparatus having a highly reliable clock including a clock oscillation circuit A, a clock oscillation circuit B, and a clock switching circuit for selecting a normal clock. In the device, the clock switching circuit is configured to control the clock A of the clock oscillation circuit A.
Counter A cyclically counts from 0 to n and asserts an output at a predetermined count N;
The clock B of the clock oscillation circuit B is cyclically counted from 0 to m and a predetermined count M (M> N)
At this time, the output is asserted and the counter B resets the count with the output of the counter A. The clock oscillation circuit A is determined by the relationship between the output of the counter B and the counts M and N.
Alternatively, the present invention proposes an information processing device having a highly reliable clock, which includes a clock abnormality determination circuit that determines whether or not the clock oscillation circuit B is abnormal and a selector that selects the clock A or the clock B based on the output of the clock abnormality determination circuit. is there.

According to another aspect of the present invention, there is provided an information processing apparatus having a highly reliable clock including a clock oscillation circuit A, a clock oscillation circuit B, and a clock switching circuit for selecting a normal clock. The switching circuit changes the clock A of the clock oscillation circuit A from 0 to n
Counter A that cyclically counts up to a predetermined count N and asserts an output at a predetermined count N, and a clock M of a clock oscillation circuit B cyclically counts from 0 to m and a predetermined count M (M> N) A counter B that asserts its output and resets the count with the output of the counter A, and a clock that determines whether the clock oscillation circuit A or the clock oscillation circuit B is abnormal based on the relationship between the output of the counter B and the counts M and N. An abnormality determination circuit, and a selector for selecting a clock A or a clock B based on an output of the clock abnormality determination circuit, wherein the clock selected during the clock switching period from power-on to immediately before the substantial operation of the information processing apparatus starts. A high-speed signal with a means for fixing the clock abnormality judgment result so that the clock after that is used. It is intended to propose an information processing apparatus having a clock.

In the present invention, since the clock switching circuit is configured to output N at the counter A and reset the counter B, the output of the counter B is such that the frequency ratio between the clock A and the clock B is M / The output is asserted when N or more. Therefore, it can be considered that the count of the counter B indicates whether or not the clock A is abnormal.

When the clock switching circuit is operated only before the substantial start of the operation of the information processing apparatus, the clock is selected only during the period in which the frequency of occurrence of the failure is highest after the power is turned on, thereby ensuring the reliability. In addition, since the clock switching during the operation of the information processing device is prohibited, the timing matching circuit for guaranteeing the continuity of the clock during the operation of the information processing device becomes unnecessary, and the continuity of the clock during the operation of the information processing device is eliminated. Since the assurance function has been reduced, miniaturization is possible.

The clock switching circuit includes means for clearing the previous determination of the clock abnormality determination circuit when the clock oscillation circuit A starts operating normally after determining once that the clock is abnormal during the clock switching period. By doing so, an erroneous determination correction function that corrects the determination result after performing the determination once can be realized. For example, even if the difference between the counts of N and M is reduced to reduce the malfunction prevention accuracy to some extent and the erroneous judgment is made, the erroneous operation accompanying the erroneous decision can be corrected. Can be prevented.

In any of the above information processing apparatuses, the clock switching circuit can include means for monitoring which clock is fixed.

The clock switching circuit may include means for monitoring the operation of the selected clock oscillation circuit during the operation of the information processing device after the clock switching period.

In any of the information processing apparatuses, the difference (M−N) between the counts M and N is calculated more than the number of clock cycles corresponding to the difference between the initial oscillation rise times of the clock oscillation circuits after power-on, which is predicted in advance. Set larger. If M and N are set such that the expected difference in clock oscillation rise is predicted and the count difference M−N is larger than the difference, malfunction of the initial oscillation rise can be prevented.

Further, the difference (M−N) between the counts M and N is set to be larger than the difference between the number of clock cycles due to the unstable clock operation predicted in advance. Even if the frequency fluctuates after the power is turned on, if the frequency is smaller than the M / N ratio, the clock is not switched to the clock B, and the clock A always operates as the system clock. If the deviation of the expected rise of the clock oscillation is predicted in advance and M / N is set to be larger than the ratio, a malfunction at the rise of the initial oscillation can be prevented.

The clock switching circuit has a terminal for receiving a signal indicating whether or not the clock switching circuit is to be operated from the information processing device, and a clock switching circuit for selecting a predetermined clock when not operating. It is also possible to provide a fixing means. If this clock switching prohibition function is used, it is possible to mount only the oscillation circuit for the clock A on the same circuit board, and operate without the clock oscillation circuit for the clock B. That is, in an information processing device that requires high reliability by adopting a common clock switching circuit chip, high reliability is incorporated by incorporating all the functions described above, while in an information processing device that does not require much reliability, a clock is used. By omitting the clock oscillation circuit for B, downsizing and cost reduction by mass production can be achieved.

If the operation of the clock A becomes abnormal due to some influence during the operation of the information processing apparatus, the state is maintained and an alarm is continuously issued to the information processing apparatus. A monitoring means is provided for an information processing apparatus to check this signal to detect and maintain a failure of the clock A at an early stage. This function is effective for preventing a “double clock failure” in which one clock fails and operates while the other clock also fails, thereby ensuring reliability.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, referring to FIGS.
An embodiment of an information processing apparatus having a highly reliable clock according to the present invention will be described.

Embodiment 1 FIG. 1 is a block diagram showing a configuration of a clock switching circuit of Embodiment 1 of an information processing apparatus having a highly reliable clock according to the present invention. The clock switching circuit 101 includes a clock A110 and a clock B1.
11 is a circuit which takes in 11, selects one of the clocks, and outputs it as a system clock 115. The clock switching circuit 101 includes a counter A102 for counting the input clock A110, and a counter A102 for counting the input clock B110.
A counter B103 for counting 111 and a clock A
The circuit comprises an abnormality determination circuit 104 and a selector 105 for selecting either clock A110 or clock B111.

Counter A1 of clock switching circuit 101
02 is a rising edge at which the clock A110 goes high, counts up cyclically from 0 to n, and outputs 112 with a count N (generally n = N).
To a high level. That is, when the clock A is continuously oscillating, the output 11 is periodically output once every N cycles.
Set 2 to high level. When the clock A is stopped, the output 112 is kept at the low level.

The counter B103 cyclically counts up from 0 to m at the rising edge at which the clock B111 becomes high, and sets the output 113 to high at a count M (generally m = M). When the clock B is continuously oscillating, the output 113 is periodically set to the high level once every M cycles. When the clock B is stopped, the output 113 keeps the low level. Further, when the R terminal goes high, the counter B resets the count of the counter B to zero.

When the input signal 113 goes high once, the clock A abnormality determination circuit 104 recognizes that it is a clock A abnormality determination, holds the state, and sets the output 114 of the clock A abnormality determination circuit 104 to high level. I do. The selector 105 that receives the output 114 as an input
Is low, clock A is selected and output 114 is
Is high level, the clock B is selected and the clock is used as the system clock 115.

FIG. 2 is a diagram showing how the count of the counter B of the clock switching circuit of the first embodiment changes. Assuming the failure of clock A and clock B, the following 3
Divided into two types. (1) When the clock A fails and does not oscillate, and only the clock B oscillates, it operates as in type 1. Counter A
Does not make the output 112 high because the clock A is not oscillating and does not count up. Therefore, the counter B keeps counting up the clock B and counts up to the count M. (2) When both the clocks A and B oscillate normally, the circuit operates as in type 2. The counter A counts N of the clock A
In each cycle, the output 112 is set to the high level, and the R terminal of the counter B is asserted. When the R terminal is asserted, the counter B repeats a cycling operation from 0 to N as in type 2 in order to set the count to zero. (3) If only the clock A oscillates normally and the clock B does not oscillate, it operates as in type 3. Counter A
The output 112 goes high every N cycles of the clock, and the R terminal of the counter B is asserted. Counter B
When the R terminal is asserted, the count is set to zero, but the oscillation of the clock B is stopped.
Count remains at zero.

FIG. 3 is a table of truth values representing failure modes in the first embodiment. In an actual information processing apparatus, the simultaneous failure of the clock A and the clock B cannot be actually caused in view of the probability of occurrence, and therefore, if ignored, the pattern in which the clock A fails and switches to the clock B is a type It can be seen that the time is 1.

Since the clock switching circuit according to the first embodiment is configured to output N by the counter A and reset the counter B, the output 113 of the counter B
The output is asserted when the frequency ratio between the clock and the clock B is M / N or more. For this reason, it can be considered that the count itself of the counter B is an output indicating an abnormality of the clock A.

FIG. 4 is a diagram showing an example of the circuit configuration of the clock A abnormality determination circuit. This circuit has a function of holding the determination that the clock A is abnormal when the output 113 of the counter B is asserted even once.

FIG. 5 is a diagram for explaining a clock operation after power is turned on. FIG. 5A is a time chart when the clock B oscillates first after the power is turned on and then the clock A oscillates. FIG. 5A is a time chart when the clock A is turned on after the power is turned on.
5A is a time chart when the clock B oscillates without oscillating, and FIG. 5C is a time chart when the clock A oscillates but the clock B does not oscillate after the power is turned on.

There is no guarantee that clock A and clock B will rise at the same time when the power is turned on. Generally, the clocks A and B are shifted for a certain time as shown in FIG.

The above conventional example is a circuit related to clock switching in a state where the clock is stable, and malfunctions due to a deviation of the rising edge of clock oscillation. On the other hand, in the first embodiment, even if there is a shift of (M−N) with respect to the clock B after the power is turned on, the clock B is not switched to the clock B and the clock A To operate as a system clock. That is, the expected deviation of the rise of the clock oscillation is predicted, and the difference M−N of the count is calculated from the difference.
When M and N are set so as to increase, it is possible to prevent a malfunction at the rise of the initial oscillation.

Examples of specific numerical values of N and M are shown below. In the product catalog of the clock oscillation circuit, it generally takes about 10 ms until the clock is stabilized. Assuming that the oscillation frequency of the clock oscillation circuit is 10 MHz, about 100,000 pulses are generated until the clock is stabilized. As an extreme example, if one of the clocks oscillates immediately, but the other starts oscillating at a margin of 10 ms, the difference is about 100,000. In this case, N = 2
When M = 100,000 or more, malfunction can be prevented.

Another unstable operation of the clock when the power is turned on is a change in the clock oscillation frequency when the power is turned on. When the power is supplied to the clock oscillation circuit, the originally oscillated frequency is oscillated. However, when the initial operation is observed, a frequency obtained by dividing the originally expected frequency by n or a frequency obtained by multiplying n times is output. May settle on frequency. In other words, when the power is turned on, the circuit may oscillate at a frequency other than the expected frequency, so that the conventional circuit malfunctions. In the first embodiment, even if the frequency fluctuates after the power is turned on, if the frequency is smaller than the M / N ratio, the clock is not switched to the clock B but the clock A
Operate as a system clock. The expected clock oscillation rise deviation is predicted in advance, and M
When / N is set to a large value, malfunction at the rise of initial oscillation can be prevented.

FIG. 6 is a diagram showing how the count of the counter B of the clock switching circuit changes after the power is turned on in connection with the prevention of these two malfunctions. FIG. 6A shows a case where the oscillation rise times and frequencies of the clocks A and B are the same after the power is turned on, that is, a case where the operation is ideal.

On the other hand, FIG. 6B shows the case where the initial oscillation rise of the clock A is later than the initial oscillation rise of the clock B, and the difference between the initial oscillation rises of the clock B and the clock A is shown. The counter B counts more by the amount, but when the count of the counter A becomes N, the count of the counter B becomes zero, and thereafter, the counter B repeats the cyclic operation with the maximum count N. That is, since the counter B does not count up to M which is determined to be abnormal, no erroneous determination occurs. When the frequency of the clock A is lower than that of the clock B, the waveform becomes as shown in FIG. 6B. However, since the waveform is within the preset range, the counter B counts up to M which is recognized as abnormal. No erroneous determination does not occur.

FIG. 6C shows a case where the initial oscillation rise of the clock A is earlier than the initial oscillation rise of the clock B. The counter B counting the clock B outputs the signal when the R terminal is asserted as soon as the difference in the rise. Becomes zero.
Thereafter, the counter B repeats the cyclic operation at the maximum count N. That is, since the counter B does not count up to M that is determined to be abnormal, no erroneous determination occurs. When the frequency of the clock A is higher than that of the clock B, the waveform becomes as shown in FIG. 6C. However, since the waveform is within the preset range, the counter B counts up to M which is determined to be abnormal. No misjudgment occurs.

Looking at the above operation from another point of view, the difference between the rising of the clock A and the rising of the clock B when the power is turned on can be absorbed by the values of the counts N and M. If the rise time difference between the two clocks is close to the design value of the device, the difference between the counts N and M can be reduced, and the amount of hardware of the counter can be reduced.

Referring back to FIG. 5, in the case of FIG. 5A where the clock A is stopped, the clock A is selected as the system clock near (1), but the count of the counter B is At the point of time (2) when the clock becomes M, the clock B is selected as the system clock.

In the case of FIG. 5C in which the clock B is stopped, the clock B is not counted up, and the clock A is always output as the system clock.

FIG. 7 is a block diagram showing an embodiment of the information processing apparatus according to the present invention employing the clock switching circuit of the first embodiment. The information processing device 701 is a controller for high reliability control, and includes a CPU 702, an MCU 703,
Main memory 704, I / O-1, 705, I / O-2,
706, a clock oscillation circuit-A720, and a clock oscillation circuit-B721. The CPU 702 is connected to the MCU 703 via the processor bus 710. The MCU 703 is a memory controller and has a CP
If the access destination from the U 702 is the main memory 704,
The main memory 704 is accessed via the memory bus 711, and if it is an I / O access, the I / O-1, 705 or I / O-2, 706 is accessed via the system bus 712.

Focusing on the clock, the functional blocks operated by the clock include the CPU 702, the MCU 703, and the I / O
O-1,705 and I / O-2,706. Clock oscillation circuit-A720 and clock oscillation circuit-B721
Are clocks A110 and B111 having the same frequency.
Are supplied to the MCU 703, respectively.

FIG. 8 shows a memory management unit (MCU) 70
FIG. 3 is a block diagram showing an example of the internal configuration of No. 3; MCU7
Numeral 03 incorporates the clock switching circuit 101 according to the present invention, and supplies the system clock 115, which is the output of the clock switching circuit 101, to each functional block inside the MCU 703 and outside the MCU via the clock bus 732.

FIG. 9 is a block diagram showing an example of the internal configuration of the MCU of the information processing apparatus in which the frequency of the system clock of each functional block is different. The difference from the configuration of FIG.
Using the output 115 of the clock switching circuit 101 as a basic clock, a clock of a predetermined frequency is generated by the frequency multiplying circuit 901 and the frequency dividing circuit 902, and is output to the outside as a system clock.

As shown in FIG. 8 or FIG.
The clock switch 101 in the internal circuit 03 has a function of preventing malfunction of the clock switch circuit 101, always selects the clock on the normal oscillation side from the clocks A and B, and supplies the system clock of the entire information processing apparatus. An information processing device having a highly reliable clock can be constructed.

<< Embodiment 2 >> FIG. 10 is a block diagram showing a configuration of a clock switching circuit according to Embodiment 2 of the present invention.
FIG. 8 is a circuit diagram illustrating a configuration of a clock A abnormality determination circuit according to a second embodiment. The difference between the clock switching circuit 101 in the second embodiment in FIG. 10 and the clock switching circuit 101 in the first embodiment in FIG. 1 is that the output 112 of the counter A is connected to the clock A abnormality determination circuit 1004. Further, the difference between the clock A abnormality determination circuit of FIG. 11 and the clock A abnormality determination circuit of FIG.
Is connected to the output 112 of the counter A.

In the second embodiment, even after the clock A abnormality determination circuit has once determined that an abnormality has occurred, when the clock A starts operating, the determination information held in the FF 104 is cleared. Therefore, it is possible to realize an erroneous determination correction function of correcting the determination result after performing the determination once. In the first embodiment, measures are taken to prevent erroneous determination. However, in the second embodiment, for example, the difference between the N and M counts is reduced to reduce the erroneous operation prevention accuracy to some extent. Since the malfunction associated with the counter can be corrected, the malfunction can be substantially prevented while reducing the amount of hardware of the counter.

Third Embodiment FIG. 12 is a block diagram showing a configuration of a clock switching circuit 101 according to a third embodiment, and FIG. 13 is a circuit diagram showing a configuration of a clock A abnormality determination circuit according to the third embodiment. . The difference between the clock switching circuit 101 in FIG. 10 and the clock switching circuit 101 in FIG. 12 is that a signal 1201 is input to the clock A abnormality determination circuit. A signal 1201 is a signal output from a memory control unit, which is an internal logic (not shown) of the MCU 703, and is an operation start signal of the information processing device 701 according to the third embodiment.

FIG. 15 is a time chart showing the output signal 1201 of the MCU together with the system clock. The state of the information processing apparatus after power-on can be divided into a period 1, a period 2, and a period 3 depending on the relationship between the power-on reset and the output signal 1201 of the MCU. Period 1 is a state before the information processing apparatus substantially starts operating even when the power is turned on. Period 2 is a period in which the power-on reset is valid, but a part of the information processing device is operating. The operation in the period 2 includes a memory power-up process and the like. Period 3 is a period in which the instruction fetch starts after the power-on reset has expired and the information processing device operates according to the program. Depending on the system configuration, there is a case where the period 2 does not exist or an operation mode is determined by dividing the period more finely.

What is important in the third embodiment is that the clock switching circuit is operated only in a state before the actual operation of the information processing apparatus is started.

The specific operation of the third embodiment will be described. FIG.
, The output signal 1201 of the MCU is
01 and outputs an inverted signal 1304. The AND circuits 1302 and 1303 perform a logical product operation of the inverted signal 1304 and the signal 113, respectively.
4 and 112 are ANDed. Inverted signal 130
4 is at a high level only during period 1, and the signal 113,
The signal 112 is propagated to the subsequent stage.
The signal goes to low level, and the signals 113 and 112 are masked.
That is, the clock switching circuit 101 operates actively only during a period before the information processing apparatus substantially starts operating, holds the clock switching state at the start of the operation, and thereafter performs the clock switching function. Lock.

According to this method, clock switching is prohibited during operation of the information processing apparatus while selecting a clock only during the period in which the frequency of occurrence of a failure occurs most frequently after power-on and ensuring reliability. In addition, a timing matching circuit for guaranteeing the continuity of the clock is unnecessary, and the function of guaranteeing the continuity of the clock during the operation of the information processing apparatus is reduced, so that the size can be reduced.

Fourth Embodiment FIG. 14 is a block diagram showing a fourth embodiment of the clock switching circuit 101. A difference between the clock switching circuit 101 in FIG. 13 and the clock switching circuit 101 in FIG. 14 is that a monitoring function of a clock operation is added. The monitoring function of this clock operation is AND
The circuit 1403, the FF 1402, and the monitoring signal 141
This can be realized by adding 1,1410 output terminals. A
The ND circuit 1403 outputs the output signals 1201 and 11 of the MCU.
3 is executed, and only when the information processing device is operating,
The signal 113 is propagated to the subsequent stage. FIG. 15 also shows the monitoring operation of the clock A abnormality. When the output signal 1201 of the MCU goes high, a monitoring operation is performed. The FF 1402 holds the state when the signal 113 goes high even once during the operation of the information processing apparatus.
That is, when the operation of the clock A becomes abnormal due to some influence during the operation of the information processing apparatus, the state is maintained, and an alarm is continuously issued to the information processing apparatus by the signal 1410. The signal 1411 provides monitoring means for the information processing apparatus to check this signal to detect and maintain the failure of the clock A at an early stage.

These functions are effective to prevent a "double clock failure" in which one clock fails and the other clock also fails while operating, thereby ensuring reliability. .

Fifth Embodiment FIG. 16 is a block diagram showing a fifth embodiment of the clock switching circuit 101. A difference between the clock switching circuit 101 in FIG. 14 and the clock switching circuit 101 in FIG. 16 is that a function for inhibiting a clock switching operation is added. This prohibition function is performed by NOR1
This can be realized by adding a terminal 601 and a terminal for the operation inhibition control signal 1602. When the terminal 1602 is connected to the GND of the board, the NOR 1602 propagates the output signal 1201 of the MCU. In this case, the predetermined operation described above is performed. On the other hand, when the terminal 1602 is connected to the VCC of the substrate, the NOR 1601 masks the output signal 1201 of the MCU, so that the output is always at the low level and the FF4
The clock switching operation is prohibited without changing the state of 01. If this function is used, only the oscillation circuit for the clock A can be mounted on the same circuit board, and the clock oscillation circuit for the clock B can be removed to operate. That is, in an information processing device that requires high reliability by adopting a chip of the common clock switching circuit 101 and incorporates all of the above functions to achieve high reliability, in an information processing device that does not require much reliability, Clock B
By omitting a clock oscillation circuit for the above, it is possible to achieve downsizing and cost reduction by mass production.

[0055]

According to the present invention, the clock A is changed from 0 to n.
A counter A that cyclically counts up to and asserts an output at a predetermined count N;
Is cyclically counted from 0 to m, and when a predetermined count M (M> N) is asserted, the output is asserted and the count is reset by the output of the counter A; the output of the counter B; And a selector for selecting a clock A or a clock B based on the output of the clock abnormality determination circuit. Only the clock B is selected as the system clock.
Erroneous determination due to a clock abnormality within the range determined by the above.

Further, the clock switching circuit is operated only at the place where the frequency of the clock failure is high immediately after the power is turned on, thereby improving the reliability, and the clock switching circuit is fixed at the places where the frequency of the failure is low. Since the functions such as the timing matching circuit required for switching can be reduced, the clock portion of the information processing device can be downsized and the cost can be reduced while maintaining the required reliability.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a clock switching circuit according to a first embodiment of an information processing apparatus having a highly reliable clock according to the present invention.

FIG. 2 is a diagram illustrating how the count of a counter B of the clock switching circuit according to the first embodiment changes.

FIG. 3 is a table of truth values representing failure modes in the first embodiment.

FIG. 4 is a diagram illustrating an example of a circuit configuration of a clock A abnormality determination circuit.

FIG. 5 is a diagram illustrating a clock operation after power is turned on.

FIG. 6 is a diagram showing a state of a change in the count of a counter B of the clock switching circuit after power-on, in relation to the prevention of malfunction.

FIG. 7 is a block diagram showing an embodiment of the information processing apparatus according to the present invention employing the clock switching circuit of Embodiment 1.

FIG. 8 is a block diagram illustrating an example of an internal configuration of a memory management unit (MCU).

FIG. 9 is a block diagram illustrating an example of an internal configuration of an MCU of the information processing device in which the system clock frequency of each functional block is different.

FIG. 10 is a block diagram illustrating a configuration of a second embodiment of the clock switching circuit.

FIG. 11 is a circuit diagram illustrating a configuration of a clock A abnormality determination circuit according to a second embodiment.

FIG. 12 is a block diagram illustrating a configuration of a third embodiment of the clock switching circuit.

FIG. 13 is a circuit diagram illustrating a configuration of a clock A abnormality determination circuit according to a third embodiment.

FIG. 14 is a block diagram showing a fourth embodiment of a clock switching circuit to which a monitoring function is added.

FIG. 15 is a time chart showing together an MCU output signal and a clock A abnormality monitoring operation with reference to a system clock.

FIG. 16 is a block diagram showing a fifth embodiment of a clock switching circuit to which a function of inhibiting a clock switching operation has been added;

[Description of Signs] 101 Clock switching circuit 102 Counter A 103 Counter B 104 Clock A abnormality determination circuit 105 Selector 110 Clock A 111 Clock B 112 Output of counter A 113 Output of counter B 114 Output of clock A abnormality determination circuit 115 System clock 701 Information processing device 702 CPU 703 Memory control unit (MCU) 704 Main memory 705 I / O-1 706 I / O-2 710 Processor bus 711 Memory bus 712 System bus 720 Clock oscillation circuit A 721 Clock oscillation circuit B 732 System clock 901 Doubler circuit 902 Divider circuit 1004 Clock A abnormality determination circuit 1201 Output signal of memory control unit 703 1204 Clock A abnormality determination circuit 1301 Inverter 13 02 AND 1303 AND 1304 Inverted signal 1402 FF 1403 AND 1404 Improved clock switching circuit 1410 Monitoring signal 1411 Monitoring signal

Continued on the front page (72) Inventor Takashi Hotta 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture Inside Hitachi, Ltd.Hitachi Research Laboratories (72) Inventor Takashi Kiyono 882, Ichimo, Ichimo, Hitachinaka City, Ibaraki Prefecture, Ltd. Within Hitachi Measuring Instruments Division (72) Inventor Yuji Sugaya 882 Momo, Oaza, Hitachinaka City, Ibaraki Prefecture Inside Hitachi Instruments Measuring Instruments Division

Claims (8)

[Claims] 1. An information processing apparatus having a highly reliable clock including a clock oscillation circuit A, a clock oscillation circuit B, and a clock switching circuit for selecting a normal clock, wherein the clock switching circuit comprises a clock of the clock oscillation circuit A. A counter A that cyclically counts A from 0 to n and asserts an output at a predetermined count N; and a predetermined count that cyclically counts clock B of the clock oscillation circuit B from 0 to m. A counter B that asserts the output when M (M> N) and resets the count with the output of the counter A;
The clock oscillating circuit A or the clock oscillating circuit B according to the relationship between the output of the counter B and the counts M and N.
An information processing apparatus having a highly reliable clock, comprising: a clock abnormality determination circuit that determines the presence or absence of an abnormality in the clock; and a selector that selects the clock A or the clock B based on an output of the clock abnormality determination circuit. 2. An information processing apparatus having a highly reliable clock including a clock oscillation circuit A, a clock oscillation circuit B, and a clock switching circuit for selecting a normal clock, wherein the clock switching circuit includes a clock of the clock oscillation circuit A. A counter A that cyclically counts A from 0 to n and asserts an output at a predetermined count N; and a predetermined count that cyclically counts clock B of the clock oscillation circuit B from 0 to m. A counter B that asserts the output when M (M> N) and resets the count with the output of the counter A;
The clock oscillating circuit A or the clock oscillating circuit B according to the relationship between the output of the counter B and the counts M and N.
And a selector for selecting the clock A or the clock B based on the output of the clock abnormality determination circuit, and immediately before the substantial operation of the information processing apparatus starts from power-on. An information processing apparatus having a highly reliable clock, comprising: means for fixing the clock abnormality determination result so that the clock selected during the clock switching period up to the clock switching is used as a clock after that. 3. The information processing device having a highly reliable clock according to claim 2, wherein the clock switching circuit operates normally after the clock switching circuit determines once that the clock is abnormal during the clock switching period. An information processing apparatus having a high-reliability clock, comprising means for clearing the previous determination of the clock abnormality determination circuit when the operation is started. 4. The information processing apparatus having a highly reliable clock according to claim 1, wherein said clock switching circuit includes means for monitoring which clock is fixed. An information processing device having a highly reliable clock. 5. The information processing device having a highly reliable clock according to claim 2, wherein the clock switching circuit operates the selected clock oscillation circuit during the operation of the information processing device after the clock switching period. An information processing apparatus having a highly reliable clock, comprising: 6. The information processing apparatus having a highly reliable clock according to claim 1, wherein the information corresponds to a difference between a predicted initial oscillation rise time of each clock oscillation circuit after power-on. An information processing apparatus having a highly reliable clock, wherein the difference (M-N) between the counts M and N is set to be larger than the number of clock cycles. 7. The information processing device having a highly reliable clock according to claim 1, wherein the counts M and N are larger than a difference between the number of clock cycles due to a clock unstable operation predicted in advance. An information processing apparatus having a highly reliable clock, wherein the difference (M−N) is set to be large. 8. The information processing device having a highly reliable clock according to claim 1, wherein the clock switching circuit outputs a signal indicating whether to operate the clock switching circuit. An information processing apparatus having a high-reliability clock, comprising: a terminal for taking in data from the information processing apparatus; and means for fixing the clock switching circuit so as to select a predetermined clock when not operating.