JPH10326827A - Method for manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device, wherein a reliable semiconductor device of constant electric performance is obtained in less adjustment processes through stable adjustment in quality while quickly coping with slight specification changes in the semiconductor device. SOLUTION: A circuit element is formed on a semiconductor substrate 1 while a first interlayer insulating film 2 is provided on the semiconductor substrate, and a first wiring pattern 3 is formed so as to be connected to the circuit element through a contact hole. After the first wiring pattern has been formed, the electric characteristics of the circuit element formed on the semiconductor substrate is measured via a monitor point of the wiring pattern. Then, a second interlayer insulating film 4 is provided on the first wiring pattern 3, and based on the measuring result of the electric characteristics, a formation place is adjusted to form a contact hole at the second interlayer insulating film 4 for connection to the wiring pattern of the first layer, and a second wiring pattern 7 is formed on the second interlayer insulating film.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having a fixed electric characteristic while correcting a variation in a manufacturing process, or a specially changed electric characteristic. More specifically, the present invention relates to a method for manufacturing a semiconductor device capable of efficiently adjusting electric characteristics and performing stable adjustment.

[0002]

2. Description of the Related Art In a conventional semiconductor device, a circuit element such as a diode, a transistor, or a resistor is formed on a semiconductor substrate, and a resistance film or a capacitor is formed on an insulating film provided on the surface of the semiconductor substrate. A wiring pattern is formed on each interlayer insulating film provided thereon, and connected to a circuit element and a wiring pattern below the interlayer insulating film via a contact hole provided in the interlayer insulating film,
An integrated circuit connecting desired circuit elements is formed.

In this semiconductor device, circuit elements formed on an insulating film such as a resistive film and a capacitor, and circuit elements such as a transistor and a resistor formed in a semiconductor substrate include:
Due to variations in the manufacturing process, depending on the wafer,
Or, even in the same wafer, its electrical characteristics may be different depending on the chip in the different place. Further, there is a case where a similar product whose electric characteristics are partially changed is requested by a user. Conventionally, when correcting the manufacturing variation to stabilize the electrical characteristics or partially change the specifications of the electrical characteristics, conventionally, the electrical characteristics are measured one by one while measuring the electrical characteristics at the final stage of the manufacturing process. The adjustment is performed for each chip.

For such adjustment, for example, as shown in FIG. 4 which illustrates the principle of adjustment in the case of resistors and capacitors, resistors R1 to R3 and capacitors C1 to C3 are connected in parallel in opposite directions. A Zener diode (Zener zap) D is built in the circuit, and each Zener diode D is short-circuited by an overcurrent one by one, or the wiring and the like are cut by a method called laser trimming by irradiating a laser beam (point A). ). That is, by short-circuiting the Zener diode D connected in parallel with the resistors R1 to R3 or the capacitors C1 to C3, the resistance value at both ends of the circuit can be reduced or the capacitance value can be increased (FIGS. 4A to 4C). b)). Also,
By cutting (point A) a part of the resistor R0 and the capacitors C1 to C3 connected in parallel, the resistance value at both ends can be increased or the capacitance value can be reduced (FIG. 4 (c)). )-(D)). This adjustment is not limited to resistors and capacitors, such as changing the connection of transistors etc.,
Circuit constants can also be adjusted by changing the bias.

[0005]

In a conventional method of manufacturing a semiconductor device, a large number of chips formed on a wafer are separated from each other in the state of a wafer or after each chip, and all of the chips are electrically connected one by one. Adjustments must be made while checking the characteristics, resulting in a problem that it takes a lot of man-hours and increases the cost.

In addition, since the diode is short-circuited due to an overcurrent, or a part of a wiring or a part is cut and adjusted by irradiating a laser beam, the state of the short-circuit or disconnection is not constant and short-circuit is subsequently performed. However, there is a problem that the characteristics are fluctuated due to an open circuit or a short circuit at a cut position, resulting in a lack of reliability.

The present invention solves such a problem, and can obtain a highly reliable semiconductor device having a stable electric performance with a small adjustment man-hour and stable quality. It is an object of the present invention to provide a method for manufacturing a semiconductor device capable of responding promptly to various specification changes.

[0008]

According to the method of manufacturing a semiconductor device of the present invention, (a) a circuit element is formed on a semiconductor substrate, (b) a first interlayer insulating film is provided on the semiconductor substrate, and a contact hole is formed. (C) forming a first wiring pattern so as to be electrically connected to the circuit element via the (through hole);
After forming the first wiring pattern, electrical characteristics of a circuit element formed on the semiconductor substrate are measured via the monitoring pad of the wiring pattern, and (d) a second wiring pattern is formed on the first wiring pattern. And (e) forming a contact hole by adjusting a formation position of a contact hole provided in the second interlayer insulating film for connection with the first wiring pattern based on a result of the measurement of the electric characteristics. And
(F) A second wiring pattern is formed on the second interlayer insulating film.

The wafer is divided into blocks each including a plurality of chips, and the electrical characteristics are measured using one chip in each block. Based on the measurement result, the second interlayer insulating film is formed for each block. By deciding where to form the contact holes, the chips in the blocks having similar characteristics can be adjusted collectively, so that the adjustment can be performed much more efficiently than the adjustment of each chip.

If the block that divides the wafer is an area where exposure is performed once by a stepper, the mask can be adjusted in units of exposure by the stepper, and
Since the electrical characteristics of each chip are manufactured with almost the same performance, it is more efficient.

The original contact hole forming mask is changed by exposing the contact hole forming position to a predetermined contact hole forming mask and further exposing the contact hole forming position adjusting mask to exposure. The desired adjustment can be performed without performing.

[0012]

Next, a method of manufacturing a semiconductor device according to the present invention will be described with reference to the drawings.

In the method of manufacturing a semiconductor device according to the present invention, as shown in FIG. 1, a plan view of a wafer in one step and a perspective view of one chip thereof are shown. A circuit element such as a resistor is formed on a semiconductor layer and, if necessary, an insulating film (not shown), and a first interlayer insulating film 2 is formed thereon. As the interlayer insulating film 2, a silicon nitride film or a silicon oxide film having a thickness of about 0.3 to 1 μm is used. Then, after forming a contact hole (not shown) in the interlayer insulating film 2, a first wiring pattern 3 is formed, and the above-described circuit elements (not shown) are connected by wiring. That is, the contact holes are provided for connection between a circuit element (not shown) and the first wiring pattern 3. The main parts of the first wiring pattern 3 include:
A plurality of monitor pads 3a are simultaneously formed,
By bringing the probe electrode into contact with the monitor pad 3a, it is possible to check the electrical characteristics between desired circuits.

Then, by measuring the desired electrical characteristics,
It is checked how the first wiring pattern 3 should be connected. For example, if the end wiring 3c of the first wiring pattern 3 is not connected, a part of the resistance or the like is not connected and desired electrical characteristics are obtained. Is obtained. After this,
As shown in FIG. 2, a second interlayer insulating film 4 is formed on the surface of the first wiring pattern 3. The interlayer insulating film 4 is made of a silicon nitride film or a silicon oxide film having a thickness of 0.5 to 1 in the same manner as described above.
One having a thickness of about μm is used. Then, a resist film (not shown) is formed on the surface thereof, and a contact hole forming mask 5 as usual is superimposed, and further a contact hole adjusting mask 6 obtained based on the above-described measurement results is superimposed. This contact hole forming mask 5 is
A so-called exposure photomask (reticle) is provided with a light-shielding metal sputtered film 5b on glass, quartz glass, or the like, and openings 5a, 5c formed only in the exposed portions. Also, contact hole adjusting mask 6
For example, in the case where the end wiring 3c is not connected according to the measurement result of the electric characteristics described above, as shown in FIG. 2, a contact hole forming mask is formed so that a contact hole is not formed on the end wiring 3c. 5 is made of glass or the like on which a light-shielding pattern 6c is formed so as to cover only the pattern opening 5c at the end. The contact hole adjusting mask 6 is formed in a pattern assuming various cases covering any of the openings 5a of the contact hole forming mask 5, so that a desired pattern can be formed according to the result of the electric characteristics. The masks may be overlapped so as to overlap. Thereafter, exposure is performed by a stepper, and a resist film is patterned and etched, so that a contact hole (not shown) is formed along the opening 5a of the contact hole forming mask 5.

Thereafter, Al is provided on the entire surface by vapor deposition or the like and is patterned to form a second wiring pattern 7 connected to the first wiring pattern 3 through the contact hole 4a, as shown in FIG. It is formed. At this time, the end wiring 3c of the first wiring pattern 3 has a contact hole adjusting mask 6 in which the pattern opening 5c at the end of the contact hole forming mask 5 is blinded. Are not formed, and the end wiring 3c and the end wiring 7c of the second wiring pattern 7 are not connected as shown in the sectional view taken along the line BB of FIG. As a result, desired electric characteristics can be obtained.

Although the above description is for one chip, almost the same electrical characteristics can be obtained in adjacent and close areas even if there are variations in the manufacturing process within the wafer. Therefore, as shown in FIG. 1, electric characteristics are measured using a certain block G in the wafer as one unit and one chip in the block as a monitor, and the entire block G is measured based on the measurement result. By adjusting the exposure pattern of the chip, the electrical characteristics of many chips can be adjusted at once while saving time due to measurement. In this case, the above-mentioned monitor pad 3a may be provided on all chips, or may be provided on a chip for checking the electrical characteristics of each block, for example, only one of the ends. The above-described block G is divided into blocks for each shot (area to be exposed at one time) by the stepper. However, since the exposure is adjusted by the contact hole adjusting mask, the adjusting mask may be overlapped with the exposure. It is possible and preferable.

According to the method of the present invention, the electric characteristics of each chip are not adjusted while measuring the electric characteristics of each chip after the end of the manufacturing process, but the electric characteristics of the chip are checked in the middle of the manufacturing process. However, since the connection of the wiring pattern is adjusted through the contact hole of the interlayer insulating film, stable adjustment is obtained unlike the case of short-circuiting parts or cutting the wiring, etc. There is no decrease in reliability. Further, the cause of the abnormality at the manufacturing stage can be fed back promptly, quality control can be sufficiently performed, and the yield can be improved.

Further, the chips in the wafer are divided into blocks, and the blocks are collectively adjusted only by measuring one chip per block, thereby adjusting several tens of chips at a time. Because one can
It is possible to adjust the electrical characteristics of a large number of chips in a very short time as compared with performing adjustment while performing individual measurement. In addition, since neighboring chips having similar electric characteristics are collectively adjusted in the state of the wafer, the quality is uniform and the electric characteristics can be adjusted efficiently even in the case of mass production. In addition, by performing this block unit in, for example, a shot unit of a stepper, adjustment of a contact hole formation place can be efficiently performed by a contact hole adjusting mask in a shot unit. Moreover, almost the entire wafer can be efficiently adjusted only by the blind program for the number of shots, and semiconductor devices having stable electric characteristics can be mass-produced at low cost.

Further, in the above-described example, the first interlayer insulating film 2
Is an example in which only the first wiring pattern is formed. However, a resistive film, a capacitor, and the like are formed on the first interlayer insulating film 2, and the connection portion is provided in the second interlayer insulating film. By adjusting the contact hole, the resistance value, the capacitance value, and the like can be adjusted.

[0020]

According to the present invention, since the adjustment is performed by adjusting the contact hole formation position while checking the electrical characteristics during the manufacturing process, the adjustment reliability is very high. In addition, since the adjustment is performed collectively for each block, it is not necessary to make the adjustment while measuring the electrical characteristics of all the chips, so that the adjustment can be performed with a very small number of steps. As a result, it is possible to freely change the circuit constant in a short time and at low cost in response to manufacturing variations and a request to change the specifications from the user, and it is possible to improve the electrical characteristics.

Furthermore, since feedback can be provided at the manufacturing stage, it is possible to immediately take measures against the occurrence of an abnormality, which leads to simplification of adjustment work and excellent quality control.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of one manufacturing process of one embodiment of a method for manufacturing a semiconductor device of the present invention.

FIG. 2 is an explanatory diagram of one manufacturing process of one embodiment of a method for manufacturing a semiconductor device of the present invention.

FIG. 3 is an explanatory diagram of one manufacturing process of one embodiment of the method for manufacturing a semiconductor device of the present invention.

FIG. 4 is a diagram illustrating the principle of adjustment of electrical characteristics.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 semiconductor substrate 2 first interlayer insulating film 3 first wiring pattern 3 a monitor pad 4 second interlayer insulating film 6 contact hole adjusting mask 7 second wiring pattern

Claims (4)

[Claims] (A) forming a circuit element on a semiconductor substrate;
(B) providing a first interlayer insulating film on the semiconductor substrate, forming a first wiring pattern so as to be electrically connected to the circuit element via a contact hole;
After the wiring pattern is formed, the electrical characteristics of the circuit element formed on the semiconductor substrate are measured via the monitoring pad of the wiring pattern, and (d) a second interlayer insulating film is formed on the first wiring pattern. (E) forming a contact hole by adjusting a formation location of a contact hole provided in the second interlayer insulating film for connection with the first wiring pattern based on a result of the measurement of the electrical characteristics; f) A method of manufacturing a semiconductor device, wherein a second wiring pattern is formed on the second interlayer insulating film. 2. A wafer is divided into blocks each composed of a plurality of chips, the electric characteristics are measured by one chip in each block, and the second interlayer insulating is provided for each block based on a result of the measurement. 2. The method for manufacturing a semiconductor device according to claim 1, wherein a location where the contact hole of the film is formed is determined. 3. The method of manufacturing a semiconductor device according to claim 2, wherein the block for dividing the wafer is an area to be exposed at one time by a stepper. 4. The method according to claim 1, wherein the adjustment of the contact hole formation location is performed by further exposing a contact hole formation location adjustment mask on a predetermined contact hole formation mask. Semiconductor device manufacturing method.