JPH10326488A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device that is provided with an input buffer circuit corresponding to a small-amplitude interface reduced in power consumption. SOLUTION: This device such as synchronous dynamic random access memory etc., is composed by installing an input buffer circuit corresponding to a small-amplitude interface. A control signal generator circuit 20 is installed, which generates a control signal, CKEE signal, that makes the active element M5 constituting the bias current source of a differential amplifier circuit 10 installed in the input buffer circuit on for a certain period of time including the rising point of time (or the falling point of time) of the clock signal. By this, the bias current of the differential amplifier circuit 10 is made to flow a certain period of time which includes the rising point of time (or falling point of time) of the clock signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION This invention relates to a semiconductor integrated circuit device, especially, a synchronous dynamic random access memory operating in synchronization with a clock signal (DRAM; D ynamic R andom A cces
in s M emory), etc., a technique effectively applied to an input buffer circuit or the like corresponding to the small amplitude interface.

[0002]

2. Description of the Related Art Conventionally, in a synchronous dynamic random access memory (hereinafter referred to as a synchronous DRAM) which operates in synchronization with a clock signal,
SSTL (S tub S eries T erminate
The input buffer circuit corresponding to the d transceiver L ogic) small-amplitude interface such, the differential amplifier circuit has been used.

FIG. 17 is a diagram showing a circuit configuration of an input buffer circuit corresponding to a small-amplitude interface in a conventional synchronous DRAM and a timing chart thereof.

As shown in FIG. 1A, a conventional input buffer circuit includes an input signal (Vin) and a reference voltage (Vre).
f) and a logic circuit unit 13 for comparing the differential amplifier circuit 10 with the differential amplifier circuit 10). The differential amplifier circuit 10 is a current mirror-coupled P-type MOS transistor (hereinafter, referred to as a PMOSFET) (M1, M2) constituting an active load circuit.
And an N-type MOSFET (hereinafter referred to as an NMOSFET) in which an input signal (Vin) and a reference voltage (Vref) are applied to a gate electrode (hereinafter, simply referred to as a gate), respectively.
Called. ) (M3, M4) and NMOSFET (M
3) or NMOS FE which constitutes a bias current source for bias current (Ibi) flowing through NMOSFET (M4)
T (M5).

The output (Vbi) of the inverter 21 (ie, the inverted signal of the power down signal (PWDN) of the synchronous DRAM) is applied to the gate of the NMOS transistor (M5).

The logic circuit unit 13 includes a PM connected between a power supply potential (VDD) and an output terminal (OUT).
OSFET (M6, M8), NMOSFET cascaded between output terminal (OUT) and reference potential (GND)
(M7, M9). This PMOSFET (M
6) and the output of the differential amplifier circuit 10 are applied to the gates of the NMOSFET (M7).
The output (Vbi) of the inverter 21 is applied to the gates of (M8) and the NMOSFET (M9).

Therefore, as shown in FIG.
When the power down signal (PWDN) is at a low level (hereinafter, referred to as
Simply referred to as L level. ), When the input signal (Vin) is at a high level (hereinafter, simply referred to as an H level), the output of the differential amplifier circuit 10 is at an L level and PM
The output of the CMOS inverter composed of the OSFET (M6) and the NMOSFET (M7) goes high, and the output (OUT) of the input buffer circuit goes high. Similarly, when the input signal (Vin) is at the high level, the output of the differential amplifier circuit 10 is at the high level,
The output of the CMOS inverter composed of the SFET (M6) and the NMOSFET (M7) goes low, and the output (OUT) of the input buffer circuit goes low.

In this case, the power down signal (PWD)
When N) is at the low level (ie, other than during power down)
In the differential amplifier circuit 10, the bias current (Ib
i) is flowing.

[0009]

As described above, in the input buffer circuit corresponding to the small-amplitude interface in the conventional synchronous DRAM, the differential amplifier circuit 10 of the input buffer circuit is always used except during power down.
, A bias current (Ibi) flows. The current (Ibi) that constantly flows through the differential amplifier circuit 10 of the input buffer circuit is, for example, a current on the order of several mA in the case of a 16M synchronous DRAM.

For example, in the case of a synchronous graphics RAM for image use having 32 data I / O pins for input data and output data, each of these I / O pins is
One input buffer circuit is mounted on the / O pin, and when the address pins and the control signal pins are combined, a total of 52 input buffer circuits are mounted per chip.

Therefore, the power consumed by the bias current (Ibi) constantly flowing through the differential amplifier circuit 10 of the input buffer circuit is several hundred mW per chip.

As described above, in the conventional semiconductor integrated circuit device, a large amount of power is consumed by the bias current that always flows through the differential amplifier circuit of the input buffer circuit.
There is a problem that it is difficult to reduce power consumption.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art, and it is an object of the present invention to provide a semiconductor integrated circuit device having an input buffer circuit compatible with a small-amplitude interface, and having a low power consumption. It is an object of the present invention to provide a technology capable of reducing the noise.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0015]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

In a semiconductor integrated circuit device such as a synchronous dynamic random access memory having an input buffer circuit corresponding to a small amplitude interface,
A control signal for generating a control signal for turning on an active element constituting a bias current source of a differential amplifier circuit provided in the input buffer circuit for a certain period including a rising point (or a falling point) of a clock signal A generating circuit, and thereby, a bias current of the differential amplifier circuit,
The clock signal is caused to flow only for a certain period including the rising point (or the falling point).

[0017]

Embodiments of the present invention will be described below in detail with reference to the drawings.

In all the drawings for describing the embodiments of the present invention, components having the same functions are denoted by the same reference numerals, and their repeated description will be omitted.

FIG. 1 is a diagram showing a circuit configuration of an example of an input buffer circuit in a semiconductor integrated circuit device according to an embodiment of the present invention, and a timing chart thereof.

As shown in FIG. 1A, the input buffer circuit shown in FIG. 1 includes current mirror-coupled PMOSFETs (M1, M2) constituting an active load circuit, and N
MOSFET (M3, M4) and NMOSFET (M
5), a CKEE control signal generation circuit 20, an inverter 11 that outputs an inverted signal of the CKEE signal, an inverted signal of the CKEE signal, and a power down signal of the synchronous DRAM ( PWD
N), a NOR gate 12 that takes a NOR logic with
SFET (M6, M8) and NMOSFET (M7, M
9).

As shown in FIG. 2B, the CKEE control signal generation circuit 20 outputs H for a period (Ts + Th) including the rising time of the clock signal (CLK) (or straddling the rising edge of the clock signal (CLK)). A pulse signal (hereinafter, referred to as a CKEE signal) serving as a level is generated.

The output (Vbi) of the NOR gate 12 is connected to an NMO
It is applied to the gate of the SFET (M5), and the power-down signal (PWDN) is low except when the power is down.
In the case of the level, the output of the NOR gate 12 (Vbi)
Is the CKEE signal.

Thus, the NMOSFET (M5)
Is turned on only for a period (Ts + Th) including the rising point of the clock signal (CLK). Therefore, the bias current (Ibi) of the differential amplifier circuit 10 is set in the period (Ts
+ Th), and the average bias current flowing through the differential amplifier circuit 10 can be reduced. That is,
Assuming that the cycle of the clock signal (CLK) is T, the average bias current can be reduced to {(Ts + Th) / T} times that of the conventional circuit.

The output (Vbi) of the NOR gate 12
Is at the L level, the bias current (Ibi) of the differential amplifier circuit 10 is cut off.
The output potential of 0 becomes floating. In this case, the PMOSFET (M8) is turned on, and the output potential (OUT) of the input buffer circuit is held at the H level.

The semiconductor integrated circuit device according to the present embodiment is applied to, for example, a synchronous DRAM or the like. Here, the synchronous DRAM is a memory synchronized according to a clock signal (CLK). , Various command signals are captured and latched in synchronization with the rising edge of the clock signal (CLK). For this reason,
The input buffer circuits for the data I / O pins, address signal pins, and various control signal pins need only operate for a period (Ts + Th) including the rising point of the clock signal (CLK).

Here, the period (Ts) and the period (Th) shown in FIG. 1B correspond to the clock signal (C) of the CKEE signal.
LK) is set up to satisfy the command setup time and command hold time of the synchronous DRAM, respectively.

As described above, according to the present embodiment, for example, the average bias current of the input buffer circuit mounted on the synchronous DRAM can be reduced, so that the power consumption is low and the SSTL, CTT, An input buffer circuit corresponding to a small-amplitude interface such as HSTL can be realized.

As is apparent from FIG. 1B, even if the CKEE signal is at H level only during the period including the falling point of the clock signal (CLK), the input signal (Vi
n), the CKEE control signal generation circuit 20 may generate the CKEE signal which becomes H level only during the period including the falling point of the clock signal (CLK).

Further, in the case of a synchronous DRAM in which various command signals are fetched in synchronization with the falling edge of the clock signal (CLK), the CKEE control signal generation circuit 20 causes the falling edge of the clock signal (CLK). It is sufficient to generate the CKEE signal which becomes H level only during the period including the time point.

In FIG. 1, the logic circuit section 13
It is also possible to replace with a through latch circuit as shown in FIG.

In FIG. 2, reference numerals 16 and 18 denote inverters,
Reference numerals 15 and 17 denote clocked inverters. The clocked inverters (15 and 17) operate as normal inverters when an H-level voltage is applied to the terminal (CA).
When an L-level voltage is applied to the terminal (CA), the terminal (CA) enters a high impedance state.

Therefore, the output of the NOR gate 12 (V
When bi) is at the H level, the clocked inverter 1
5 is turned on, the clocked inverter 17 is turned off, and the input signal (IN) passes through each inverter and becomes an output signal (OUT). Further, the output of the NOR gate 12 (V
When bi) is at the L level, the clocked inverter 1
5 is turned off, the clocked inverter 17 is turned on, and the output signal (OUT) is latched by the inverter 16 and the clocked inverter 17.

According to the through latch circuit shown in FIG. 2, the output signal (OUT) can be changed only at the rising edge of the CKEE signal and not changed at other times.

FIG. 3 is a diagram showing a circuit configuration of an example of the CKEE control signal generation circuit 20 shown in FIG. 1 and a timing chart thereof.

The CKEE control signal generating circuit 20 shown in FIG.
Is a clock signal (CLK) as shown in FIG.
And a delay circuit (DLY) 32 to which an output signal from the inverter 31 is input;
The output signal from the inverter 31 and the delay circuit 32
And an output signal from the AND gate 33, and a delay circuit (DLY) 34 to which the output signal from the AND gate 33 is input.

Here, the period of the clock signal (CLK) is T (the high-level period is Ta and the low-level period is Tb),
Further, the delay times of the delay circuits (32, 34) are respectively represented by d
1, d2.

As shown in the timing chart of FIG. 2B, the inverter 31 outputs an inverted signal (ea) obtained by inverting the clock signal (CLK). The delay circuit 32
It outputs a delay signal (eb) obtained by delaying the inverted signal (ea) from the inverter 31 by (d1) time. AND gate 3
Reference numeral 3 outputs an output signal (ec) by performing an AND logic operation on the inverted signal (ea) and the delay signal (eb). Delay circuit 3
4 outputs the output signal (ec) from the AND gate 33 to (d
2) Output the CKEE signal with a time delay.

As can be seen from FIG. 2B, the CKEE signal is at the high level only during the period that crosses the rising edge of the clock signal (CLK), and the setup time and the hold time of the CKEE signal with respect to the clock signal (CLK) are maintained. The times are (Tb-d1-d2) and d2, respectively.

Therefore, by adjusting the delay times (d1, d2) of the delay circuits (32, 34), an optimum C
It is possible to obtain a KEE signal pulse.

By applying the CKEE control signal generation circuit 20 to the input buffer circuit of the present embodiment, a low power consumption type input buffer circuit compatible with a small amplitude interface can be realized. it can.

FIG. 4 is a diagram showing a circuit configuration of another example of the CKEE control signal generation circuit 20 shown in FIG.

The CKEE control signal generating circuit 20 shown in FIG.
In the CKEE control signal generation circuit 20 shown in FIG. 3, delay circuits (32a, 32b, 32b) having different delay times in accordance with the frequency of the clock signal (CLK).
c) and the delay circuits (34a, 34b, 34c) can be selected.

The CKEE control signal generating circuit 20 shown in FIG.
According to this, it is possible to realize an input buffer circuit corresponding to a low-power-consumption small-amplitude interface adapted to a wide range of clock frequencies.

In FIG. 4, the circuit configuration for making the delay time variable is not limited to the example shown in FIG. 4, and various circuit configurations may be adopted.

FIG. 5 is a diagram showing a circuit configuration of another example of the CKEE control signal generation circuit 20 shown in FIG. 1 and a timing chart thereof.

The CKEE control signal generation circuit 20 shown in FIG.
Is a clock signal (CLK) as shown in FIG.
, An inverter (42, 43) cascade-connected to the inverter 41, a NAND gate 44 to which a clock signal (CLK) and an output signal from the inverter 43 are input, and a NAND gate 44 And an output signal from the inverter 41 are input, an NAND gate 46 to which the output signal from the AND gate 45 and the output signal from the inverter 43 are input, and an output from the NAND gate 46 And an inverter 47 to which a signal is input.

Here, the cycle of the clock signal (CLK) is T (the high level period is Ta, the low level period is Tb),
The delay time of one stage of the inverter is d.

As shown in the timing chart of FIG. 7B, the inverters (41, 42, 43) connected in series
Is a clock signal (CLK) or each inverter (4
1, 42), the inverted signal (ea,
eb, ec). The NAND gate 44 takes NAND logic of the clock signal (CLK) and an inverted signal (ec) from the inverter 43 (a clock signal (CLK) delayed by a delay time (3d) for three stages of inverters) and outputs an output signal. (Ed) is output. AND gate 45
The output signal (ee) is output by taking AND logic of the output signal (ed) from the AND gate 44 and the inverted signal (ea) from the inverter 41. The NAND gate 46
The output signal (ef) is output by taking NAND logic of the output signal (ee) from the AND gate 45 and the inverted signal (ec) from the inverter 43. The inverter 47 has a NA
Inverting the output signal (ef) from the ND gate 46,
Outputs the KEE signal.

As can be seen from FIG. 9B, the CKEE signal is at the high level only during the period (Tb-3d) that crosses the rising edge of the clock signal (CLK), and the CKEE signal is the clock signal (CLK) of the CKEE signal. Setup time and hold time for (Tb-2d),
d.

Thus, by applying the CKEE control signal generation circuit 20 to the input buffer circuit of the present embodiment, it is possible to realize an input buffer circuit which is of low power consumption type and compatible with a small amplitude interface. it can.

FIG. 6 is a diagram showing a circuit configuration of another example of the CKEE control signal generation circuit 20 shown in FIG. 1 and a timing chart thereof.

The CKEE control signal generation circuit 20 shown in FIG.
Is a clock signal (CLK) as shown in FIG.
(DLY) 51 to which is input the delay circuit 51
And an EX-OR gate 52 to which the output signal from the controller and the clock signal (CLK) are input.
Delay circuit (DLY) 53 to which the output signal from 2 is input
And an inverter 54 to which an output signal from the delay circuit 53 is input.

Here, the period of the clock signal (CLK) is T (Ta during the high level period, Tb during the low level period),
The delay times of the delay circuits (51, 53) are d1,
d2.

As shown in the timing chart of FIG. 7B, the delay circuit 51 outputs the clock signal (CLK) to d1.
The delay signal (ea) is output with a time delay. EX-OR
The gate 52 outputs the delay signal (ea) and the clock signal (C
LK) and outputs an output signal (eb). The delay circuit 53 delays the output signal (eb) from the EX-OR gate 52 by a time d2 and outputs the delayed signal (e).
Output c). Inverter 54 inverts the output signal (ec) from delay circuit 53 and outputs a CKEE signal.

As can be seen from FIG. 7B, the CKEE signal is at the high level only during the period that straddles the rising edge and the falling edge of the clock signal (CLK), respectively, and the setup for the rising edge of the clock signal of the CKEE signal is performed. Time and hold time are (Tb-d1
−d2), d2, the setup time and the hold time for the falling edge of the clock signal are (Ta−d1−d)
2), d2.

The delay time d1 corresponds to the clock signal (C
LK) is set to be shorter than the high-level period (Ta) and the low-level period (Tb).
The high level period (Ta) and the low level period (Tb) of the clock signal (CLK) are set to be substantially equal, that is, set to have a duty ratio of 50%.

Therefore, by adjusting the delay times (d1, d2) of the delay circuits (51, 53), the optimum C
It is possible to obtain a KEE signal pulse. Thus, by applying the CKEE control signal generation circuit 20 to the input buffer circuit of the present embodiment, it is possible to realize an input buffer circuit that is of low power consumption and compatible with a small-amplitude interface.

FIG. 7 is a diagram showing a circuit configuration of another example of the CKEE control signal generation circuit 20 shown in FIG. 1 and a timing chart thereof.

The CKEE control signal generating circuit 20 shown in FIG.
Is an EX-OR gate 61 to which a clock signal (CLK) is inputted to one input terminal as shown in FIG.
And a D-type flip-flop circuit (D-OR) in which an output signal of the EX-OR gate 61 is input to a clock terminal (CP).
FF) 62 and a D-type flip-flop circuit (D-FF)
62 is input and the output signal is EX.
An inverter group 63 that outputs to the other input terminal of the -OR gate 61 and an inverter 64 to which an output signal of the EX-OR gate 61 is input.

Here, the cycle of the clock signal (CLK) is T (Ta during the high level period, Tb during the low level period),
The delay time of one stage of the inverter is d. The total delay time of the D-type flip-flop circuit 62 and the EX-OR gate 61 is represented by τ.

As shown in the timing chart of FIG. 9B, the EX-OR gate 61 outputs the clock signal (CL).
K) and a delayed signal (e) of the positive-phase output Q of the D-type flip-flop circuit 62 delayed by 4d by the inverter group 63.
The exclusive OR with a) is taken and an output signal (eb) is output. The D-type flip-flop circuit 62 has an EX-OR
Each time the output signal (eb) from the gate 61 is input,
Invert its output. The inverter 64 inverts the output signal (eb) from the EX-OR gate 61 and outputs the CKEE
Output a signal.

As can be seen from FIG. 7 (b), the CKEE signal is at the high level only during the period that crosses the rising edge and the falling edge of the clock signal (CLK), respectively. The setup time and hold time are Tb- (3
d + τ), d, the setup time and the hold time for the falling edge of the clock signal are Ta− (3d + τ), d
Becomes

The delay time (4d + τ) is set to be shorter than the high-level period (Ta) and the low-level period (Tb) of the clock signal (CLK). Generally, the delay time (4d + τ) is generally shorter than the clock signal (CLK). High-level period (T
a) and the low level period (Tb) are set to be substantially equal, that is, set to have a duty ratio of 50%.

Therefore, the delay time (d) of one stage of the inverter, the D-type flip-flop circuit 62 and the EX-
By adjusting the total delay time (τ) of the OR gate 61, an optimum CKEE signal pulse can be obtained. As a result, the CKEE control signal generation circuit 2
By applying 0 to the input buffer circuit according to the present embodiment, it is possible to realize an input buffer circuit that is low power consumption and compatible with a small amplitude interface.

FIG. 8 is a diagram showing a circuit configuration of another example of the CKEE control signal generation circuit 20 shown in FIG.

The CKEE control signal generating circuit 20 shown in FIG.
Is connected to an external clock signal (Ext.CLK) in a multi-stage series.
Integrated voltage controlled oscillator (MST-VCO;Multi
SstageTapplied-VoltageContr
olledOoutput from the SILATOR 104
Phase difference with the internal clock signal (Int.CLK)
Output phase difference detection circuit (Phase Detector)
101 and the output voltage of the phase difference detection circuit 101
Charge pump circuit 102 and the charge pump
Low-pass that transmits only the low-frequency region of the output of the loop circuit 102
The filter circuit 103 and the low-pass filter circuit 10
3 according to the output voltage of the internal clock signal (Int.
K) the multi-stage series-coupled voltage whose oscillation frequency is controlled
It comprises a control oscillation circuit 104.

[0067] The CKEE control signal generating circuit 20 is generally well-known PLL (P hase L ocke
d L loop) circuit configuration and an external clock signal (E
xt. CLK) (internal clock signal (Int.CLK)) (a clock signal for synchronizing the semiconductor integrated circuit) without skew.

FIG. 9 is a diagram showing a circuit configuration of an example of the multi-stage series-coupled voltage controlled oscillation circuit 104 shown in FIG. 8 and a timing chart thereof.

The multi-stage series-coupled voltage-controlled oscillation circuit 104 shown in FIG.
And a T-ring oscillator circuit 120. The voltage-current conversion circuit 110 has PMOSFETs (M30, M31) that are current-mirror-coupled, and NMOSFETs (M32, M33) for an input stage and a load.

The MST ring oscillator circuit 120
Is a PMOSF controlled by the voltage-current conversion circuit 110
ET (M40-M48) and PMOSFET (M50-
M58), NMOSFETs (M60 to M68), and NMOSFET controlled by the voltage-current conversion circuit 110
(M70 to M78) are a set of inverters, and the inverters are connected in a loop of a plurality of odd-numbered stages (9 stages in the figure).

Here, the MST ring oscillator circuit 12
Since the gates of the load PMOSFETs (M40 to M48) and the NMOSFETs (M70 to M78) within 0 are connected to the voltage-current conversion circuit 110, the driving current of the MST ring oscillator circuit 120 is changed to the voltage-current conversion circuit. As a result, the oscillation frequency of the MST ring oscillator circuit 120 is also controlled.

Note that the output signals (φ0 to φ8) are
The output of each stage of the ring oscillator circuit 120 is extracted via an inverter (130 to 138), and the output signal (φ0) is an internal clock signal (Int.
CLK), and AND gate 141
Calculates the logical product of the output signal (φ7) and the inverted signal of the delay signal obtained by delaying the output signal (φ0) by the delay circuit (DLY) 140, and the output signal from the AND gate 141 is the CKEE signal. Becomes

The multi-stage series-coupled voltage controlled oscillation circuit 104 shown in FIG.
K) and the input voltage (Vi) to the voltage-current conversion circuit 110 according to the phase difference between the internal clock signal (Int.CLK) and the internal clock signal (Int.CLK).
na) is applied. Thereby, the drive current of MST ring oscillator circuit 120 is adjusted, and the frequency and phase of internal clock signal (Int.CLK) match external clock signal (Ext.CLK).

As shown in the timing chart of FIG. 9B, the cycle of the external clock signal (Ext.
Then, the phases of the output signals (φ0 to φ8) of each stage of the MST ring oscillator circuit 120 are respectively set to the period ((T
/ 2) / 9). That is, the output signals of each stage of the MST ring oscillator circuit 120 (φ0 to φ
8) has a cycle whose external clock signal (Ext.
K) and each phase has a period ((T / 2))
/ 9) is repeated.

Since the CKEE signal is generated by taking the logical product of the output signal (φ7) and the inverted signal of the delay signal obtained by delaying the output signal (φ0), the CKEE signal is generated from the external clock signal (Ext.CLK). (Or a signal that is at a high level only during a period that straddles the rising edge of the internal clock signal (Int.CLK)).

When the delay time of the delay circuit 140 is d2, the external clock signal (Ext. C) of the CKEE signal is output.
The setup time and the hold time for (LK) are (T / 9−d2) and d2, respectively.

Therefore, if the present CKEE control signal generation circuit 20 is applied to the input buffer circuit shown in FIG. 1, it is possible to generate a CKEE signal having no skew with respect to an external clock signal, and to achieve a higher speed synchronous DRAM.
Thus, it is possible to realize an input buffer circuit that is low power consumption type and supports a small amplitude interface.

FIG. 10 is a diagram showing a circuit configuration of another example of the CKEE control signal generation circuit 20 shown in FIG. 1 and a timing chart.

[0079] CKEE control signal generating circuit 20 shown in the diagram (a) is, SMD (S ynchronous M irr
and or D elay) circuit 200, and a one-shot pulse generating circuit 207.

The SMD circuit 200 includes a clock input buffer circuit 201 to which an external clock signal (Ext. CLK) is input, a delay monitor circuit 202 to which an output signal (e1) of the clock input buffer circuit 201 is input, and a delay monitor circuit. A traveling direction delay circuit array 203 to which an output signal (e2) of the circuit 202 is input;
A reverse delay circuit train 205 to which a signal is transmitted in the reverse direction;
The output of the traveling direction delay circuit row 203 and the reverse delay circuit row 20
5 includes a mirror image control circuit 204 for connecting the inputs as if the signal delay is a mirror, and a clock driver circuit 206 for driving the output signal (e5) of the reverse delay circuit 205.

Here, the delay monitor circuit 202 calculates the total delay time (λ 1) of the delay time λ 1 of the clock input buffer circuit 201 and the delay time λ 2 of the clock driver circuit 206.
+ Λ2). The one-shot pulse generation circuit 207 generates a one-shot pulse based on the output signal of the backward delay circuit 205.

Next, an outline of the operation of the SMD circuit 200 will be described with reference to a timing chart shown in FIG.

Now, as the output signal (e1) of the clock input buffer circuit 201, the nth, n + 1th, n + 2
Consider the th clock pulse.

First, the n-th clock passes through the delay monitor circuit 202, and proceeds in the traveling direction delay circuit array 203 until the (n + 1) -th clock enters the mirror image control circuit 204. When the (n + 1) th clock is input to the mirror image control circuit 204, the nth clock
3 to the backward delay circuit 205 as if the (n + 2) th clock is a mirror.

The n-th clock is supplied to the reverse delay circuit 205
Returning to the inside, the n-th clock is
Reverse delay circuit 2 for a time equal to the time of passing through circuit 03
Pass through 05. The time when the n-th clock has passed through the delay monitor circuit 202 and the traveling direction delay circuit array 203 is determined by the delay monitor circuit 20 in the clock cycle (tCK).
2 is (λ1 + λ2), the delay time of the forward delay circuit 203 and the backward delay circuit 205 is (tCK).
− (Λ1 + λ2)).

Therefore, the output signal (e 5) of the n-th clock from the backward delay circuit 205 passes through the clock input buffer circuit 201, the delay monitor circuit 202, the forward direction delay circuit column 203 and the backward delay circuit 205. The clock driver circuit 206 is delayed from the external n-th clock by the time represented by the following equation (1),
At the delay time λ2.

[0087]

Λ 1 + (λ 1 + λ 2) + (tCK− (λ 1 + λ 2)) × 2 = 2 tCK−λ 2 (1) In this manner, n The internal clock (Int.C) which is the output signal of the clock driver circuit 206 of the second clock
LK) eliminates the skew with the external (n + 2) th clock.

Here, when the output signal (e5) of the backward delay circuit 205 is input to the one-shot pulse generation circuit 207 as shown in FIG.
t. CLK) can be generated at a high level only during a period that crosses the rising edge of CLK).

The one-shot pulse generation circuit 2
Assuming that the pulse width of the pulse generated at step 07 is λ, the setup time and the hold time of the CKEE signal with respect to the external clock signal (Ext.CLK) are λ, respectively.
2, (λ−λ2).

FIG. 11 shows the traveling direction delay circuit row 203, mirror image control circuit 204, and reverse delay circuit row 2 shown in FIG.
FIG. 5 is a diagram showing a circuit configuration of one example of a unit circuit 05.

In the figure, reference numeral 213 denotes one unit circuit of the traveling direction delay circuit row 203, and 214 denotes a mirror image control circuit 20.
Reference numeral 4 denotes one unit circuit, and 215 denotes one unit circuit of the reverse delay circuit array 205.

One unit circuit 213 of the traveling direction delay circuit array 203 includes a NAND circuit (FNm) and an inverter (FI).
m), the output of the NAND circuit (FNm) is at the H level and the output of the inverter (FIm) is at the L level during standby. One unit circuit 214 of the mirror image control circuit 204 is formed of a NAND circuit (MNm), and the output of the NAND circuit (MNm) is at the H level during standby. One unit circuit 213 of the traveling direction delay circuit row 203 includes a NAND circuit (BNm) and an inverter (BI
m), the output of the NAND circuit (BNm) is at the L level and the output of the inverter (BIm) is at the H level during standby.

Now, the high pulse of the n-th clock is (F
At the same time as entering the unit circuit 213 from the (Im-1) terminal, the high pulse of the (n + 1) th clock is (e1)
When entering the unit circuit 214 from the terminal, the output of the NAND circuit (MNm) becomes L level.

Therefore, the output of the inverter (BIm) becomes L level, and the L level output of the inverter (BIm) is transferred to the (BNm-1) terminal as a low pulse. Further, the output of the L-level NAND circuit (MNm) is also input to the NAND circuit (FNm + 2),
Since the output of the circuit (FNm + 2) maintains the H level,
Since the high pulse in the unit circuit 213 of the traveling direction delay circuit row 203 is erased, the transfer is performed as if it were a mirror.

FIG. 12 shows a more specific circuit configuration of the traveling direction delay circuit array 203, the mirror image control circuit 204, and the backward delay circuit array 205 composed of six units.

The SMD circuit 200 is connected to an internal clock signal (Int.
CLK) is generally stopped during a standby period to reduce power consumption and activated by an active command.

Therefore, the CKEE control signal generation circuit 20
May be configured separately from the SMD circuit for generating the internal clock signal, and may be constantly operated. However, in this case, the SMD circuit 200 used in the CKEE control signal generation circuit 20
The delay time λ2 corresponding to the setup time required for the KEE signal is set, and the delay time of one unit of the traveling direction delay circuit array 203, the mirror image control circuit 204, and the backward delay circuit array 205 is increased, so that the traveling direction delay is increased. Circuit row 20
3. The number of units of the mirror image control circuit 204 and the backward delay circuit row 205 can be reduced, and the power consumption of the SMD circuit 200 can be reduced.

Therefore, if the present CKEE control signal generation circuit 20 is applied to the input buffer circuit shown in FIG. 1, it is possible to generate a CKEE signal having no skew with respect to an external clock signal, and to achieve a faster synchronous DRAM.
, A low power consumption type input buffer circuit compatible with a small-amplitude interface can be realized.

In the input buffer circuit according to the present embodiment, CK is applied both during the period that crosses the rising edge and the period that crosses the falling edge of the clock signal (CLK).
The EE signal may be at the H level. FIG. 13 shows a timing chart in that case.

According to this example, the input buffer circuit operates during both the period that crosses the rising edge and the period that crosses the falling edge of the clock signal (CLK). Therefore, a synchronous DRAM (so-called DDR (Double Data Rate) synchronous DRA) synchronized at both the rising edge and the falling edge of the clock signal.
M) and the like, and an input buffer circuit that is low power consumption type and compatible with a small-amplitude interface can be realized.

FIG. 14 is a diagram showing a circuit configuration of another example of the input buffer circuit of the present embodiment and a timing chart thereof.

The input buffer circuit shown in the figure is a PMOS transistor of the logic circuit unit 13 in the input buffer circuit shown in FIG.
FETs (M8, M9) were deleted and replaced with PMOSFE
T (M10) is added.

Here, when the output signal of the NOR gate 12 to which the inverted signal of the CKEE signal is input is at L level, the PMOSFET (M10) is turned on, and when it is at H level, the PMOSFET (M10) is turned off.

Therefore, when the power down signal (PWDN) signal of the synchronous DRAM is at the L level,
When the KEE signal is at the L level (that is, the output signal of the inverter 11 is at the H level), the output of the input buffer circuit (the output of the CMOS inverter composed of the PMOSFET (M6) and the NMOSFET (M7)) (OUT)
Are always fixed at the H level. Then, the CKEE signal is at the H level (that is, the output signal of the inverter 11 is at the L level) and the input signal (Vin) of the differential amplifier circuit 10 is provided.
Is high, the output of the input buffer circuit (O
UT) becomes H level.

Therefore, the PMOSF of the differential amplifier circuit 10
Since the ET (M1, M2) does not contribute to the rise time of the output of the differential amplifier circuit 10, the PMOSFET (M
1, M2) can be designed to be small. Thus, it is possible to realize an input buffer circuit having a small circuit area and corresponding to a low power consumption type small amplitude interface.

FIG. 15 is a diagram showing another circuit configuration of the input buffer circuit of the present embodiment and a timing chart thereof.

The input buffer circuit shown in FIG.
The input buffer circuit shown in FIG. 1 is different from the input buffer circuit shown in FIG.
Are replaced by an OR gate 14.

The differential amplifying circuit 10 shown in the figure has NMOSFETs (M11, M
12), PMOSFET (M13, M14), PM
OSFET (M15). Therefore, even when the reference voltage (Vref) is low, the differential amplifier circuit 10 operates normally. This makes it possible to realize a low power consumption type input buffer circuit compatible with a small-amplitude interface having a small reference voltage (Vref) such as GTL.

FIG. 16 is a block diagram showing a schematic configuration of a synchronous DRAM to which the present invention is applied.

The synchronous DRAM shown in FIG.
Is formed on one semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique, although not particularly limited.

The synchronous DRAM shown in the figure includes a memory array 301A forming the memory bank 1 and a memory array 301B forming the memory bank 2.
Each of the memory arrays (301A, 301B) includes dynamic memory cells arranged in a matrix. Select terminals of memory cells arranged in the same row are connected to word lines of each row, and data input / output terminals of memory cells arranged in the same column are connected to complementary data lines of each column.
The complementary data line is connected to a row address decoder (302A, 30A).
One of them is driven to the selected level according to the decoding result of the row address according to 2B).

Sense amplifier and column selection circuit (304)
A, 304B) detects and amplifies a small potential difference generated in each complementary data line by reading data from the memory cell. Further, the sense amplifier and the column selection circuit of the column selection circuit (304A, 304B) select the complementary data line in particular and connect it to the complementary common data line.
This column selection circuit includes a column decoder (303A, 303B)
Is selected as a result of decoding the column address.

The complementary common data line is connected to the input buffer 3
09 and the input terminal of the output buffer 308. An input terminal of the input buffer 309 and an output terminal of the output buffer 308 are connected to a data output terminal (I / O).
Connected to.

The row address or the column address input from the address input terminal (Adin) is taken into the row address buffer 305 and the column address buffer 306 in a multiplex format and held. The output of the column address buffer 306 is supplied to the column address counter 307 as preset data of the column address counter 307.

A column address counter 307 supplies the preset data or data obtained by sequentially incrementing the preset data to a column address decoder (303A, 303B) in accordance with an operation mode designated by a command or the like. I do.

The controller 310 receives an address signal, a clock signal (CLK), a chip select signal (/ CS) (symbol //) input from an address input terminal (Adin).
Means that the signal to which this is attached is a row enable signal. ), Row address strobe signal (/ R
AS), an external control signal such as a column address trobe signal (/ CAS) is input, and the operation mode of the synchronous DRAM or the operation of each circuit block is controlled based on the level change and timing of these signals. Is formed.

The present invention can be applied to an input buffer circuit corresponding to a small-amplitude interface of a synchronous type memory operating in synchronization with a clock signal such as a synchronous SRAM other than the synchronous DRAM.

The circuit configuration of the differential amplifier circuit or the CKEE control signal generation circuit in the input buffer circuit may be other than that described in each embodiment.

Although the present invention has been specifically described based on the embodiments of the present invention, the present invention is not limited to the embodiments of the present invention, and various modifications may be made without departing from the gist of the present invention. It goes without saying that you get it.

[0120]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

(1) According to the present invention, the bias current of the differential amplifier circuit in the input buffer circuit is caused to flow only for a certain period including the rising point (or the falling point) of the clock signal. The average bias current of the dynamic amplifier circuit can be reduced. Thus, it is possible to provide a semiconductor integrated circuit device that is low power consumption type and compatible with a small amplitude interface.

[Brief description of the drawings]

FIG. 1 is a diagram showing a circuit configuration of an example of an input buffer circuit in a semiconductor integrated circuit device according to an embodiment of the present invention, and a timing chart thereof.

FIG. 2 is a diagram illustrating a through latch circuit that can be replaced with the logic circuit unit illustrated in FIG. 1;

FIG. 3 is a diagram showing a circuit configuration of an example of a CKEE control signal generation circuit shown in FIG. 1 and a timing chart thereof.

FIG. 4 is a diagram showing a circuit configuration of another example of the CKEE control signal generation circuit shown in FIG. 1;

5 is a diagram showing a circuit configuration of another example of the CKEE control signal generation circuit shown in FIG. 1 and a timing chart thereof.

FIG. 6 is a diagram showing a circuit configuration of another example of the CKEE control signal generation circuit shown in FIG. 1 and a timing chart thereof.

7 is a diagram showing a circuit configuration of another example of the CKEE control signal generation circuit shown in FIG. 1 and a timing chart thereof.

8 is a diagram showing a circuit configuration of another example of the CKEE control signal generation circuit shown in FIG.

9 is a diagram showing a circuit configuration of an example of a multi-stage series-coupled voltage controlled oscillator circuit shown in FIG. 8 and a timing chart thereof.

FIG. 10 is a diagram showing a circuit configuration and a timing chart of another example of the CKEE control signal generation circuit shown in FIG. 1;

11 is a diagram illustrating a circuit configuration of one unit circuit as an example of the traveling direction delay circuit array, the mirror image control circuit, and the backward delay circuit array illustrated in FIG. 10;

FIG. 12 is a diagram showing a more specific circuit configuration of a traveling direction delay circuit array, a mirror image control circuit, and a backward delay circuit array composed of six units.

FIG. 13 shows the relationship between CK during a period that crosses a rising edge and a period that crosses a falling edge of a clock signal (CLK).
FIG. 7 is a diagram showing a timing chart when an EE signal is set to an H level.

FIG. 14 is a diagram showing a circuit configuration of another example of the input buffer circuit of the present embodiment and a timing chart thereof.

FIG. 15 is a diagram showing another circuit configuration of the input buffer circuit of the present embodiment and a timing chart thereof.

FIG. 16 is a block diagram showing a schematic configuration of a synchronous DRAM to which the present invention is applied.

FIG. 17 is a diagram showing a circuit configuration of an input buffer circuit corresponding to a small-amplitude interface in a conventional synchronous DRAM and a timing chart thereof.

[Explanation of symbols]

10 ... Differential amplifier circuit, 11, 16, 18, 21, 31,
41, 42, 43, 47, 54, 64, 130 to 13
8, FIm, BIm: inverter, 12: NOR gate, 13: logic circuit unit, 14: OR gate, 15, 17
... Clocked inverter, 20 ... CKEE control signal generation circuit, 32, 32a, 32b, 32c, 34, 34a,
34b, 34c, 51, 53, 140 ... delay circuit (DL
Y), 33, 45, 141... AND gate, 44, 4
6, FNm, MNm, BNm ... NAND gate, 52,
61 EX-OR gate, 62 D-type flip-flop circuit (D-FF), 63 inverter group, 101 phase difference detection circuit, 102 charge pump circuit, 103 low-pass filter circuit, 104 multi-stage series connection type Voltage controlled oscillation circuit (MST-VCO), 110: voltage-current conversion circuit, 120: MST ring oscillator circuit, 200:
Synchronous delay circuit (SMD), 201: clock input buffer circuit, 202: delay monitor circuit (DMC), 203
... A traveling direction delay circuit sequence (FDA), 204 ... a mirror image control circuit (MCC), 205 ... a reverse delay circuit sequence (BDA), 2
06: clock driver circuit, 207: one-shot pulse generation circuit (OSP), 213: one unit circuit of the traveling direction delay circuit row 203, 214: mirror image control circuit 204
1 unit circuit, 215... 1 of the backward delay circuit train 205
Unit circuits, 301A, 301B ... memory array, 3
02A, 302B... Row address decoders, 303A, 3
03B: column decoder; 304A, 304B: sense amplifier and column selection circuit; 305: column address buffer;
06: row address buffer, 307: column address counter, 308: output buffer, 309: input buffer, 3
10: Controller, Mn: P-channel MOSFET
Or N-channel MOSFET.

Claims (9)

[Claims] 1. A semiconductor integrated circuit device that operates in synchronization with a clock signal, the semiconductor integrated circuit device including an input buffer circuit having a differential amplifier circuit that compares an input signal voltage with a reference voltage. A control signal generating circuit for generating a control signal for turning on an active element serving as a bias current source of the differential amplifier circuit for a certain period including a rising time (or a falling time) of the clock signal based on the signal. A semiconductor integrated circuit device comprising: 2. The semiconductor integrated circuit according to claim 1, wherein a certain period including a rising point (or a falling point) of the clock signal is a period equal to or less than a half cycle of the clock signal. apparatus. 3. An output voltage holding means for holding a potential at an output terminal of the input buffer circuit at a predetermined voltage level while an active element serving as a bias current source of the differential amplifier circuit is off. 3. The semiconductor integrated circuit device according to claim 1, wherein: 4. The control signal generating circuit according to claim 1, wherein the control signal generating circuit performs a predetermined logic operation between the clock signal and the delayed clock signal from the delay circuit, and controls the control signal. 4. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device comprises a logic circuit that outputs a signal. 5. A PLL circuit comprising a multi-stage series-coupled voltage-controlled oscillator for generating an internal clock signal synchronized with an external clock signal, and a multi-stage series-coupled voltage-controlled oscillator for the PLL circuit. 4. The semiconductor according to claim 1, comprising a logic circuit that outputs a control signal by taking a predetermined logic between output signals of an output stage. Integrated circuit device. 6. The semiconductor integrated circuit device according to claim 5, wherein the internal clock signal generated by the PLL circuit is a clock signal for synchronizing the semiconductor integrated circuit device. 7. The control signal generating circuit includes: an external clock input buffer circuit to which an external clock signal is input, a delay monitor circuit for delaying an output signal from the external clock input buffer circuit for a predetermined time, and the delay monitor circuit A forward delay circuit array to which an output signal of the forward delay circuit is input, a backward delay circuit train to which a signal is transmitted in a direction opposite to the forward delay circuit train, an output signal of the forward delay circuit train, and the backward delay circuit train And a one-shot pulse generating circuit for outputting a control signal based on an output signal of the reverse delay circuit. The semiconductor integrated circuit device according to claim 1. 8. The apparatus according to claim 7, further comprising a clock driver circuit for driving an output of said backward delay circuit, wherein said clock driver circuit outputs a clock signal for synchronizing a semiconductor integrated circuit device. Semiconductor integrated circuit device. 9. The semiconductor integrated circuit device according to claim 1, wherein said semiconductor integrated circuit device is a synchronous dynamic random access memory.