JPH10322305A - Demodulator for quadrature frequency division multiplex system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten the pull-in time of a carrier frequency by demodulating an in-phase signal and a quadrature signal from a selected quadrature modulation wave, converting a digital signal, multiplying a delayed signal by an original signal, adding the output of a multiplier by prescribed time, controlling a gain, generating the timing of a valid symbol and executing discrete Fourier transformation. SOLUTION: A tuner 10 frequency-converts a desired frequency band into an intermediate frequency band. The frequency-converted signal is orthogonally demodulated by a quadrature demodulator 11 and I and Q signals are reproduced. A ground interval removal circuit 14 takes out only the valid symbol part of the digitized signals of the I and Q signals and it is transferred to an FFT processing part 15. A QAM demodulation circuit 17 demodulates data of the respective carriers and an error correction circuit 18 corrects errors and outputs the signal as demodulation data. The guard interval removal circuit 14 separates only the valid symbol with a synchronizing signal 6 from a synchronism processing circuit 22 as a reference and transfers it to the FET processing part 15.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a demodulator in a communication system using an orthogonal frequency division multiplexing system, and more particularly to a demodulator in the communication system.

[0002]

2. Description of the Related Art Digital terrestrial broadcasting has been actively researched and developed, but the amount of information of digitized images has been greatly reduced due to the advance of image compression technology based on MPEG2, and transmission by wireless communication is possible. Advanced to the level.

Generally, when transmitting such compressed data, an information transmission rate of about 5 to 20 Mbps is usually required. If an error correction system for correcting data errors or a coded modulation system capable of improving the durability against errors is used for these data, the redundancy is further increased and a higher transmission rate is required.

In order to transmit such information within a limited band, it is necessary to develop a more efficient transmission system. At present, as a solution to this, it has been proposed to transmit information to be transmitted in multi-valued digital form. In particular, in order to realize terrestrial digital broadcasting in the future, the 8VSB system for transmitting eight levels using a 6 MHz band is being studied in the United States.

In the 8VSB system, 3-bit information can be transmitted in one symbol, and has a symbol rate of 10.76 M baud in a 6 MHz band. Although this system has high band use efficiency, it has an aspect that it is difficult to adapt to SFN (single frequency network) and mobile reception.
On the other hand, orthogonal frequency division multiplexing is being studied in Japan and Europe. This system is a system for transmitting information by simultaneously using a plurality of carriers, and has a feature that it is strong in multipath and is adaptable to SFN (single frequency network) and mobile reception.

In a limited radio wave environment such as terrestrial broadcasting, it is becoming important to use radio waves, which is one of effective resources, efficiently. It is being developed as a digital transmission system in the digital broadcasting era. The orthogonal frequency division multiplexing method is a method of transmitting information by simultaneously using a plurality of orthogonal carrier waves, and the number of carrier waves used at this time is about 1000 to 8000.
About a book.

[0007] Each carrier is modulated by multi-level QAM or the like, so that the band is used with high efficiency. Conventionally, this technology was developed as a technology used for digital audio stereo broadcasting in Europe, and it has been known that it can be realized using fast Fourier transform (FFT) as a means for modulating a large number of carriers at the same time. Is being done.

For example, regarding this technology, Michel
Alard, Rpselyne Lassall
e "Principle of modulation
and channel coding for d
digital broadcastcasting form
object receivers "EBU REVIE
W-TECHNICAL 1987, pp 168-19
0 is described in detail. The basic principle of OFDM is as follows. If the carrier frequency and _{{f k}, f k =} f 0 + k / T s k = 0~N-1 basic signal [psi _j, when a _{k (t), Ψ j,} k (t) = g k ( t−jT _s ) k = 0 to N−1, j
= −∞ to + ∞ g _k = exp (2iπf _k t) 0 ≦ t ≦ T _s g _k = 0 The frequency spectra of the other signal g _k (t) overlap each other. Ψ _j , _k (t) satisfy the orthogonality condition with each other.

[0009] A complex sequence of data to be transmitted is represented by {C _j , _k }
Then, the OFDM transmission signal X (t) can be described as follows.

[0010]

(Equation 1)

The received signal is demodulated by the following equation.

[0012]

(Equation 2)

When the above signal is transmitted through a transmission line, the orthogonality is damaged and disturbed by distortion and multipath caused by the transmission line. Therefore, intersymbol interference occurs in a demodulated signal of a received signal. Which results in increased errors.
As a solution to this problem, a method has been proposed in which a guard interval for absorbing intersymbol interference is provided before each signal Ψ _j , _k (t) at the expense of a part of transmission energy.

At this time, the symbol period of the transmission signal is described by the following equation.

T's = Ts + Δ Here, Ts is an effective symbol period, Δ is a guard interval period, and if an effective signal is Ψ _j , _k (t), Ψ _j , _k (t) = g _k (t −jT ′s) At this time, the transmission signal is Ψ ′ _j , _k (t) = g ′ _k (t−jT ′s) g ′ _k = exp (2iπf _k t) −Δ ≦ t <Ts g ′ _k = 0 At this time, the transmission signal X (t) of OFDM can be described as follows.

[0016]

(Equation 3)

The received signal is demodulated by the following equation.

[0018]

(Equation 4)

In the guard interval, by adding an invalid symbol as a buffer data portion before an effective symbol to be transmitted originally, it is possible to prevent the occurrence of inter-channel interference or inter-symbol interference, and to achieve high quality in digital transmission. Information can be sent. At this time, the invalid symbol to be added uses a part of the valid symbol and corresponds to a period of one tenth to one-seventh of the whole.

The signal waveform to be transmitted thus generated has a form like random noise, and the delimitation between symbols is not known. If the positions of the symbols are not accurately known, intersymbol interference with adjacent symbols will occur, and the demodulation signal will be degraded. Therefore, conventionally, a null symbol signal is used for symbol synchronization at the expense of some symbols. FIG. 10 is a diagram showing a frame configuration of a conventional transmission signal. Each symbol guard interval 15
1 and the effective symbol 152 are combined, and a plurality of symbols are collected into one frame, and a null symbol 150 is inserted at the beginning of the frame.

This method has a disadvantage that the amount of information that can be transmitted is reduced, and efficient information transmission cannot be performed. As means for solving this problem, there has been proposed a method of calculating a correlation coefficient of a part of the guard period and the effective symbol period and detecting symbol synchronization (Japanese Patent Laid-Open No. 7-14309).
7: OFDM synchronous demodulation circuit).

Further, since the signal waveform transmitted by the orthogonal frequency division multiplex system is multicarrier transmission, a large number of carriers (50 MHz) can be set within a limited band (6 MHz to 9 MHz).
(About 0 to 8000 lines), the frequency interval of each carrier becomes very narrow, about 1 KHz to 10 KHz.

Therefore, if there is a difference between the frequency on the transmitting side and the frequency on the receiving side, the quality of the demodulated signal is greatly deteriorated. For the above reasons, in the orthogonal frequency division multiplexing method, it is necessary to accurately reproduce the carrier frequency on the receiver side.
With regard to the conventional carrier frequency reproduction, a reference signal is assigned to a predetermined position of each symbol on the transmission side, and a prescribed signal is inserted, and a method of reproducing the carrier frequency based on this is adopted on the reception side. I was

When this method is used, if the reference signal is disturbed, the carrier cannot be reproduced, and the demodulated received signal is greatly deteriorated. Further, the autocorrelation coefficient of the I signal and IQ
The correlation coefficient of the signal is calculated and the frequency error is calculated.
A system for reproducing a carrier based on this error signal has been proposed (Japanese Patent Laid-Open No. 7-143097: OFDM synchronous demodulation circuit).

[0025]

Generally, a signal waveform transmitted by the orthogonal frequency division multiplexing method is a waveform like random noise, and it is difficult to determine a break between symbols. If the position of the symbol is not accurately determined in the receiver, intersymbol interference with adjacent symbols occurs, and the demodulated signal deteriorates.

Therefore, conventionally, a null symbol signal is inserted for symbol synchronization at the expense of some symbols. However, this method has a disadvantage that the amount of information that can be transmitted is reduced. As means for solving this problem, there has been proposed a method of calculating a correlation coefficient of a part of the guard period and the effective symbol period and detecting symbol synchronization.
In this proposal, when a correlation coefficient is calculated, a large correlation is obtained periodically, and the timing of this peak is determined as a symbol break.

The flywheel timing circuit can remove noise and pseudo correlation peaks based on this timing. However, in this method, if there is a frequency offset, a peak may not be obtained in the output of the correlation coefficient. In this case, symbol synchronization is lost, intersymbol interference with adjacent symbols occurs, and the characteristics of the demodulated signal deteriorate.

In addition, since there is no peak in the correlation coefficient during the initial symbol synchronization pull-in, there is a problem that the pull-in time is required. The conventionally proposed method of reproducing a carrier frequency has a disadvantage that the carrier frequency pull-in time becomes long.

[0029]

[Means for Solving the Problems]

(1) In a digital communication system for transmitting data by simultaneously using a plurality of orthogonal carrier waves, in a system in which one symbol period is transmitted using a signal format composed of an effective symbol period and a guard period, It is provided with a tuning means for selecting a desired frequency and a quadrature demodulation means for demodulating an in-phase signal and a quadrature signal from the tuned quadrature modulated wave, and converts the obtained digital signal into data by discrete Fourier transform. An effective symbol delay unit that includes a Fourier transform unit and delays the in-phase signal and the quadrature signal by the effective symbol period time, and a first multiplication that multiplies each of the signal delayed by the effective symbol delay unit and the original signal. A variable sample delay adder for adding an output of the multiplier by a time corresponding to a guard period, and the variable sample delay A second multiplier for multiplying an output of the multiplier by a signal from a coefficient generator, a variable symbol delay adder for adding the output of the multiplier for a predetermined time and controlling a gain, and A waveform shaping circuit that generates the timing of an effective symbol from the signal of the detector,
An orthogonal frequency division multiplexing demodulator performing the discrete Fourier transform based on an output signal of the waveform shaping circuit.

(2) The variable sample delay addition means of (1) includes a sample delay device for delaying in units of samples, a plurality of the sample delay devices connected in cascade, and an adder for adding their outputs. Equipped with an enable control circuit for controlling the operation of the sample delay unit with an external guard signal, enabling the addition period to be changed according to the guard interval period, adaptively generating a symbol synchronization signal, and based on this signal. An orthogonal frequency division multiplexing demodulator performing the discrete Fourier transform according to claim 1.

(3) The variable symbol delay adding means of (1) includes a variable symbol delayer for delaying by a period obtained by adding an effective symbol period and a guard period, and includes an absolute value circuit for obtaining an absolute value of an input signal. A plurality of symbol delay units connected in cascade, an adder for adding the outputs of the symbol delay units, an addition period control unit that can change an addition period in accordance with the position determination state and the operation start state of the effective symbol; A quadrature frequency, comprising: a gain control circuit for controlling the gain of the output by an external control signal; and a third multiplier for performing multiplication, wherein the discrete Fourier transform is performed based on an output signal of the third multiplier. Demodulator of division multiplex system.

(4) An effective symbol delay unit for delaying the in-phase signal and the quadrature signal described in (1) by an effective symbol period, and a first multiplier for multiplying the quadrature signal and the in-phase signal by a respective one. A variable sample delay adder for performing sample delay addition of a result multiplied by the first multiplier, wherein a value of a signal obtained from the variable sample delay adder is multiplied by a signal from a coefficient generator. 2. A hold circuit comprising: a second multiplier; a second multiplier according to claim 1; and an arithmetic processing unit for performing an arithmetic operation on an output signal of the second multiplier, and a hold circuit for holding an output of the arithmetic processing unit at a predetermined timing. A variable symbol delay adder for adding the output of the hold circuit for a predetermined period, and a frequency oscillator for quadrature demodulation using the output of the variable symbol delay adder as a frequency error signal. Demodulator of the orthogonal frequency division multiplexing system, characterized in that Gosuru.

(5) In the variable symbol delay adder for adding the output of the hold circuit in (4) for a predetermined period, the variable symbol delay adder includes a symbol delayer for delaying by a period obtained by adding an effective symbol period and a guard period. A plurality of cascade connections, an adder for adding the respective outputs, an enable control circuit for controlling an operation state of the symbol delay unit in accordance with a control signal from the outside, and controlling a gain based on the control signal. An orthogonal frequency division multiplexing demodulator, comprising: a gain control circuit; and a multiplier for multiplying the adder output based on a signal from the gain control circuit.

(6) A reference signal separation circuit for separating the reference signal inserted at the time of transmission from the output of the Fourier transform unit in (1) is provided, and a reference signal generator for generating the same reference signal as the transmitting side is provided. A correlator for correlating a signal separated by the reference signal separation circuit with a reference signal generated by the reference signal generator; a variable symbol delay adder for adding an output signal of the correlator; An orthogonal frequency division multiplexing demodulator characterized by controlling an orthogonal demodulation frequency oscillator by an output of a symbol delay adder.

(7) An adder for adding the frequency error signal of the output of the variable symbol delay adder in (4) and the frequency error signal of the output of the variable symbol delay adder in (6) is provided. A quadrature frequency division multiplexing demodulator characterized in that an addition amount and a gain of a delay adder can be controlled separately, and a frequency oscillator for quadrature demodulation is controlled using an output of the adder as a frequency error signal.

When the processing method of the present invention is used, symbol synchronization can be detected stably even if a frequency offset exists, and good signal demodulation can be performed. It is also possible to execute high-speed synchronization of the initial symbol synchronization. In the reproduction of the carrier frequency, the frequency error signal calculated by calculating the autocorrelation of the I signal and the Q signal and the correlation coefficient of the IQ signal and the frequency error signal calculated from the reference signal are independently delayed and added. By controlling the gain, it is possible to reproduce and pull in the carrier frequency at high speed.

[0037]

BEST MODE FOR CARRYING OUT THE INVENTION

1: Symbol synchronization: An embodiment of the present invention will be described below with reference to FIG. FIG. 1 is a block diagram of a receiver according to an embodiment of the present invention. The received signal is input from an input signal terminal 1 and a desired frequency band is selected by a tuner 10 and frequency-converted to an intermediate frequency band. The frequency-converted signal is quadrature-demodulated by the quadrature demodulator 11 to reproduce an I signal and a Q signal (baseband signal).

The obtained baseband signal passes through the low-pass filter 12 and is converted into a digital signal by the AD converter 23. From the digitized signals of the I signal and the Q signal, only the effective symbol portion is extracted by the guard interval removing circuit 14, and only the extracted effective symbol is passed to the FFT processing unit 15 at the subsequent stage. The effective symbol signal is converted from a signal in the time domain into a signal in the frequency domain by the FFT processing unit 15.

The converted signal corrects the distortion received on the transmission line by the transmission line compensating circuit 16 and outputs the QAM demodulation circuit 1 in the subsequent stage.
Transfer to 7. The QAM demodulation circuit 17 demodulates data of each carrier. The demodulated signal is subjected to error correction by an error correction circuit 18 and output as demodulated data.

Here, the configuration of the transmission signal will be described with reference to FIG. FIG. 8 shows one symbol of the transmission signal. 1
The symbol period 90 is the sum of the guard interval 91 and the effective symbol period 92. The guard interval signal 94 is configured using a part of the signal 95 after the effective symbol signal 93.

This relationship will be described with reference to FIG. FIG. 9 shows the same configuration of the L-th transmission symbol 101 as in FIG. The transmission symbol 101 is guard interval 1
02 and the effective symbol 103, and the transmission data 100a to 100g in the effective symbol 103
Contains N data.

The guard interval signals 100h to 100j in the guard interval 102 include Ng data. r- _Ng is the leading data 100h of the guard interval signal, which is the effective symbol signal 100h.
The same signal as the _rN-Ng signal of e is used. Similarly, data 1
00i is equal to data 100f, and data 100j is equal to data 100g.

When the transmission symbol 101 is configured in this way, the receiving side cuts out the effective symbol period 103 of the received signal by a window, and only this portion is subjected to FFT processing by the FFT processing unit 15 in FIG. You can do it.

Even if the transmitted signal is damaged by the multipath in the transmission path, if the maximum delay of the multipath is smaller than the guard interval time,
Data can be demodulated by the above processing.

However, if the guard interval is too long, the effective data amount with respect to the total transmission data amount becomes small, and the data transmission efficiency deteriorates.

As described above, in the OFDM transmission system, data can be reproduced by converting only the effective symbol signal from the time domain signal to the frequency domain signal by the FFT processing unit 15. For this purpose, it is necessary to accurately extract the effective symbol period.

In FIG. 1, the guard interval elimination circuit 14 separates only the effective symbols based on the synchronization signal 6 from the synchronization processing circuit 22 and passes it to the FFT processing unit 15 at the subsequent stage. The parameter determination circuit 24 extracts information related to the modulation parameter added on the transmission side, sends the information to the synchronization processing circuit 22 as a transmission parameter signal 25, and
In step 2, an error signal generation method for frequency synchronization and symbol synchronization is adaptively varied according to transmission parameters.

Here, a method of generating the synchronization signal 6 will be described with reference to the block diagram of FIG. FIG. 2 is a diagram showing a configuration of a block for generating a symbol synchronization signal in the synchronization processing circuit 22 of the present invention.

The signals 3 and 4 digitized by the A / D converter are input as an I signal input 60 and a Q signal input 61. The I signal input 60 is applied to the I signal autocorrelator 30.
The Q signal inputs 61 are respectively input to the Q signal autocorrelator 31 and processed. The I signal input 60 is delayed by the delay unit 33 by the number of points corresponding to the effective symbol period, and is multiplied by the multiplier with the original signal. The obtained result is added by the variable delay adder 39 based on the guard control signal 63.

The added signal is multiplied by a coefficient from a coefficient generator 45 by a multiplier 42 at the subsequent stage. This coefficient can be set to an appropriate value based on the guard control signal 63 and can be adaptively varied. The signals generated in this manner are added by the variable delay adder 48. At this time, the number of added data can be changed by the control signal 65,
The optimum addition number is set according to the reception state. Similarly, the same processing is applied to the Q signal input 61. A signal obtained by adding these signals by the adder 51 is subjected to waveform shaping by a waveform shaping circuit 52 to generate a symbol synchronization signal.

For example, as parameters used, the number of FFT points: 2048 (points) Guard interval: 128 (points) (1/1)
When 6) is used, the delay unit 33 in FIG. 2 delays 2048 samples, and the multipliers 36 and 37 perform multiplication with the original signal.

2: Symbol synchronization: FIG. 4 shows FIGS. 2 and 3.
Variable sample delay adders 39, 40, 4 shown in FIG.
1 is a diagram showing a configuration of FIG. N unit delay units 70a to 70n are connected in cascade, and each unit delay unit 70a
Adder 71 for adding the outputs of .about.70n and a unit delay unit 70
It comprises an enable control circuit 72 for controlling whether a to 70n operate.

The outputs of the multipliers 36, 37 and 38 shown in FIGS. 2 and 3 are input to the variable delays 39, 40 and 41, respectively, and the unit delays 70a. . . . Are entered in order. The enable control circuit 72 limits the operation range of the unit delay according to the guard signal 75. For example, if the guard interval period is 64 points, the unit delay amount is set so as to operate only 64 or less. These signals are added to generate a correlation output 74.

For example, as transmission parameters, the number of FFT points: 2048 (points) Guard interval: 64, 128, 256, 512 (points) Ratio: 1/32, 1/16, 1/8, 1/4 , The sample delay unit 70 of FIG.
It will have 12 sample delays. Actually, in order to avoid the influence of multi-paths and the like, about 256 of them may be used as a guide and about 256 delay units may be built in.

That is, assuming that the parameter indicating the transmission state transmits the guard interval at 64 points,
Only the first 64 delay units 70 are operated. Actually, about 32 pieces are sufficient for the above reason.

3: Symbol synchronization: FIG. 5 is a diagram showing the configuration of the variable sample delay adders 48 and 49 shown in FIG. The input signal 84 is input to an absolute value circuit 80 to extract only the magnitude component of the signal, and the output is input to a cascade-connected symbol delay circuit 81. The input signals are sequentially sent to the leading symbol delay circuits 81a to 81b, 81c, 81d,. . . . . 81n, and the respective outputs are added by an adder 82. The added signal is multiplied by the signal from the gain control circuit 87 by the multiplier 88. The gain control circuit 87 generates an optimum value based on an external control signal 86. The output of the multiplier 88 is output as an output signal 85.

For example, as transmission parameters, the number of FFT points: 2048 (points) Guard interval: 64, 128, 256, 512 (points) Ratio: 1/32, 1/16, 1/8, 1/4 In this case, the symbol delay unit 81 of FIG.
048 + 512 symbol delays will be performed.

Actually, it is changed depending on the size of the guard interval. That is, assuming that the parameter indicating the transmission state transmits the guard interval at 64 points, the symbol delay unit 81 performs 2112 sample delay. Further, by using a plurality of the sample delay units 81 and taking an averaging operation, the influence of noise can be reduced. At the same time, the synchronization signal can be stably reproduced even when a frequency error exists.

For example, if four are used here, only two sample delay units are operated at the time of pull-in, and all are operated when pull-in is completed, thereby stabilizing synchronization detection. At this time, the signal amount increases due to the addition.
Multiply by 1/4 when 4 are used. FIG. 11 shows a waveform when a synchronization signal is detected in the present invention.

FIG. 11 shows the FFT points: 2048,
Guard interval number: 128 points. The number of delay additions is eight. FIG. 11A shows a transmission waveform of an OFDM signal. When a frequency error exists on the transmission side and the reception side, detection of a synchronization signal is missing in a correlation signal as shown in FIG. 11B. According to the present invention, FIG.
It can be seen that the synchronization signal can be detected stably as shown in FIG.

4: Frequency synchronization: In FIG. 1, the quadrature demodulation unit 11 multiplies the sine wave and cosine wave output from the oscillator 19 by the input signal, and demodulates and outputs the I signal and the Q signal. The oscillator 19 controls the oscillation frequency of the frequency error signal 5 detected by the synchronization processing circuit 22 through the DA converter 21.

The synchronization processing circuit generates a frequency error signal from the output signals 3 and 4 of the A / D converter 13 and the reference signal 7 separated by the reference signal separation circuit 23. The A / D converter 13 converts the in-phase signal and the quadrature signal demodulated by the quadrature demodulator into a digital signal using the clock signal from the voltage controlled oscillator 20.

The voltage controlled oscillator 20 includes a synchronous processing circuit 22
Is controlled by a control signal 8. The cross-correlator 32 is multiplied by a multiplier 38 with a signal obtained by delaying the I signal input 60 and the Q signal input 61 by an effective symbol period by a delay unit 35, and the obtained signal is subjected to delay addition by a variable delay adder 41. . At this time, the range of the delay addition can be changed by the guard signal 63, and the obtained signal is multiplied by the signal generated by the coefficient generator 47 by the multiplier 44 at the subsequent stage.

At this time, the coefficient generator is also the guard signal generator 6
3 and can be changed in conjunction with each other. The arc tangent of the I signal signal generated by the autocorrelator 30 and the signal generated by the cross correlator 32 is obtained by the arithmetic processing unit 50, and the hold circuit 53 holds one symbol period data. This signal is subjected to delay addition processing by the variable delay adder 54 based on the control signal 66. The signal thus obtained is output as a frequency error signal.

In FIG. 3, the frequency error signal is generated based on the I signal input, but a similar error signal can be obtained by using the Q signal input. Similar effects can be obtained by using both signals.

5: Frequency Synchronization: FIG. 6 is a diagram showing the configuration of the variable sample delay adder 54 shown in FIG.
The input signal 84 is input to the cascade-connected symbol delay circuit 81. The input signals are sequentially sent to the first symbol delay circuits 81a to 81b, 81c, 81c.
d,. . . . . 81n, and the respective outputs are added by an adder 82. The added signal is used as a multiplier 88
Is multiplied by the signal from the gain control circuit 87. The gain control circuit 87 changes the adaptively generated coefficient based on a control signal 86 from the outside. The output of the multiplier 88 is output as an output signal 85.

For example, the number of FFT points: 2048 (points) Guard interval: 64, 128, 256, 512 (points) Ratio: 1/32, 1/16, 1/8, 1/4 as transmission parameters , The symbol delay unit 81 in FIG.
048 + 512 symbol delays will be performed.

Actually, it is changed depending on the size of the guard interval. That is, assuming that the parameter indicating the transmission state transmits the guard interval at 64 points, the symbol delay unit 81 delays 2112 samples. Also, this symbol delay unit 81
The influence of noise can be reduced by taking the averaging using a plurality of.

For example, here, four symbol delayers 8
When 1 is used, four sampling delay units are operated at the time of pull-in according to the operation state, and the gain is increased by the gain control circuit. When the initial pull-in is completed, only the two symbol delayers are operated, and the gain is reduced to increase the stability compared to the initial pull-in. In order to eventually track the frequency error, the operation of the symbol delayer is 1
Each is set, and the gain is controlled to be further reduced.
In this way, the frequency pull-in for the frequency error can be performed stably at high speed, and the tracking can be performed more stably.

6: Frequency Synchronization: FIG. 7 is a block diagram for generating a frequency error signal based on a reference signal. FIG.
, The output of the FFT processing unit 15 is
After compensating the transmission line distortion in step 6, the obtained signal is passed through a reference signal separation circuit 122 to separate the reference signal. At this time, the reference signal has a signal predetermined at a predetermined position inserted on the transmission side, and the receiver separates the reference signal according to the inserted rule. The separated reference signal is correlated with the reference signal generated from the reference signal generator 123 by the correlator 124. At this time, the reference signal generator 123 generates a reference signal based on an external reference synchronization signal.

FIG. 12 is a block diagram showing an embodiment of a correlator according to the present invention. The input signal 130 is input to the selection circuit 134 and is selected between the input signal 130 and a signal from the constant generator 133. The selection is a reference signal selection control signal generation circuit 1
41 is selected. The reference signal selection control signal generation circuit 141 calculates the position of the reference signal based on the reference signal start signal 131, operates the selection circuit 134, and passes the reference signal to a delay circuit 135.

Here, the signal output from the constant generator 133 generates "0". The signal that has passed through the selection circuit 134 is input to delay units 135a to 135n.
39 are multiplied by the coefficients C1 to Cn. The output of each multiplier 136 is added by an adder 138,
It is output as a correlation output signal 132. Delay device 135a
135n controls the operation based on the signal from the reference signal selection control signal generation circuit 141, and operates the delay units 135a to 135n only when the reference signal is detected.

The output of the correlator 124 performs addition or subtraction of the I signal and the Q signal by an adder 125 and passes the result to a variable delay adder 126. The variable delay adder 126 controls an addition amount and a gain by an external control signal.

The variable delay adder 126 has the same structure as the variable sample delay adder shown in FIG. 4, and the input signal 73 is input to a processing unit in which a plurality of sample delay units 70 are connected in cascade. Is sent to The addition of the output of each sample delay unit 70 is performed by the addition unit 71 to obtain an output signal. Using this frequency error signal, the oscillator 19 is controlled through the DA converter 21 in FIG. 1 to perform carrier synchronization.

7: Frequency synchronization: The output range of the frequency error signal 67 in FIG. 3 can be changed by the variable symbol delay adder 54 to an external control signal 66.

In FIG. 7, the output of the variable delay adder 126 is multiplied by the multiplier 120 with the coefficient of the gain controller 121. The variable delay adder 126 can change the addition range from a signal from an external control signal 117. Multiplier 120
Is added to the frequency error signal 67 in FIG. 3 by the adder 127 at the subsequent stage. The output from the adder 127 is output as the frequency error signal 114.

The same effect can be obtained by the symbol synchronization detection in the present invention. Further, the present invention is not limited to the above-described embodiment, and can be modified and implemented without departing from the gist of the present invention.

[0078]

As described above, according to the present invention, effective symbols can be extracted satisfactorily and good data can be obtained without causing inter-channel interference or inter-symbol interference even in a complicated multipath environment. Can be received.

Further, the frequency error on the transmitting side and the receiving side can be detected well, and carrier synchronization can be performed at high speed by controlling based on this signal.

Even if the transmission parameters are changed on the transmission side, the parameters can be adaptively handled by detecting the parameters on the reception side and using the method of the present invention.

Even in a complicated radio wave environment such as during mobile reception, good data can be reproduced, and high-quality video, audio, and data can be reproduced.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a signal processing system on a receiving side including an embodiment of the present invention.

FIG. 2 is a block diagram showing a block for generating a symbol synchronization signal according to one embodiment of the present invention.

FIG. 3 is a block diagram showing a block for generating a frequency error signal according to one embodiment of the present invention.

FIG. 4 is a block diagram illustrating a variable sample delay adder according to the present invention.

FIG. 5 is a block diagram showing a variable symbol delay adder according to the present invention.

FIG. 6 is a block diagram showing a variable symbol delay adder for detecting a frequency error according to the present invention.

FIG. 7 is a block diagram showing a frequency error generator of the present invention.

FIG. 8 is a diagram showing symbols of a normal transmission signal.

FIG. 9 is a diagram showing data in a symbol of a normal transmission signal.

FIG. 10 is a diagram showing a conventional frame configuration.

FIG. 11 is a diagram showing a symbol synchronization detection waveform.

FIG. 12 is a block diagram illustrating a correlator according to an embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 1 received signal input terminal 2 demodulated data output terminal 3 quadrature demodulated I signal 4 quadrature demodulated Q signal 5 frequency error signal 6 effective symbol reference signal 10 tuner 7 11 quadrature demodulator 13 AD converter 14 guard interval remover 15 FFT processing unit 16 Transmission path compensation circuit 17 QAM demodulation unit 18 Error correction unit 19, 20 Voltage controlled oscillator 21 DA converter 22 Synchronization processing circuit 23 Reference signal separation circuit 24 Parameter determination circuit 30, 31, 32 Correlation coefficient calculation unit 33, 34, 35 Symbol delay units 36, 37, 38 Multipliers 39, 40, 41 Variable sample delay adders 42, 43, 44 Multipliers 45, 46, 47 Coefficient generation units 48, 49 Variable symbol delay adders 50 Arithmetic processing units 51 Adders 52 Waveform shaping circuit 53 Hold circuit 54 Variable symbol delay adder 60 Signal input 61 Q signal input 62 Symbol synchronization signal 63 Guard signal 64 Symbol signal 65 Control signal 66 Control signal 67 Frequency error signal 70 Sample delay unit 71 Adder 72 Enable control circuit 73 I / Q signal input 74 Correlation output 75 Guard signal 76 Enable control signal 77 I / Q signal input 80 Absolute value circuit 81 Sample delay unit 82 Adder 83 Enable control circuit 84 Signal input terminal 85 Signal output terminal 86 Control signal input terminal 87 Gain control circuit 88 Multiplier 89 Enable control signal 90 Transmission Symbol 91 Guard period 92 Effective symbol period 93 Effective symbol 94 Guard interval signal 95 Information identical to guard interval 100 Transmission data sample sequence 101 Lth transmission symbol 102 Guard interval 10 Effective symbol 110 I signal input 111 Q signal input 112 I signal output 113 Q signal output 114 Frequency error signal output 115 Frequency error signal input 116 Reference synchronization signal 117 Control signal 120 Multiplier 121 Gain controller 123 Reference signal generator 124 Correlator 125 adder / subtractor 126 variable delay adder 127 adder 150 null symbol 151 guard interval 152 effective symbol

Claims (7)

[Claims] In a digital communication system for transmitting data by simultaneously using a plurality of mutually orthogonal carriers, a digital communication system in which one symbol period is transmitted using a signal format including an effective symbol period and a guard period is used. It is provided with a tuning means for tuning a desired frequency from a received signal and a quadrature demodulation means for demodulating an in-phase signal and a quadrature signal from the tuned quadrature modulated wave. A Fourier transform unit for performing a conversion, and an effective symbol delayer for delaying the in-phase signal and the quadrature signal by the effective symbol period time, and multiplying each of the signal delayed by the effective symbol delayer and the original signal. A variable sample delay adder for adding an output of the multiplier by a time corresponding to a guard period; A second multiplier for multiplying the output of the delay adder with a signal from the coefficient generator, a variable symbol delay adder for adding the output of the multiplier for a predetermined time and controlling the gain, and An orthogonal frequency division multiplexing demodulator, comprising: a waveform shaping circuit that generates a timing of an effective symbol from a signal of a delay adder; and performing the discrete Fourier transform based on an output signal of the waveform shaping circuit. 2. The variable sample delay addition means according to claim 1, further comprising: a sample delay unit for delaying in units of samples, a plurality of said sample delay units connected in cascade, and an adder for adding respective outputs. An enable control circuit that controls the operation of the sample delay unit with a guard signal from the outside is provided, so that the addition period can be changed according to the guard interval period, a symbol synchronization signal is generated adaptively, and a request is made based on this signal The orthogonal frequency division multiplexing demodulator according to claim 1, wherein the discrete Fourier transform according to item 1 is performed. 3. The variable symbol delay adding means according to claim 1, further comprising: a variable symbol delay device for delaying by a period obtained by adding an effective symbol period and a guard period; and an absolute value circuit for obtaining an absolute value of an input signal. A plurality of delay units connected in cascade, an adder for adding the outputs of the delay units, an addition period control unit capable of changing an addition period according to a position determination state and an operation start state of the effective symbol; 2. A gain control circuit for controlling a gain by an external control signal and a third multiplier for multiplying, and the discrete Fourier transform is performed based on an output signal of the third multiplier. The demodulator of the orthogonal frequency division multiplex system described in the above. 4. An effective symbol delay device for delaying the in-phase signal and the quadrature signal according to claim 1 by an effective symbol period, and a first multiplier for multiplying the quadrature signal and the in-phase signal respectively. A variable sample delay adder for performing sample delay addition of a result multiplied by the first multiplier, and a second unit for multiplying a signal value obtained from the variable sample delay adder by a signal from a coefficient generator. 2. A multiplier, comprising: the second multiplier according to claim 1; an arithmetic processing unit for performing an arithmetic operation on an output signal of the second multiplier; and a hold circuit for holding an output of the arithmetic processing unit at a predetermined timing. , A variable symbol delay adder that adds the output of the hold circuit for a predetermined period, and controls the frequency oscillator for quadrature demodulation using the output of the variable symbol delay adder as a frequency error signal The orthogonal frequency division multiplexing demodulator according to claim 1, wherein: 5. A variable symbol delay adder for adding a hold circuit output for a predetermined period according to claim 4, further comprising a symbol delay unit for delaying by a period obtained by adding an effective symbol period and a guard period. A plurality of cascaded connections, an adder for adding their outputs, an enable control circuit for controlling an operation state of the symbol delay unit according to an external control signal, and a gain for controlling a gain based on the control signal The orthogonal frequency division multiplexing demodulator according to claim 4, further comprising a multiplier, comprising a control circuit, for multiplying the output of the adder based on a signal from the gain control circuit. 6. A reference signal separation circuit for separating a reference signal inserted at the time of transmission from an output of the Fourier transform unit according to claim 1, further comprising a reference signal generator for generating the same reference signal as that on the transmission side. A correlator for correlating a signal separated by the reference signal separation circuit with a reference signal generated by the reference signal generator; a variable symbol delay adder for adding an output signal of the correlator; 2. An orthogonal frequency division multiplex demodulator according to claim 1, wherein an output of the delay adder controls an orthogonal demodulation frequency oscillator. 7. A variable symbol delay adder for adding a frequency error signal output from a variable symbol delay adder according to claim 4 and a frequency error signal output from a variable symbol delay adder according to claim 6, wherein each variable symbol delay is 7. The orthogonal frequency according to claim 4, wherein an addition amount and a gain of the adder can be controlled separately, and an output of the adder is used as a frequency error signal to control a frequency oscillator for orthogonal demodulation. Demodulator of division multiplex system.