JP3507657B2 - Orthogonal frequency division multiplexing demodulator - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a demodulator in a communication system using an orthogonal frequency division multiplexing system, and more particularly to that system.

[0002]

2. Description of the Related Art Although terrestrial digital broadcasting has been actively researched and developed, the amount of information in a digitized image is significantly reduced by the progress of the image compression technology based on MPEG2, and transmission by wireless communication is possible. Progressed to the level.

Generally, when transmitting these compressed data, an information transmission rate of about 5 to 20 Mbps is usually required. If an error correction method for correcting an error in the data or a code modulation method capable of improving the durability against the error is used for these data, the redundancy is further increased and a higher transmission rate is required.

In order to transmit such information within a limited band, it is necessary to develop a more efficient transmission method. At present, as a solution to this problem, it has been proposed to transmit the information to be transmitted in multivalued digital form. Particularly, in order to realize terrestrial digital broadcasting in the future, an 8VSB system for transmitting 8 levels using a 6 MHz band is being studied in the United States.

The 8VSB system can transmit 3-bit information in one symbol and has a symbol rate of 10.76M baud in a band of 6MHz. Although this system has high band utilization efficiency, it has an aspect that it is difficult to adapt to SFN (Single Frequency Network) and mobile reception.
On the other hand, in Japan and Europe, orthogonal frequency division multiplexing is being studied. This system is a system for transmitting information by using a plurality of carriers at the same time, and has a characteristic that it is strong against multipath and can be applied to SFN (Single Frequency Network) and mobile reception.

In a limited radio wave environment such as terrestrial broadcasting, it is becoming important to use radio waves, which is one of effective resources, efficiently. It is being developed as a digital transmission system in the digital broadcasting era. The orthogonal frequency division multiplexing system is a system for transmitting information by simultaneously using a plurality of orthogonal carriers, and the number of carriers used at this time is about 1000 to 8000.
It is about a book.

Further, each carrier wave is modulated by multi-level QAM or the like, which is a system with high band utilization efficiency. Conventionally, this technique was developed as a technique used for digital audio stereo broadcasting in Europe, and it has been known that it can be realized by using a fast Fourier transform (FFT) as a means for modulating a large number of carrier waves at the same time, and it has already been put to practical use. Is being done.

[0008] For example, regarding this technique, Michel
Arard, Rpselyne Lassall
e "Principle of modulation
and channel coding for d
digital broadcasting for m
mobile receivers "EBU REVIE
W-TECHNICAL 1987, pp168-18
0 in detail. The basic principle of OFDM is as follows. If the carrier frequency is {f _k }, then f _k = f ₀ + k / T _s k = _{0 to} N−1 Let the basic signal be Ψ _j , _k (t), then Ψ _j , _k (t) = g _k ( t−jT _s ) k = 0 to N−1, j
= −∞ to + ∞ g _k = exp (2iπf _k t) 0 ≦ t ≦ T _s g _k = 0 otherwise The frequency spectra of the signal g _k (t) overlap with each other. Ψ _j , _k (t) satisfy the orthogonal conditions with each other.

The complex sequence of data to be transmitted is {C _j , _k }
Then, the OFDM transmission signal X (t) can be described as follows.

[0010]

[Equation 1]

The received signal is demodulated by the following equation.

[0012]

[Equation 2]

When the above signal is transmitted through the transmission line, the orthogonality is damaged and disturbed by the distortion and multipath caused by the transmission line. Therefore, intersymbol interference may occur in the demodulated signal of the received signal. Which results in increased error.
As one solution to this problem, a method has been proposed in which a guard interval for absorbing intersymbol interference is provided before each signal Ψ _j , _k (t) at the expense of part of the transmission energy.

At this time, the symbol period of the transmission signal is described by the following equation.

T's = Ts + Δ Here, Ts is an effective symbol period, Δ is a guard interval period, and when an effective signal is Ψ _j , _k (t), Ψ _j , _k (t) = g _k (t -jt's) this time transmission signal _{Ψ 'j, k (t)} = g' k (t-jT's) g 'k = exp (2iπf k t) -Δ ≦ t <Ts g' k = 0 otherwise At this time, the OFDM transmission signal X (t) can be described as follows.

[0016]

[Equation 3]

The received signal is demodulated by the following equation.

[0018]

[Equation 4]

The guard interval can prevent inter-channel interference and inter-symbol interference by adding an invalid symbol as a buffer data portion before a valid symbol which is originally desired to be transmitted, and has high quality in digital transmission. You can send information. At this time, a part of the effective symbol is used as the invalid symbol to be added, which corresponds to a period of several tenths to a fraction of the whole number.

The transmitted signal waveform thus generated has a form like random noise, and the delimiters between symbols are not known. If the position of the symbol is not known accurately, intersymbol interference with adjacent symbols will occur and the demodulated signal will deteriorate. Therefore, conventionally, a null symbol signal has been used for symbol synchronization at the expense of some symbols. FIG. 10 is a diagram showing a frame structure of a conventional transmission signal. Each symbol guard interval 15
1 and an effective symbol 152 are added together, and a plurality of added symbols are collected into one frame, and a null symbol 150 is inserted at the beginning thereof.

This method has a drawback that the amount of information that can be transmitted is reduced, and efficient information transmission cannot be performed. As a means for solving this, a method has been proposed in which the correlation coefficient of a part of the guard period and the effective symbol period is calculated to detect symbol synchronization (Japanese Patent Laid-Open No. 7-14309).
7: OFDM synchronous demodulation circuit).

Since the signal waveform transmitted by the orthogonal frequency division multiplexing system is multi-carrier transmission, a large number of carriers (50 MHz) within a limited band (6 MHz to 9 MHz) are used.
(0 to 8000 lines), the frequency interval of each carrier becomes very narrow, about 1 KHz to 10 KHz.

Therefore, if there is a deviation between the frequency on the transmitting side and the frequency on the receiving side, the quality of the demodulated signal is greatly deteriorated. For the above reasons, it is necessary to accurately reproduce the carrier frequency on the receiver side in the orthogonal frequency division multiplexing system.
Regarding the conventional reproduction of carrier frequency, the transmitting side allocates the reference signal to the predetermined position of each symbol and inserts the specified signal, and the receiving side adopts the method of reproducing the carrier frequency based on this. Was there.

When this method is used, if the reference signal is disturbed, the carrier cannot be reproduced, and the demodulated received signal is greatly deteriorated. Also, using the guard interval and the correlation coefficient of the effective symbol, the autocorrelation coefficient of the I signal and the IQ
The correlation coefficient of the signal is calculated and the frequency error is calculated.
A method of reproducing a carrier based on this error signal has been proposed (Japanese Patent Laid-Open No. 7-143097: OFDM synchronous demodulation circuit).

[0025]

Generally, the signal waveform transmitted by the orthogonal frequency division multiplexing system is a waveform like random noise, and it is difficult to determine the delimiter between symbols. If the symbol position is not known accurately at the receiver, intersymbol interference with adjacent symbols will occur and the demodulated signal will deteriorate.

For this reason, conventionally, a null symbol signal is inserted for symbol synchronization at the expense of some symbols. However, this method has a drawback that the amount of information that can be transmitted is reduced. As a means for solving this, a method has been proposed in which the correlation coefficient of a part of the guard period and the effective symbol period is calculated to detect symbol synchronization.
In this proposal, when the correlation coefficient is calculated, a large correlation can be obtained periodically, so that the timing of this peak is determined as a symbol break.

Based on this timing, the flywheel timing circuit can remove noise and peaks of pseudo correlation. However, in this method, when a frequency offset exists, a peak may not be obtained in the output of the correlation coefficient. In this case, symbol synchronization is lost, intersymbol interference with adjacent symbols occurs, and the characteristics of the demodulated signal deteriorate.

Further, since the peak does not appear in the correlation coefficient at the initial pull-in of symbol synchronization, there is a problem that the pull-in time is long. The conventionally proposed method of reproducing the carrier frequency has a drawback that the time for pulling in the carrier frequency becomes long.

[0029]

Means for Solving the Problems (1) In a digital communication system for transmitting data by simultaneously using a plurality of carriers that are orthogonal to each other, a signal format in which one symbol period includes an effective symbol period and a guard period is used. In the transmitted system, the digital signal obtained is provided with a channel selecting means for selecting a desired frequency from the received signal and a quadrature demodulating means for demodulating an in-phase signal and a quadrature signal from the selected quadrature modulated wave. A Fourier transform unit for transforming data by a discrete Fourier transform, and an effective symbol delayer for delaying the in-phase signal and the quadrature signal by the effective symbol period time, a signal delayed by the effective symbol delayer, and an original signal A variable sample delay for adding the output of the multiplier for a time period according to the guard period. A variable symbol delay adder that includes an adder and a second multiplier that multiplies the output of the variable sample delay adder with the signal from the coefficient generator, and adds the output of the multiplier for a predetermined time to control the gain. And a waveform shaping circuit for generating the timing of the effective symbol from the signal of the variable symbol delay adder,
An orthogonal frequency division multiplex system demodulator, characterized in that the discrete Fourier transform is performed based on the output signal of the waveform shaping circuit.

(2) The variable sample delay adding means of (1) includes a sample delayer for delaying in sample units, a plurality of sample delayers are cascade-connected, and an adder for adding respective outputs is added, Equipped with an enable control circuit that controls the operation of the sample delay unit in the first half by using a guard signal from the outside so that the addition period can be changed according to the guard interval period and the symbol synchronization signal is adaptively generated. An orthogonal frequency division multiplex system demodulator, which performs the discrete Fourier transform according to claim 1.

(3) The variable symbol delay adding means of (1) includes a variable symbol delay device that delays by a period obtained by adding the effective symbol period and the guard period, and an absolute value circuit that takes an absolute value of an input signal. A plurality of symbol delay devices are connected in cascade, each of which is provided with an adder for adding respective outputs, and an addition period control unit capable of changing the addition period according to the position determination state and the operation start state of the effective symbol is provided. An orthogonal frequency characterized by including a gain control circuit for controlling a gain by an external control signal and a third multiplier for multiplying the output, and performing the discrete Fourier transform based on an output signal of the third multiplier. Division multiplex demodulator.

(4) A first multiplier having an effective symbol delay device for delaying an in-phase signal and a quadrature signal according to (1) by an effective symbol period, and performing multiplication with the quadrature signal and the in-phase signal, respectively. A variable sample delay adder for performing sample delay addition on the result multiplied by the first multiplier, and multiplying the value of the signal obtained by the variable sample delay adder with the signal from the coefficient generator, A hold circuit that includes two multipliers, comprises a second multiplier according to claim 1, and an arithmetic processing unit that arithmetically operates an output signal of the second multiplier, and holds an output of the arithmetic processing unit at a predetermined timing. A variable symbol delay adder for adding the output of the hold circuit for a predetermined period is provided, and the output of the variable symbol delay adder is used as a frequency error signal to provide a frequency oscillator for quadrature demodulation. Demodulator of the orthogonal frequency division multiplexing system, characterized in that Gosuru.

(5) A variable symbol delay adder for adding the output of the hold circuit in (4) for a predetermined period includes a symbol delay device for delaying a period obtained by adding the effective symbol period and the guard period. A plurality of cascade-connected, and an adder for adding respective outputs, and an enable control circuit for controlling the operating state of the symbol delay unit according to a control signal from the outside, and controlling the gain based on the control signal. An orthogonal frequency division multiplex system demodulator, comprising: a gain control circuit; and a multiplier that multiplies the output of the adder based on a signal from the gain control circuit.

(6) A reference signal separation circuit for separating the reference signal inserted at the time of transmission from the output of the Fourier transform section in (1) is provided, and a reference signal generator for generating the same reference signal as that at the transmission side is provided. A variable symbol delay adder for adding the output signals of the correlator, and a variable symbol delay adder for correlating the signal separated by the reference signal separation circuit and the reference signal generated by the reference signal generator. An orthogonal frequency division multiplex system demodulator, wherein a frequency oscillator for orthogonal demodulation is controlled by the output of a symbol delay adder.

(7) An adder for adding the frequency error signal output from the variable symbol delay adder in (4) and the frequency error signal output from the variable symbol delay adder in (6) is provided. An orthogonal frequency division multiplex system demodulator, wherein the addition amount and gain of the delay adder can be controlled separately and the output of the adder is used as a frequency error signal to control a frequency oscillator for orthogonal demodulation.

When the processing method of the present invention is used, symbol synchronization can be detected stably even in the presence of a frequency offset, and good signal demodulation can be performed. It is possible to execute the initial symbol synchronization pull-in at high speed. In reproducing the carrier frequency, the frequency error signal calculated by the calculation processing of the autocorrelation of the I signal and the Q signal and the correlation coefficient of the IQ signal and the frequency error signal calculated from the reference signal are delayed and added independently. By controlling the gain, it is possible to reproduce and pull in the carrier frequency at high speed.

[0037]

DETAILED DESCRIPTION OF THE INVENTION

1: Symbol synchronization: An embodiment of the present invention will be described below with reference to FIG. FIG. 1 is a block diagram of an embodiment of a receiver of the present invention. The received signal is input from the input signal terminal 1, the desired frequency band is selected by the tuner 10, and the frequency is converted to the intermediate frequency band. The frequency-converted signal is orthogonally demodulated by the orthogonal demodulator 11 to reproduce the I signal and the Q signal (baseband signal).

The obtained baseband signal is converted into a digital signal by the AD converter 23 through the low pass filter 12. Only the effective symbol portion of the digitized signal of the I signal and the Q signal is taken out by the guard interval removing circuit 14, and only the taken out effective symbol is passed to the FFT processing unit 15 in the subsequent stage. The effective symbol signal is converted by the FFT processing unit 15 from a time domain signal to a frequency domain signal.

The converted signal corrects the distortion received on the transmission line by the transmission line compensating circuit 16, and the QAM demodulating circuit 1 at the subsequent stage is corrected.
Pass to 7. The QAM demodulation circuit 17 demodulates the data of each carrier. The demodulated signal is error-corrected by the error correction circuit 18 and output as demodulated data.

Here, the structure of the transmission signal will be described with reference to FIG. FIG. 8 shows one symbol of the transmission signal. 1
The symbol period 90 is a combination of the guard interval 91 and the effective symbol period 92. The guard interval signal 94 is formed by using a part of the signal 95 after the effective symbol signal 93.

This relationship will be described with reference to FIG. FIG. 9 shows the structure of the L-th transmission symbol 101 which is the same as that in FIG. Transmission symbol 101 is guard interval 1
02 and an effective symbol 103, and transmission data 100a to 100g in the effective symbol 103.
Contains N data.

The guard interval signals 100h to 100j in the guard interval 102 include Ng data. r- _Ng is the leading data 100h of the guard interval signal and is the effective symbol signal 100.
The same signal as the r _N-Ng signal of e is used. Similarly, data 1
00i is equal to data 100f, and data 100j is equal to data 100g.

When the transmission symbol 101 is constructed in this manner, the effective symbol period 103 of the received signal is cut out by a window on the receiving side, and only this portion is FFT processed by the FFT processing unit 15 in FIG. 1 to reproduce the signal. You can do it.

Even if the signal transmitted at this time is damaged by multipath in the transmission path, if the maximum delay amount of the multipath is smaller than the guard interval time,
Data can be demodulated by the above processing.

However, if the guard interval is made too long, the effective data amount with respect to the total transmitted data amount becomes small, and the data transmission efficiency deteriorates.

From the above, in the OFDM transmission system, data can be reproduced by converting only the effective symbol signal from the time domain signal to the frequency domain signal by the FFT processing unit 15. For this purpose, it is necessary to accurately extract the effective symbol period.

In FIG. 1, the guard interval removal circuit 14 separates only the effective symbol based on the synchronization signal 6 from the synchronization processing circuit 22 and passes it to the FFT processing unit 15 in the subsequent stage. The parameter determination circuit 24 extracts the information about the modulation parameter added on the transmission side, passes it to the synchronization processing circuit 22 as a transmission parameter signal 25, and outputs it to the synchronization processing circuit 2.
In 2, the error signal generation method of frequency synchronization and symbol synchronization is adaptively changed according to the transmission parameter.

Here, a method of generating the synchronization signal 6 will be described with reference to the block diagram of FIG. FIG. 2 is a diagram showing the structure of a block in the synchronization processing circuit 22 of the present invention which is generating a symbol synchronization signal.

The signals 3 and 4 digitized by the A / D converter are input as an I signal input 60 and a Q signal input 61. The I signal input 60 is input to the I signal autocorrelator 30,
The Q signal inputs 61 are input and processed in the Q signal autocorrelator 31, respectively. The I signal input 60 is delayed by the delay device 33 by the number of points corresponding to the effective symbol period, and is multiplied by the original signal by the multiplier 36. The obtained results are added by the variable delay adder 39 based on the guard control signal 63.

The added signal is multiplied by the coefficient from the coefficient generator 45 by the multiplier 42 in the subsequent stage. This coefficient can be adaptively varied by setting an appropriate value based on the guard control signal 63. The signals thus generated are added by the variable delay adder 48. At this time, the number of added data can be changed by the control signal 65,
The optimum addition number is set according to the reception state. Similarly, the same processing is performed on the Q signal input 61. These signals are added by the adder 51 and the obtained signal is shaped by the waveform shaping circuit 52 to generate a symbol synchronization signal.

For example, the number of FFT points used as parameters is 2048 (points) Guard interval: 128 (points) (1/1
6) is used, the delay unit 33 in FIG. 2 delays by 2048 samples, and the multipliers 36 and 37 perform multiplication with the original signal.

2: Symbol synchronization: FIG. 4 shows FIG. 2 and FIG.
Variable sample delay adders 39, 40, 4 shown in FIG.
It is a figure which shows the structure of 1. N unit delay devices 70a to 70n are cascade-connected, and each unit delay device 70a
Adder 71 and unit delay device 70 for adding outputs of up to 70 n
It is composed of an enable control circuit 72 for controlling whether or not a to 70n operate.

The outputs of the multipliers 36, 37 and 38 shown in FIGS. 2 and 3 are input to the variable delay units 39, 40 and 41, and the unit delay units 70a. ． ． ． Are input in order. The enable control circuit 72 limits the operation range of the unit delay according to the guard signal 75. For example, if the guard interval period is 64 points, the unit delay amount is set so that only 64 or less units operate. These signals are added to generate a correlation output 74.

For example, the number of FFT points: 2048 (points), guard interval: 64, 128, 256, 512 (points) ratio: 1/32, 1/16, 1/8, 1/4 are used as transmission parameters. If the sample delay unit 70 of FIG.
It will have 12 sample delays. Actually, in order to avoid the influence of multipath and the like, about half of this is a guideline and about 256 delay devices may be incorporated.

That is, assuming that the parameter indicating the transmission state is transmitting the guard interval at 64 points,
Only 64 delay devices 70 will be operated from the beginning. Actually, about 32 is sufficient for the above reason.

3: Symbol synchronization: FIG. 5 is a diagram showing the configuration of the variable sample delay adders 48 and 49 shown in FIG. The input signal 84 is input to the absolute value circuit 80 in order to extract only the magnitude component of the signal, and its output is input to the symbol delay circuit 81 connected in cascade. The input signals are sequentially output from the leading symbol delay circuits 81a to 81b, 81c, 81d ,. ． ． ． ． 81n, and the respective outputs are added by the adder 82. The added signal is multiplied by the signal from the gain control circuit 87 by the multiplier 88. The gain control circuit 87 generates an optimum value based on a control signal 86 from the outside. The output of the multiplier 88 is output as the output signal 85.

For example, the number of FFT points: 2048 (points), guard interval: 64, 128, 256, 512 (points) ratio: 1/32, 1/16, 1/8, 1/4 is used as a transmission parameter. In this case, the symbol delay unit 81 of FIG.
A delay of 048 + 512 symbols will be performed.

Actually, it is changed depending on the size of the guard interval. That is, if the parameter indicating the transmission state is that the guard interval is transmitted at 64 points, the symbol delay unit 81 will delay 2112 samples. Moreover, the influence of noise can be reduced by using a plurality of the sample delay units 81 and taking the averaging. At the same time, the synchronization signal can be stably reproduced even when there is a frequency error.

For example, when four pieces are used here, only two sample delay units are operated at the time of pull-in, and all are operated after the pull-in is completed to stabilize the synchronization detection. At this time, since the signal amount increases due to the addition, the signal is halved by the gain control circuit 87 when two are used.
When using four, multiply by 1/4. FIG. 11 shows a waveform when a sync signal is detected in the present invention.

FIG. 11 shows the number of FFT points: 2048,
Number of guard intervals: 128 points. The number of delayed additions is eight. FIG. 11A shows the transmission waveform of the OFDM signal, and when the frequency error exists on the transmission side and the reception side, the detection of the synchronization signal is missing in the correlation signal as shown in FIG. 11B. According to the invention, FIG.
As shown in (c), it can be seen that the sync signal can be stably detected.

4: Frequency synchronization: In FIG. 1, the quadrature demodulation unit 11 multiplies the sine wave and the cosine wave output from the oscillator 19 by the input signal, demodulates the I signal and the Q signal, and outputs them. The oscillator 19 controls the oscillation frequency of the frequency error signal 5 detected by the synchronization processing circuit 22 through the DA converter 21.

The synchronization processing circuit generates a frequency error signal from the output signals 3 and 4 of the A / D converter 13 and the reference signal 7 separated by the reference signal separation circuit 23. The A / D converter 13 converts the in-phase signal and the quadrature signal demodulated by the quadrature demodulator by the clock signal from the voltage controlled oscillator 20 into a digital signal.

The voltage controlled oscillator 20 includes a synchronization processing circuit 22.
Is controlled by the control signal 8 from To the cross-correlator 32, a signal obtained by delaying the I signal input 60 and the Q signal input 61 by the delay device 35 by the effective symbol period is multiplied by the multiplier 38, and the obtained signal is delayed and added by the variable delay adder 41. . At this time, the guard signal 63 can change the delay addition range, and the obtained signal is multiplied by the signal generated by the coefficient generator 47 by the multiplier 44 in the subsequent stage.

At this time, the coefficient generator is also the guard signal generator 6
It is configured to be variable by interlocking with 3. The arc tangent of the I signal generated by the autocorrelator 30 and the signal generated by the crosscorrelator 32 is calculated by the arithmetic processing unit 50, and the 1-symbol period data is held by the hold circuit 53. This signal is subjected to delay addition processing by the variable delay adder 54 based on the control signal 66. The signal thus obtained is output as a frequency error signal.

Although the frequency error signal is generated with reference to the I signal input in FIG. 3, a similar error signal can be obtained by using the Q signal input. The same effect can be obtained by using both signals.

5: Frequency synchronization: FIG. 6 is a diagram showing the configuration of the variable sample delay adder 54 shown in FIG.
The input signal 84 is input to the symbol delay circuit 81 connected in cascade. The input signals are sequentially output from the leading symbol delay circuits 81a to 81b, 81c, 81.
d ,. ． ． ． ． 81n, and the respective outputs are added by the adder 82. The added signal is a multiplier 88
Is multiplied by the signal from the gain control circuit 87. The gain control circuit 87 adaptively changes the generated coefficient based on the control signal 86 from the outside. The output of the multiplier 88 is output as the output signal 85.

For example, the number of FFT points: 2048 (points) guard interval: 64, 128, 256, 512 (points) ratio: 1/32, 1/16, 1/8, 1/4 is used as a transmission parameter. If the symbol delay device 81 of FIG.
A delay of 048 + 512 symbols will be performed.

Actually, it is changed depending on the size of the guard interval. That is, if the parameter indicating the transmission state is that the guard interval is transmitted at 64 points, the symbol delay unit 81 delays by 2112 samples. Also, this symbol delay unit 81
It is possible to reduce the influence of noise by using multiple averages and taking the averaging.

For example, here, four symbol delay units 8
When 1 is used, four sample delay units are operated at the time of pulling in according to the operating state, and the gain is increased by the gain control circuit. When the initial pull-in is completed, only two symbol delay units are operated, and the gain is made smaller than that in the initial pull-in in order to increase the stability. In order to finally track the frequency error, the symbol delay operation is 1
Individually set, and controlled to further reduce the gain.
In this way, the frequency pull-in for the frequency error can be stably performed at high speed, and the tracking can be performed more stably.

6: Frequency synchronization: FIG. 7 shows a block diagram for generating a frequency error signal according to a reference signal. Figure 1
At the output, the output of the FFT processing unit 15
After the transmission line distortion is compensated by 6, the obtained signal is passed through the reference signal separation circuit 122 to separate the reference signal. At this time, as the reference signal, a signal determined in advance at a predetermined position on the transmission side is inserted, and the reference signal is separated on the receiver side according to the inserted rule. The separated reference signal is correlated with the reference signal generated by the reference signal generator 123 by the correlator 124. At this time, the reference signal generator 123 generates a reference signal based on an external reference synchronization signal.

FIG. 12 is a block diagram showing an embodiment of a correlator according to the present invention. The input signal 130 is input to the selection circuit 134 and is selected from the signals from the constant generator 133. The selection is the reference signal selection control signal generation circuit 1
41 is selected. The reference signal selection control signal generation circuit 141 calculates the position of the reference signal based on the reference signal start signal 131, operates the selection circuit 134, and passes the reference signal peak to the delay circuit 135.

Here, the signal output from the constant generator 133 is "0". The signals that have passed through the selection circuit 134 are input to the delay devices 135a to 135n, and the outputs of the delay circuits 135a to 135n are input to the reference coefficient generator 1 by the multiplier 136 of 136.
Multiply the coefficients C1 to Cn generated from 39. The outputs of the respective multipliers 136 are added by the adder 138,
It is output as the correlation output signal 132. Delay device 135a
To 135n control the operation based on the signal from the reference signal selection control signal generation circuit 141, and operate the delay devices 135a to 135n only when the reference signal is detected.

The output of the correlator 124 is added to or subtracted from the I signal and the Q signal by the adder 125, and is passed to the variable delay adder 126. The variable delay adder 126 controls the amount of addition and the gain by an external control signal.

The variable delay adder 126 has the same structure as the variable sample delay adder shown in FIG. 4, and the input signal 73 is input to the processing section to which a plurality of sample delay units 70 are connected in cascade, and the sequence is changed. Is sent to. The outputs of the respective sample delay units 70 are added by the adder 71 to obtain output signals. Using this frequency error signal, the oscillator 19 is controlled through the DA converter 21 in FIG. 1 to perform carrier synchronization.

7: Frequency synchronization: The output range of the frequency error signal 67 in FIG. 3 can be changed by the variable symbol delay adder 54 to a control signal 66 from the outside.

In FIG. 7, the output of the variable delay adder 126 is multiplied by the coefficient of the gain controller 121 by the multiplier 120. The variable delay adder 126 can change the addition range from the signal from the external control signal 117. Multiplier 120
Is added to the frequency erroneous calculation signal 67 of FIG. 3 by the adder 127 in the subsequent stage. The output from the adder 127 is output as the frequency error signal 114.

Similar effects can be obtained in the symbol synchronization detection according to the present invention. Further, the present invention is not limited to the above-mentioned embodiment, and can be modified and carried out without departing from the gist of the present invention.

[0078]

As described above, according to the present invention, effective symbols can be extracted well, and even in a complicated multipath environment, good data can be obtained without causing interchannel interference or intersymbol interference. Can be received.

Further, the frequency error on the transmitting side and the receiving side can be satisfactorily detected, and carrier synchronization can be performed at high speed by controlling based on this signal.

Even if the transmission parameter is changed on the transmitting side, the receiving side can detect the parameter and adaptively cope with it by using the method of the present invention.

Even in a complicated radio wave environment such as during mobile reception, good data can be reproduced, and high quality video, audio and data can be reproduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a signal processing system on a receiving side including an embodiment of the present invention.

FIG. 2 is a block diagram showing a block for generating a symbol synchronization signal according to an embodiment of the present invention.

FIG. 3 is a block diagram showing a block for generating a frequency error signal according to an embodiment of the present invention.

FIG. 4 is a block diagram showing a variable sample delay adder of the present invention.

FIG. 5 is a block diagram showing a variable symbol delay adder of the present invention.

FIG. 6 is a block diagram showing a variable symbol delay adder for frequency error detection according to the present invention.

FIG. 7 is a block diagram showing a frequency error generation unit of the present invention.

FIG. 8 is a diagram showing symbols of a normal transmission signal.

FIG. 9 is a diagram showing data in a symbol of a normal transmission signal.

FIG. 10 is a diagram showing a conventional frame structure.

FIG. 11 is a diagram showing a symbol synchronization detection waveform.

FIG. 12 is a block diagram showing a correlator according to an embodiment of the present invention.

[Explanation of symbols]

1 Received signal input terminal 2 Demodulated data output terminal 3 Quadrature demodulation I signal 4 Quadrature demodulation Q signal 5 Frequency error signal 6 Effective symbol reference signal 10 tuner 7 11 Quadrature demodulator 13 AD converter 14 Guard interval removal unit 15 FFT processing section 16 Transmission line compensation circuit 17 QAM demodulator 18 Error correction section 19, 20 Voltage controlled oscillator 21 DA converter 22 Synchronous processing circuit 23 Reference signal separation circuit 24 parameter judgment circuit 30, 31, 32 Correlation coefficient calculator 33, 34, 35 symbol delayer 36, 37, 38 Multiplier 39, 40, 41 Variable sample delay adder 42, 43, 44 multiplier 45, 46, 47 Coefficient generator 48, 49 Variable Symbol Delay Adder 50 arithmetic processing unit 51 adder 52 waveform shaping circuit 53 Hold circuit 54 Variable Symbol Delay Adder 60 I signal input 61 Q signal input 62 symbol sync signal 63 Guard signal 64 symbol signal 65 control signal 66 control signal 67 Frequency error signal 70 sample delay 71 adder 72 Enable control circuit 73 I / Q signal input 74 Correlation output 75 Guard signal 76 Enable control signal 77 I / Q signal input 80 Absolute value circuit 81 sample delay 82 adder 83 Enable control circuit 84 signal input terminal 85 Signal output terminal 86 Control signal input terminal 87 Gain control circuit 88 multiplier 89 Enable control signal 90 transmission symbols 91 Guard period 92 Effective symbol period 93 valid symbols 94 guard interval signal The same information as 95 Guard Interval 100 transmission data sample sequence 101 Lth transmission symbol 102 guard interval 103 valid symbols 110 I signal input 111 Q signal input 112 I signal output 113 Q signal output 114 Frequency error signal output 115 Frequency error signal input 116 Reference sync signal 117 control signal 120 multiplier 121 gain controller 123 Reference signal generator 124 Correlator 125 adder / subtractor 126 Variable delay adder 127 adder 150 null symbol 151 guard interval 152 Effective symbol

Continuation of the front page (56) Reference JP-A-7-99486 (JP, A) JP-A-10-209998 (JP, A) JP-A-10-190610 (JP, A) JP-A-8-102771 (JP , A) JP 8-237219 (JP, A) JP 7-143097 (JP, A) JP 10-117178 (JP, A) JP 9-219692 (JP, A) JP 2002 -64457 (JP, A) JP-A-11-112460 (JP, A) JP-A-10-308716 (JP, A) JP-A-10-294711 (JP, A) JP-A-8-223132 (JP, A) ) JP 2001-7781 (JP, A) JP 6-38332 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H04J 11/00

Claims (7)

(57) [Claims] 1. A digital communication system for transmitting data by simultaneously using a plurality of mutually orthogonal carrier waves, in a system in which one symbol period is transmitted using a signal format composed of an effective symbol period and a guard period. Equipped with a channel selection means for selecting a desired frequency from the received signal and a quadrature demodulation means for demodulating an in-phase signal and a quadrature signal from the selected quadrature modulated wave, and the obtained digital signal is subjected to data by discrete Fourier transform. A Fourier transform unit for converting the effective signal delay unit for delaying the in-phase signal and the quadrature signal by the effective symbol period time, and multiplying each of the signal delayed by the effective symbol delay unit and the original signal A variable sample delay adder for adding the output of the multiplier for a time period according to a guard period, and the variable sampler A variable symbol delay adder for controlling the gain by adding the output of the multiplier for a predetermined time, and the variable symbol delay adder An orthogonal frequency division multiplex system demodulator comprising a waveform shaping circuit for generating a timing of an effective symbol from a signal of a delay adder, and performing the discrete Fourier transform based on an output signal of the previous period waveform shaping circuit. 2. The variable sample delay adder according to claim 1, further comprising a sample delayer for delaying in units of samples, a plurality of sample delayers being cascade-connected, and an adder for adding respective outputs, An enable control circuit that controls the operation of the sample delay unit by an external guard signal is provided, the addition period can be changed according to the guard interval period, the symbol synchronization signal is adaptively generated, and the billing is based on this signal. The orthogonal frequency division multiplexing system demodulator according to claim 1, wherein the discrete Fourier transform according to claim 1 is performed. 3. The variable symbol delay adding means according to claim 1, further comprising a variable symbol delay device that delays by a period obtained by adding an effective symbol period and a guard period, and an absolute value circuit that takes an absolute value of an input signal. A plurality of delay devices are connected in cascade, and an adder is provided for adding the respective outputs, and an addition period control unit capable of changing the addition period according to the position determination state and the operation start state of the effective symbol is provided. Is provided with a gain control circuit for controlling gain by a control signal from the outside and a third multiplier for performing multiplication, and the discrete Fourier transform is performed based on an output signal of the third multiplier. An orthogonal frequency division multiplex system demodulator as described. 4. An effective symbol delay device for delaying the in-phase signal and the quadrature signal according to claim 1 by an effective symbol period, and a first multiplier for multiplying the quadrature signal and the in-phase signal respectively. A variable sample delay adder for performing sample delay addition on the result multiplied by the first multiplier, and multiplying the value of the signal obtained by the variable sample delay adder with the signal from the coefficient generator, A holding circuit, comprising: a multiplier; the second multiplier according to claim 1; and an arithmetic processing unit that performs arithmetic operation of an output signal of the second multiplier, and a hold circuit that holds an output of the arithmetic processing unit at a predetermined timing. , Equipped with a variable symbol delay adder that adds the hold circuit output only for a predetermined period, and uses the output of the variable symbol delay adder as a frequency error signal to control the frequency oscillator for quadrature demodulation An orthogonal frequency division multiplex system demodulator according to claim 1, wherein: 5. A variable symbol delay adder for adding the output of the hold circuit according to claim 4 for a predetermined period, comprising a symbol delay device for delaying for a period obtained by adding an effective symbol period and a guard period, wherein the symbol delay device comprises: A gain that controls a gain based on the control signal, includes a plurality of cascade-connected adders that add respective outputs, and an enable control circuit that controls an operation state of the symbol delay unit according to a control signal from the outside. 5. The orthogonal frequency division multiplexing system demodulator according to claim 4, further comprising a control circuit, wherein the multiplier output is multiplied based on a signal from the gain control circuit. 6. A reference signal separation circuit for separating the reference signal inserted at the time of transmission from the output of the Fourier transform unit according to claim 1, and a reference signal generator for generating the same reference signal as the transmission side, A variable symbol delay adder for adding the output signals of the correlator, and a variable symbol delay adder for correlating the signal separated by the reference signal separation circuit and the reference signal generated by the reference signal generator. 2. The orthogonal frequency division multiplexing system demodulator according to claim 1, wherein the frequency oscillator for orthogonal demodulation is controlled by the output of the delay adder. 7. An adder for adding the frequency error signal output from the variable symbol delay adder according to claim 4 and the frequency error signal output from the variable symbol delay adder according to claim 6, each variable symbol delay being provided. 7. The quadrature frequency according to claim 4 or 6, wherein the addition amount and gain of the adder can be controlled separately and the output of the adder is used as a frequency error signal to control the frequency oscillator for quadrature demodulation. Division multiplex demodulator.