JPH10322210A - A/d converting circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow the A/D converter circuit consisting of a voltage mode circuit to convert an externally received voltage between an input lower limit voltage and an input upper limit voltage into digital data in a prescribed bit number and to prevent an unstable operation. SOLUTION: A threshold level circuit (Th3-Th0) corresponds to each bit of a digital signal and consists of a weighting circuit comprising a capacitor connection, an inverter (INV31-01), a bistable circuit (B3-0) consisting of a series circuit of inverters having a different threshold level, and an output inverter (INV34-04) In each threshold level circuit, an analog input voltage Vin, the input upper limit voltage LEVEL1, the input lower limit voltage LEVEL2, and the LEVEL1 or 2 selected by an output of the threshold level corresponding to high-order bits are summed with a prescribed weight. Since an output of the higher order threshold level circuit is given to a lower order threshold level circuit via a bistable circuit, the operation of the A/D converter is made stable.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog-to-digital converter, and more particularly to an analog-to-digital converter comprising a voltage mode circuit.

[0002]

2. Description of the Related Art Conventionally, an analog / digital conversion circuit (A /
As a D conversion circuit, a circuit using a voltage divider using a series resistor is widely used. However, such an A
The / D conversion circuit has a problem that power consumption increases because current always flows.

[0003] The applicants have proposed an A / D conversion circuit constituted by a voltage mode circuit (Japanese Patent Application No. 07-263574). In this A / D converter circuit, a plurality of threshold circuits are provided in parallel, an analog input voltage is applied to the plurality of threshold circuits, and the output of the threshold circuit on the side corresponding to the upper bit is lower. It is connected so as to be input with a predetermined weight to a threshold circuit on the bit side, and has high accuracy and can realize low power consumption.

FIG. 6 is a block diagram showing a configuration of a first example (quantization circuit) of the proposed A / D conversion circuit. The A / D conversion circuit can convert an input voltage into digital data of an arbitrary number of bits. Here, a case of converting the input voltage into 4-bit digital data will be described as an example. As shown in this figure, in this case, four threshold circuits Th3 to Th0 corresponding to each bit of the output digital data are provided. As shown in the figure, each of the threshold circuits Th3 to Th0 is provided with a capacitive coupling composed of a plurality of capacitances and four MOS inverters INVi1 to iVi (i = 0 to 3). Each of the threshold circuits Th3 to Th0
First stage MOS inverter INVi1 (i = 0-3)
Is the voltage Vdd when the power supply voltage is Vdd, respectively.
/ 2 is set as a threshold value, and when the input voltage is smaller than Vdd / 2, it outputs Vdd, and when the input voltage is Vdd / 2 or more, it operates to output the ground voltage GND (0). ing.

[0005] Each threshold circuit is provided with four MOS inverters in series. In principle, however, the output voltage of the capacitive coupling is a voltage higher than a predetermined threshold. , And a final-stage MOS inverter for inverting the output of the first-stage MOS inverter to output data by inverting the output of the first-stage MOS inverter. The reason why MOS inverters are provided in series in three stages before is to increase the number of inverters to increase the inversion speed and realize high-speed conversion.

Output voltages Vb3 to Vb0 are output from the threshold circuits Th3 to Th0, respectively.
Further, the intermediate output V is output from the third-stage inverter INVi3.
b3 ′ to Vb0 ′ are output. Further, AIN is an analog voltage input terminal, Vdd is a power supply voltage, and GND is a ground voltage.

A threshold circuit Th3 corresponding to the third bit (the most significant bit in this case) has a weighting circuit constituted by capacitive coupling having input capacitances C31, C32 and C33, and an output of the weighting circuit. And four stages of MOS inverters INV31 to INV34 connected in series, and the input capacitance C31 is connected to the analog voltage input terminal AI.
N from the input capacitance C
The power supply voltage Vdd is input to 32, and the ground voltage GND is input to the input capacitance C33. As described below, these input voltages are
The addition is performed with a predetermined weight given by the capacitive coupling.

The threshold circuit T corresponding to the second bit
h2 is a weighting circuit constituted by capacitive coupling having input capacitances C21, C22, C23 and C24 and a four-stage MOS inverter I connected in series.
The analog input voltage Vin is input to an input capacitance C21, the power supply voltage Vdd is input to an input capacitance C22, and the ground voltage GND is input to an input capacitance C23. The input capacitance C24 is connected to the third-stage inverter INV33 of the threshold circuit Th3.
Output Vb3 ′ is input.

The threshold circuit T corresponding to the first bit
h1 is the input capacitance C11, C12, C13,
It has a weighting circuit constituted by capacitive coupling having C14 and C15, and four stages of inverters INV11 to INV14 connected in series, the input capacitance C11 being the analog input voltage Vin, and the input capacitance C12 being the power supply. The ground voltage GND is input to the voltage Vdd and the input capacitance C13. The input capacitance C15 is connected to the third-stage inverter INV33 of the threshold circuit Th3.
Output Vb3 'is input and the input capacitance C14
Is supplied with the output Vb2 'of the inverter INV23 of the threshold circuit Th2.

The threshold circuit Th0 corresponding to the least significant bit includes input capacitances C01, C02, C0.
3, a weighting circuit constituted by capacitive coupling having C04, C05 and C06, and four stages of inverters INV01 to INV04 connected in series, and the input capacitance C01 has the analog input voltage Vi.
n, and the input capacitance C02 is the power supply voltage Vd.
d, the input capacitance C03 is connected to the ground voltage GND.
Are entered. The input capacitance C06 has the output Vb3 'of the third-stage inverter INV33 of the threshold circuit Th3, and the input capacitance C05 has the output Vb2' of the third-stage inverter INV23 of the threshold circuit Th2. The output Vb1 'of the third inverter INV13 of the threshold circuit Th1 is input to the input capacitance C04.

Note that the input capacitances C31 to C33, C21 to C24, C11 to C in the respective capacitive couplings.
The capacity ratio of C15 to C06 is set as shown in the table of FIG. Here, Cu is a unit capacity. Taking the threshold circuit Th0 corresponding to the least significant bit as an example, the power supply voltage Vdd and the ground voltage G
The threshold circuit T having a capacity for ND of 1 or 1 bit higher
The capacity corresponding to the intermediate output Vb1 'of h1 is 2, the capacity corresponding to the intermediate output Vb2' of the 2-bit higher threshold circuit Th2 is 4 (= 2 ² ), and the 3-bit upper threshold circuit T is
The capacity corresponding to the intermediate output Vb3 ′ of h3 is 8 (=
2 ³ ), the capacitance corresponding to the analog input voltage Vin is 16 (= 2 ⁴ ). As described above, in the weighting circuit constituted by the respective capacitive couplings, the intermediate output of the upper threshold circuit and the analog input voltage are added with a weight corresponding to a power of 2 in accordance with the capacitance ratio of the input capacitance. The Rukoto.

The output voltage of this capacitive coupling will be described with reference to FIG. FIG. 8 is a diagram showing an example of capacitive coupling. Here, five input capacitances C1 to C5 are provided, and the electric charge stored in each of the input capacitances C1 to C5 is 0 in an initial state. And Even when the input voltages V1 to V5 are respectively applied to the input capacitances C1 to C5, the total amount of electric charge accumulated in each of the capacitances with respect to the output terminal is 0, so that the following equation (1) holds. . Here, Vo is the output voltage of the output terminal.

(Equation 1)

Therefore, the output voltage Vo is expressed by the following equation (2).

(Equation 2) As described above, the output voltage of the capacitive coupling is a value obtained by adding each input voltage by adding a weight corresponding to the capacitance of the input capacitance.

As shown in FIG. 7, in the threshold circuit Th3, the input capacitances C31 to C3
The capacity ratio of No. 3 is C31: C32: C33 = 16: 8: 8. Therefore, the output voltage V3 of this capacitive coupling
Is as shown in the following equation (3).

(Equation 3)

Thus, when the analog input voltage Vin becomes V
When in = (1/2) Vdd, V3 is the inverter IN
The threshold voltage of V31 becomes Vth3 = (1/2) Vdd. Therefore, when 0 ≦ Vin <(１ ／) Vdd, the output of the MOS inverter INV31, that is, the intermediate output Vb3 ′ becomes Vdd, and the inverter INV34.
Output Vb3 becomes zero. Also, (1/2) Vdd ≦ V
When in <Vdd, the inverter INV31 is inverted,
The intermediate output Vb3 'is 0, and the output Vb3 is Vdd.

In the threshold circuit Th2, as shown in FIG. 7, the capacitance ratio of the input capacitances C21 to C24 is C21: C22: C23: C.
24 = 16: 4: 4: 8. Therefore, from the above equation (2), the output voltage V2 of this capacitive coupling is as shown in the following equation (4).

(Equation 4)

Here, as described above, Vb3 'is 0
Vb3 '= Vdd when ≤Vin <(1/2) Vdd
And the following equation (5) is established.

(Equation 5) When (1/2) Vdd ≦ Vin <Vdd, Vb
3 ′ = 0, and the following equation (6) is established.

(Equation 6)

Therefore, the above equations (5) and (6)
Thus, Vin = (1/4) Vdd and Vin = (3 /
4) When Vdd, V2 = (1/2) Vdd (INV
21 <threshold voltage), and 0 ≦ Vin <(１ ／)
Vdd and (1/2) Vdd ≦ Vin <
When (3/4) Vdd, the output of the inverter INV21, that is, the intermediate output Vb2 'is Vdd, and the output Vb2 is 0.
Becomes Also, (１ ／) Vdd ≦ Vin <(１ ／)
Vdd and (3/4) Vdd ≦ Vin <V
At the time of dd, the output of the inverter INV2 and the intermediate output Vb2 'become 0, and the output Vb2 becomes Vdd.

Similarly, the output voltage V1 of the capacitive coupling in the threshold circuit Th1 is expressed by the following equation (7).

(Equation 7) Thus, as in the case described above, 0 ≦ Vin <(1
/ 8) Vdd, (1/4) Vdd ≦ Vin <(3/8)
Vdd, (1/2) Vdd ≦ Vin <(5/8) Vdd
When (3/4) Vdd ≦ Vin <(7/8) Vdd, the output of the inverter INV11, that is, the intermediate output Vb1 ′ becomes Vdd, and the output Vb1 becomes 0. Also, (１ ／) Vdd ≦ Vin <(２) Vdd,
(3/8) Vdd ≦ Vin <(1/2) Vdd, (5 /
8) Vdd ≦ Vin <(3/4) Vdd and (7 /
8) When Vdd ≦ Vin <Vdd, the INV11 and the intermediate output Vb1 ′ become 0, and the output VB1 becomes Vdd.

The output voltage V0 of the capacitive coupling in the threshold circuit Th0 is expressed by the following equation (8).

(Equation 8) Thereby, similarly, 0 ≦ Vin <(1/16) V
dd, (1/8) Vdd ≦ Vin <(3/16) Vd
d, (１ ／) Vdd ≦ Vin <(5/16) Vdd,
(3/8) Vdd ≦ Vin <(7/16) Vdd, (1
/ 2) Vdd ≦ Vin <(9/16) Vdd, (5 /
8) Vdd ≦ Vin <(11/16) Vdd, (3 /
4) Vdd ≦ Vin <(13/16) Vdd and (7)
/ 8) When Vdd ≦ Vin <(15/16) Vdd, the output of the inverter INV01, that is, the intermediate output Vb
0 ′ becomes Vdd, and the output Vb0 becomes 0.

Also, (1/16) Vdd ≦ Vin <(1
/ 8) Vdd, (3/16) Vdd ≦ Vin <(1 /
4) Vdd, (5/16) Vdd ≦ Vin <(3/8)
Vdd, (7/16) Vdd ≦ Vin <(1/2) Vd
d, (9/16) Vdd ≦ Vin <(5/8) Vdd,
(11/16) Vdd ≦ Vin <(3/4) Vdd,
When (13/16) Vdd ≦ Vin <(7/8) Vdd and (15/16) VddVin <Vdd, the output of the inverter INV01, that is, the intermediate output Vb0 ′ is 0.
, And the output Vb0 becomes Vdd.

The above operation is summarized in the table of FIG.
As shown in the table, an output obtained by converting the input analog signal voltage into 4-bit digital data of d0 to d3 can be obtained from the output terminal of each threshold circuit.

In such a voltage mode circuit, a residual charge is accumulated in each input capacitance and inverter, whereby accurate weighted addition cannot be performed, and the accuracy of A / D conversion may be deteriorated. . Therefore, although not shown, in the proposed A / D conversion circuit, the first stage in each of the threshold circuits,
A switch for short-circuiting the input side and the output side of the third and fourth stage inverters is provided, these switches are turned on, and a reference voltage V is applied to each input capacitance.
By applying ref, refresh is performed by eliminating residual charges.

Next, a second example of the proposed A / D conversion circuit will be described. This A / D conversion circuit is the A / D conversion circuit (quantization circuit) of the first example shown in FIG.
Are used to obtain a digital output with higher precision. FIG. 10 is a block diagram showing a configuration of the analog-to-digital conversion circuit. In this figure, INV1 and INV2 are inverting amplifiers. The inverting amplifiers INV1 and INV2 are connected to the CM
The CMOS inverter is used as an amplifier by utilizing a portion where the output of the OS inverter transitions from a high level to a low level or from a low level to a high level, and is connected in series in an odd number of stages (for example, three stages). C
It is composed of a MOS inverter.

An input capacitance C1 is inserted between the input side of the first inverting amplifier INV1 and the analog voltage input terminal, and the output side and the input side of the first inverting amplifier INV1 are inserted. Is connected to the feedback capacitance Cf1. Further, the output side of the inverting amplifier INV1 and the second inverting amplifier IV1
A capacitance C2 is connected between the input side of NV2 and a feedback capacitance Cf2 is connected between the output side and the input side of the second inverting amplifier INV2.

The inverting amplifiers INV1 and INV1
2 is connected to refresh switches Sr11 and Sr12 for short-circuiting the input and output. These switches Sr11 and Sr12 are controlled by a refresh signal REF, and are made conductive when the refresh signal REF is at a high level.

Further, MUX11, MUX12 and MU
X13 is a multiplexer to which the refresh signal REF is applied as a control signal. When the refresh signal REF is at a low level, the multiplexer MUX11 is connected to the analog voltage input terminal VIN.
To the input capacitance C1, the multiplexer MUX12 selects the analog voltage input terminal VIN and connects it to the first quantization circuit Q1, and the multiplexer MUX13 connects to the second inverting amplifier IN.
The output of V2 is connected to a second quantization circuit Q2. When the refresh signal REF is at a high level, the multiplexer MUX11 outputs the reference voltage Vref1 of the inverting amplifiers INV1 and INV2.
And the multiplexers MUX12 and MUX
13 is a reference voltage Vr of the first and second quantization circuits.
ef is selected.

Q1 and Q2 are A / Q shown in FIG.
D conversion circuit (quantization circuit), and a first quantization circuit Q
1 is connected to the analog input voltage Vin. As described above, from the first quantization circuit Q1,
Four outputs Vb3 corresponding to 4-bit digital data
To Vb0, and these outputs are connected to the input side of the second inverting amplifier INV2 via capacitive coupling composed of the corresponding capacitances Cb3 to Cb0. The input of the second quantization circuit Q2 is connected to the output of the second inverting amplifier INV2 via a multiplexer MUX13, and a 4-bit digital signal is output from the second quantization circuit Q2. Outputs Va3 to Va0 corresponding to the data are output.

Here, first, the refresh signal RE
It is assumed that F is at a low level. As described above, the inverting amplifiers INV1 and INV2 have three stages of Cs.
It has a large gain given by the product of the open gains of the MOS inverters, and its input-side potential is a substantially constant voltage. Normally, in order to maximize the dynamic range, the voltage on the input side of each of the inverting amplifiers INV1 and INV2 is set to Vdd / 2.

Accordingly, the same charge conservation law as described above holds, and the inverting amplifier INV1 has its input capacitance C1 and feedback capacitance Cf1.
The output voltage Vo1 given by the ratio is generated with good linear characteristics. The output voltage Vo1 is expressed by the following equation (9), where Vin1 is the voltage on the input side of the inverting amplifier INV1.

(Equation 9)

The output of the inverting amplifier INV1 is input to the inverting amplifier INV2 via the capacitance C2, and the inverting amplifier INV2 receives the output of the capacitance Cb3.
The output of the first quantization circuit Q1 is input via a capacitive coupling consisting of .about.Cb0. The voltage on the input side of this second inverting amplifier INV2 is Vin2 and the voltage on the output side is V2.
Assuming o2, the relationship shown in the following equation (10) is established.

(Equation 10)

Here, as described above, Vin2 = Vd
d / 2. It is assumed that the ratio of the capacitance in each of the capacitances is set as shown in the following equation (11).

[Equation 11]

Therefore, the second inverting amplifier INV
The output voltage Vo2 of Equation (2) is obtained by the equation (10) and the equation (1).
From 1), the following equation (12) is obtained.

(Equation 12) As shown in the equation (12), the second inverting amplifier I
The output voltage Vo2 of NV2 is equal to the value of the first quantization circuit Q1.
Is converted to 4-bit digital data, and is subtracted from the input voltage Vin.

The output voltage Vo2 is input to the second quantization circuit Q2, and is converted into 4-bit digital data Va3 to Va0 in the second quantization circuit Q2 in the same manner as described above. . The 4-bit digital data Va3 to Va0 correspond to the lower 4 bits when the input voltage Vin is converted into 8-bit digital data. The 4-bit outputs Vb3 to Vb0 from the first quantization circuit Q1 correspond to the upper 4 bits of the A / D conversion output.

When the refresh signal REF is at a high level, the multiplexers MUX11-MUX
X13 is controlled to select either the reference voltage Vref1 or the reference voltage Vref. The refresh switches Sr11 and Sr12 are turned on. Therefore, it is possible to eliminate the residual charges accumulated in the respective capacitances and the inverting amplifiers. In this way, the input analog voltage can be A / D converted to 8-bit digital data with high accuracy.

[0036]

As described above, according to the A / D conversion circuit constituted by the proposed voltage mode circuit, low power consumption and high precision analog-to-digital conversion can be realized. But the power supply potential Vdd
From the ground potential GND to k-bit digital data. Therefore, the change width of the input voltage (the difference between the input lower limit voltage and the input upper limit voltage) is equal to the power supply potential Vd.
When d is smaller than the width of the ground potential GND, the resolution is low.

In the A / D conversion circuit, when the input voltage is near a predetermined value, the operation sometimes becomes unstable. FIG. 11 shows the A / D shown in FIG.
4 shows an example of an output of a conversion circuit. In this figure, (a)
Is a diagram showing an output of the threshold circuit Th3 corresponding to the most significant bit, and the broken line is the input voltage. (B) shows the threshold circuit Th
2, (c) is the output of the threshold circuit Th1,
(D) shows the output of the threshold circuit Th0. As shown in this figure, when the value of the input voltage Vin is near a predetermined value, it can be seen that the outputs of the threshold circuits are in an unstable state.

This is because each of the threshold circuits Th3 to Th
0, the threshold values of the plurality of CMOS inverters connected in series are the same (Vdd / 2)
Therefore, when the output of any one of the capacitive coupling circuits is near the threshold, the operation of the subsequent inverter becomes unstable, and this also affects the threshold circuit of the lower bit. This is because the entire output is unstable. There is also a disadvantage that the output is similarly unstable due to noise included in the input.

Therefore, the present invention provides an A / D conversion circuit constituted by the above-described voltage mode circuit, wherein the input lower limit voltage and the input upper limit voltage can be set from outside the A / D conversion circuit, It is an object of the present invention to provide an A / D conversion circuit with high resolution capable of converting a voltage between the set input lower limit voltage and the set input upper limit voltage into digital data of a predetermined number of bits. It is another object of the present invention to prevent an output from becoming unstable in an A / D conversion circuit constituted by a voltage mode circuit. Further, in the A / D conversion circuit in which the output voltage is prevented from becoming unstable, in order to guarantee a highly accurate conversion operation, residual charges accumulated in each capacitance and the like are eliminated, and the It is intended to be able to perform precision conversion. Still another object of the present invention is to further reduce power consumption in an A / D conversion circuit that prevents the output voltage from becoming unstable.

[0040]

In order to achieve the above object, an analog-to-digital converter according to the present invention is an analog-to-digital converter for converting an analog input voltage into k-bit (k is an integer) digital data. , And k threshold circuits provided corresponding to each bit of the digital data, and a weighting circuit provided at a preceding stage of each of the threshold circuits. The circuit outputs a high-level signal when the output voltage of the corresponding weighting circuit is lower than a predetermined threshold, and outputs a low-level signal when the output voltage is higher than the predetermined threshold. Wherein each of the weighting circuits is configured to output the analog input voltage, a first voltage corresponding to an input lower limit voltage, and a second voltage corresponding to an input upper limit voltage. And the first or second voltage selected corresponding to an output of the threshold circuit corresponding to a bit higher than the threshold circuit is input to one terminal, and the other terminal is The first capacitor is configured by capacitive coupling composed of a plurality of capacitors connected in common;
And the weight for the second voltage and the second voltage is 1, the nth bit (n is an integer) higher than the threshold circuit is selected by the output of the threshold circuit corresponding to a bit higher than the threshold voltage by n bits (n is an integer). The weight for the first or second voltage is 2
ⁿ , and when the weight for the output of the threshold circuit corresponding to the most significant bit is 2 ^m , the weight for the analog input voltage is 2 ^{(m + 1)} , and the respective input voltages are added. It is characterized by having.

The output of each of the threshold circuits is supplied to each of the threshold circuits corresponding to the lower bits via a bistable circuit configured to output the same state as the output. Is what is being done. The bistable circuit is constituted by an even-numbered inverter having an even different threshold value, an even-numbered Schmitt trigger circuit, or at least one inverter and one Schmitt trigger circuit connected in series. is there.

Further, a switch means connected between the input and output of an inverter connected to the output of the capacitive coupling of the weighting circuit in each of the threshold circuits, and each capacitance of the weighting circuit is connected to each of the input voltages. A switching means for supplying a reference voltage instead, wherein the switching means is closed and the switching means applies a reference voltage to each of the capacitors to eliminate the residual charge. is there.

Further, there is provided switch means for connecting the input side of the inverter in each of the threshold circuits to a ground potential or a power supply potential. It is something which is made to be.

Still another analog-to-digital conversion circuit according to the present invention includes a first input capacitance to which an analog input voltage is input, and a first input capacitor having a linear characteristic connected to an output of the first input capacitance. An inverting amplifier, a first quantizing circuit that receives the analog input voltage and outputs a quantized output of the analog input voltage, and an output of the first inverting amplifier and an output of the first quantizing circuit. A second inverting amplifier having a linear characteristic to which the output of the capacitive coupling is input, and an output of the second inverting amplifier is input, and the output of the second inverting amplifier is quantized. An analog-to-digital conversion circuit comprising a second quantization circuit, wherein the first and second quantization circuits are the aforementioned analog-to-digital conversion circuits, and Switching means for inputting a first voltage corresponding to an input lower limit when the output of the first quantization circuit is at a low level, and selecting and inputting a second voltage corresponding to an input upper limit when the output of the first quantization circuit is at a high level , The output of the first quantization circuit is input.

[0045]

FIG. 1 is a block diagram showing a configuration of an A / D conversion circuit according to a first embodiment of the present invention. The embodiment shown in this figure corresponds to the A / D conversion circuit (quantization circuit) shown in FIG. In this figure, the same components as those in FIG. 6 are denoted by the same reference numerals to avoid duplication of description. Further, the capacitance of each input capacitance is set to the value shown in the table of FIG. 7 as in the case of FIG. 6 described above.

As shown in FIG. 1, A /
The D conversion circuit has, as input terminals, an analog voltage input terminal AIN, a reference voltage Vref input terminal, a terminal for inputting a first level voltage LEVEL1, and a second level voltage L
It has four input terminals for inputting EVENT2, and an analog voltage input terminal AIN receives an input voltage Vin.
Is entered. Here, the reference voltage Vref is Vre
f = Vdd / 2, the first level voltage LEVEL1 is a voltage corresponding to the upper limit of the input voltage, and the second level voltage LEVEL2 is a voltage corresponding to the lower limit of the input voltage. For example, when the full range of the input voltage is 0 to Vdd, the first level voltage L
EVEL1 = Vdd, the voltage LEVEL of the second level
L2 = GND = 0, and the state is the same as the case described above. As described above, in the present invention, the first level voltage LEVEL1 corresponding to the upper limit of the input voltage and the second level voltage LEVEL2 corresponding to the lower limit of the input voltage are externally supplied. .

MUX1 to MUX3 are voltages, Vin, Vref, and LEVEL input from the input terminals.
A multiplexer for applying L1 and LEVEL2 to each threshold circuit. The multiplexers MUX1 to MUX1
MUX3 has a sleep signal SLEE as a control signal.
A signal of the logical sum of P and the refresh signal REF is applied.

Th3 to Th0 are the threshold circuits described above, and in this embodiment, each has four inverters as in the case of FIG. Here, the inverter INVi1 (i = 3 to 0) at the first stage of each of the threshold circuits Th3 to Th0 is connected to V
It has a threshold of dd / 2. Also, the third-stage inverter INVi3 (i = 3) indicated by hatching in the drawing.
To 0) are the inverters INVi1 and INVi2 of the other stages.
And INVi4 (i = 3 to 0) have different threshold values. It is also desirable that the second-stage inverter INVi2 (i = 3 to 0) has a different threshold value from that of the first-stage inverter INVi1 (i = 3 to 0).

Thus, a series circuit of the inverters INV32 and INV33 having different threshold values from each other, INV
22 and INV23, INV12 and INV13
And the series circuit of INV02 and INV03 constitute bistable circuits B3 to B0 having two stable output states, respectively. By using a series circuit of inverters having such different threshold values,
It is possible to prevent the output voltage from oscillating at the specific input voltage as described above.

Each of the threshold circuits Th3 to Th0
First stage inverters INV31, INV21, INV
Switches Ss3, Ss2, Ss1 and Ss0 for sleep are respectively connected to the input sides of 11 and INV01, and the other ends of the switches Ss3 to Ss0 are connected to the reference voltage Vref. Each of the switches Ss3 to Ss0 has a sleep signal SL as a control signal.
EEP is applied, and the sleep signal SLEEP
Is set to a high level, the sleep switches Ss3 to Ss0 are turned on.
At the same time, a ground voltage GND is applied to the reference voltage input terminal Vref instead of the reference voltage Vref.

The first-stage inverters INV31 to INV01 of the threshold circuits Th3 to Th0 are provided with refresh switches Sr3 to Sr0 for short-circuiting the input and output sides, respectively. The refresh switches Sr3 to Sr0 are supplied with the refresh signal REF as a control signal, and are turned on when the refresh signal REF is at a high level.

The threshold circuits Th2 to Th0 other than the threshold circuit Th3 corresponding to the most significant bit (in this case, the third bit) respectively have the threshold circuits Th3 to Th1 of the upper bit. Are applied as control signals to the corresponding multiplexers MUX4 to MUX6.

As in the case of the above-described prior art, the intermediate outputs of the upper-bit threshold circuits Th3, Th2 and Th1 are input to the lower-bit threshold circuits Th2 to Th0, respectively, and subjected to A / D conversion. However, in the A / D conversion circuit of the present invention, each of the multiplexers MUX4 to MUX4 to use the intermediate output as a control signal instead of directly inputting each intermediate output to the threshold circuit of the lower bit.
The first level voltage LEVEL1 and the second level voltage LEVEL2 supplied from an external circuit are input to the lower threshold circuit via the MUX 6.

In a normal operation in which the refresh signal REF and the sleep signal SLEEP are both at a low level, the MUX 4 uses the intermediate output of the threshold circuit Th3 of the most significant bit as a control signal and outputs the L signal.
LEVEL1 and LEVEL2 are switched and applied to the lower threshold circuits Th2 to Th0. That is, when the Th3 intermediate output Vb3 'is at Vdd (high level), the multiplexer MUX4 outputs the LEVEL signal.
L1 is controlled to be selected, and a first level voltage LEVEL1 supplied from an external circuit is applied to the input capacitances C24, C15 and C06. On the other hand, the intermediate output Vb3 'of Th3 is 0 (low level).
, The multiplexer MUX4 sets the L
LEVEL2 is controlled to select the second level voltage LEVEL2.
4, applied to C15 and C06.

Similarly, the multiplexer MUX
Reference numeral 5 switches between LEVEL1 and LEVEL2 in accordance with the intermediate output of the second-bit threshold circuit Th2 and applies it to the lower-order threshold circuits Th1 and Th0. Further, the multiplexer MUX6 applies the corresponding voltages LEVEL1 and LEVEL2 to the threshold circuit Th0 according to the intermediate output of the threshold circuit Th1 of the first bit.

The A / D conversion operation in the A / D conversion circuit of the present invention thus configured will be described. As described above, the capacitance ratio of each of the input capacitances C01 to C33 is the capacitance ratio shown in FIG.
C32: C33 = 16: 8: 8. Therefore, the output voltage of the capacitive coupling composed of the capacitances C31 to C33 in the threshold circuit Th3 corresponding to the third bit, that is, the input voltage V of the inverter INV31.
3 is expressed by the following equation (13) in the same manner as in the case described above. Here, Vin is an analog voltage input terminal AI
Input voltage from N, LV1 = LEVEL1, LV2 = L
EVENT2.

(Equation 13)

Also, C21: C22: C23: C24 =
16: 4: 4: 8, the capacitances C21 to C21 in the threshold circuit Th2 corresponding to the second bit
The output voltage of the capacitive coupling composed of C24, that is, the input voltage V2 of the inverter INV21 is expressed by the following equation (14). Here, Vd3 is the output of the multiplexer MUX4, and the threshold circuit T corresponding to the third bit is used.
The intermediate output Vb3 ′ output from the bistable circuit B3 of h3
Is high level, Vd3 = LV1, and Vb3
Is low level, Vd3 = LV2.

[Equation 14]

Further, similarly, the inverter IN
The input voltage V1 of V11 and the input voltage V0 of the inverter INV01 are expressed by the following equations (15) and (1), respectively.
6). Here, Vd2 and Vd1 are:
The multiplexers MUX5 and MUX6 respectively
Is the output of

(Equation 15)

(Equation 16)

Here, the threshold value of the first-stage inverter INV31 of the threshold circuit Th3 for the most significant bit is Vd.
d / 2, and from the equation (13), this inverter I
Regarding the input voltage Vin when the NV 31 is inverted,
The following equation (17) holds.

[Equation 17] Therefore, the inverter INV31 inverts when the input voltage Vin is a voltage represented by the following equation (18). This input voltage Vin is assumed to be A7.

(Equation 18)

Therefore, when the input voltage Vin is (Vdd-
LV1) When ≤Vin <A7, the inverter INV
The output Vb3 'of the signal 31 becomes high level, and the first input voltage LEVEL1 is selected and output from the multiplexer MUX4. Also, A7 ≦ Vin <(Vdd−
In the case of LV2), the output Vb3 'of the INV31 becomes low level, and the second input voltage LEVEL2 is selected from the multiplexer MUX4.

Next, the second-bit threshold circuit Th
The input voltage Vin when the second inverter INV21 of the second stage is inverted is as follows. First, (Vdd-LV
1) When ≤Vin <A7, the multiplexer M
LEVEL1 is output from UX4 and applied to input capacitance C24. Therefore, the following expression (19) is established from the expression (14).

[Equation 19] As a result, the inverter INV21 outputs the input voltage Vin.
Is inverted when the voltage is expressed by the following equation (20), and this input voltage is defined as A3.

(Equation 20)

A7 ≦ Vin <(Vdd−LV2)
, The multiplexor MUX4 outputs the LEVEL
2 is selected and output. Therefore, the above equation (1)
From 4), the following equation (21) holds.

(Equation 21) According to the equation (21), the inverter INV21 inverts when the input voltage Vin is the voltage shown in the following equation (22). This input voltage is assumed to be A11.

(Equation 22)

That is, the output Vb2 'of the inverter INV21 of the threshold circuit Th2 corresponding to the second bit.
Is that the input voltage Vin is (Vdd-LV1) ≦ Vin <A
3 and when A7 ≦ Vin <A11, the multiplexer MUX5 selects and outputs the first level voltage LEVEL1. On the other hand, A3 ≦ V
in <A7 and A11 <Vin ≦ (Vdd-LV2)
, And the multiplexer MUX5 outputs the second-level voltage LEVEL2.

Next, the input voltage Vin when the inverter INV11 of the threshold circuit Th1 corresponding to the first bit is inverted is as follows. First, when Vin <A3, the intermediate output Vb3 'of the threshold circuit Th3 corresponding to the third bit goes high, and the intermediate output Vb2' of the threshold circuit Th2 corresponding to the second bit goes high. , Each of the multiplexers MUX4 and MUX5 outputs a first voltage LEVEL1, and Vd3 = LV1
And Vd2 = LV1. Therefore, the above equation (1)
From 5), the following equation (23) holds.

(Equation 23) Therefore, from the equation (23), the inverter INV1
1 is inverted when the input voltage Vin is a voltage represented by the following equation (24). This input voltage is assumed to be A1.

(Equation 24)

Next, when A3 ≦ Vin <A7, the intermediate output Vb3 ′ of the threshold circuit Th3 is at a high level,
The intermediate output Vb2 'of the threshold circuit Th2 goes low. Therefore, the output Vd3 of the multiplexer MUX4 = LV1 and the output Vd2 of the multiplexer MUX5 = LV2, and the following equation (25) is established from the above equation (15).

(Equation 25) From this equation (25), the inverter INV11 inverts when the input voltage Vin is the voltage shown in the following equation (26). This input voltage is defined as A5.

(Equation 26)

Further, when A7 ≦ Vin <A11,
The intermediate output Vb3 'of the threshold circuit Th3 goes low, and the intermediate output Vb2' of the threshold circuit Th2 goes high. Therefore, the multiplexer MUX
4 output Vd3 = LV2, MUX5 output Vd2 = LV
From equation (15), as in the case described above, the inverter IN at the voltage shown in the following equation (27)
V11 is inverted. This input voltage is assumed to be A9.

[Equation 27]

Further, when A11 ≦ Vin, the intermediate output Vb3 ′ of the threshold circuit Th3 is at a low level, the intermediate output Vb2 ′ of the threshold circuit Th2 is at a low level, and Vd3 = LV2 and Vd2 = LV2. Therefore, by substituting these values into equation (15), the following equation (2) is obtained in the same manner as in the above case.
The input voltage at which the inverter INV11 shown in 8) is inverted can be obtained. This voltage is defined as A13.

[Equation 28]

Similarly, the input voltage at which the inverter INV01 of the threshold circuit Th0 corresponding to the least significant bit is inverted can be calculated by using the above equation (16). Inverter INV0 calculated in this way
The input voltages A0, A2, A4, A6, A8,
A10, A12 and A14 are shown.

(Equation 29)

FIG. 2 is a chart summarizing the above operations. As shown in this table, according to the A / D conversion circuit of the present invention, the first voltage LEV corresponding to the input upper limit voltage
EL1 to a second voltage LEVEL corresponding to the input lower limit voltage
Between 2 can be converted into digital data of a predetermined number of bits (4 bits in the above embodiment).

Now, in the A / D converter of the present invention,
As described above, the first-stage inverter INVi1 (i = 3 to
By supplying the output of 0) to the threshold circuit corresponding to the lower bit via the bistable circuits B3 to B0, the occurrence of an unstable state of the output is prevented. FIG. 3 is a diagram illustrating an example of an output voltage of the A / D conversion circuit according to the embodiment of the present invention. In this figure, a) shows the output of the threshold circuit Th3 corresponding to the most significant bit, and the broken line shows the input voltage. (B) shows the output of the threshold circuit Th2;
(C) shows the output of the threshold circuit Th1, and (d) shows the output of the threshold circuit Th0. As shown in this figure, according to the A / D conversion circuit of the present invention, a stable output is obtained.

Next, the case where the refresh signal REF is set to the high level will be described. At this time, all of the multiplexers MUX1 to MUX3 are switched so as to select the reference voltage Vref, and the reference voltage Vr is applied to all the input capacitances C01 to C33.
ef will be applied. Further, the refresh switches Sr3 to Sr0 are all turned on, and the input and output of the first-stage inverters INV31 to INV01 of the threshold circuits Th3 to Th0 are short-circuited. Therefore, the input capacitance and the residual charge accumulated in the inverter can be eliminated, and accurate conversion can be performed.

Next, the case where the sleep signal SLEEP is set to the high level will be described. In this case,
As described above, the ground potential (GND) is input to the reference voltage input terminal instead of the reference voltage. Then, all of the multiplexers MUX1 to MUX3 are switched to select the reference voltage input terminal side, and the ground voltage GND is applied to all input capacitances. Further, the sleep switches Ss3 to Ss0 are turned on, and the ground voltage GND is applied to the input sides of the first-stage inverters INV31 to INV01 of the threshold circuits Th3 to Th0. Therefore, each of the inverters is in a saturated state,
Power consumption can be reduced to almost zero. Note that a power supply voltage Vdd may be applied instead of the ground voltage.

As described above, according to the A / D conversion circuit, it is possible to prevent the output from becoming unstable when the input voltage becomes close to a specific value. Further, residual charges can be effectively eliminated only by using a refresh circuit having a simple configuration. Further, when the operation is unnecessary, the sleep mode is set, so that the power consumption can be further reduced.

In the above-described embodiment, the bistable circuit is formed by connecting inverters having different threshold values in series. However, the present invention is not limited to this. FIG. 4 is a diagram showing an embodiment in which another configuration is adopted as the bistable circuit. FIG. 4A is a diagram showing an embodiment in which the bistable circuit is constituted by two Schmitt trigger circuits Sh1 and Sh2 connected in series. Thus, even when the Schmitt trigger circuit is used, a stable output can be obtained as in the case described above.

FIG. 4B is a diagram showing another example of the configuration of the bistable circuit. The example shown in this figure is for Schmidt
The bistable circuit is constituted by a series circuit of the trigger circuit Sh and the inverter INV. Also in this case, the same effect can be obtained. In FIG. 4B, the Schmitt trigger circuit Sh is at the front stage and the inverter INV is at the rear stage, but the order may be reversed. However, as shown in FIG. 4B, the effect is greater when the Schmitt trigger circuit Sh is provided in the preceding stage.

In the above description, two inverters having two different threshold values, two-stage Schmitt trigger circuit, or two serially connected Schmitt trigger circuits and an inverter are connected in series. The case where the circuit forms a bistable circuit has been described. However, the present invention is not limited to this, and it is sufficient if the circuit is an even-numbered series circuit.

Next, another embodiment of the present invention will be described with reference to FIG. This embodiment corresponds to the above-described A / D conversion circuit in FIG. 10, and the same components as those in FIG. 10 are assigned the same reference numerals to avoid duplication of description. The capacitance of each capacitance is set in the same manner as in the case of FIG.

In FIG. 5, quantization circuits Q1 and Q2
Is A / of the first embodiment of the present invention shown in FIG.
It is a D conversion circuit. Also, MUX14 to MUX17 are
Multiplexers respectively connected to the capacitances Cb3 to Cb0, and one of their input terminals has a first level voltage LEVEL corresponding to the upper limit of the input.
L1 is connected, and a second level voltage LEVEL2 corresponding to the lower limit of the input is connected to the other input terminal. Then, the output voltage Vb of the most significant bit of the first quantization circuit is applied to the multiplexer MUX14.
3 is applied as a control signal and the multiplexer M
UX15 receives the output voltage Vb2 of the second bit,
X16 is the output voltage Vb1 of the first bit, and the multiplexer MUX17 is the output voltage Vb of the 0th bit.
0 is applied as a control signal.

As described above, instead of using the output voltage of the first quantization circuit Q1 directly as the input voltage to the corresponding capacitance, the first level voltage LEVEL1 and the second level LEVEL1 applied from the external circuit are not used. Level voltage LEV
EL2 is applied to the capacitance. This makes it possible to perform A / D conversion with a full range between LEVEL1 and LEVEL2. Further, since the A / D conversion circuit of the first embodiment of the present invention shown in FIG. 1 is used as the first and second quantization circuits, the output is unstable at a specific input voltage. Can be prevented.

[0080]

As described above, according to the present invention,
In an A / D conversion circuit constituted by a voltage mode circuit, an analog input voltage between first and second voltages corresponding to a lower limit and an upper limit of an input applied from an external circuit is converted into digital data of a predetermined number of bits. It is possible to do. Further, it is possible to prevent a phenomenon that the output becomes unstable when the input voltage becomes close to a specific value, and it is possible to improve noise resistance.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an A / D conversion circuit according to a first embodiment of the present invention.

FIG. 2 is a chart for explaining an output of the A / D conversion circuit shown in FIG. 1;

FIG. 3 is a diagram illustrating an example of an output of the A / D conversion circuit illustrated in FIG. 1;

FIG. 4 is a diagram illustrating another configuration example of the bistable circuit in the A / D conversion circuit illustrated in FIG. 1;

FIG. 5 is a block diagram showing a configuration of another embodiment of the A / D conversion circuit of the present invention.

FIG. 6 is a diagram illustrating a configuration of a first example of an A / D conversion circuit configured by a proposed voltage mode circuit;

FIG. 7 is a table for explaining a capacitance ratio of an input capacitance in the A / D conversion circuit of FIG. 6;

FIG. 8 is a diagram for explaining an example of capacitive coupling.

FIG. 9 is a table for explaining an output of the A / D conversion circuit of FIG. 6;

FIG. 10 is a block diagram showing a configuration of a second example of the proposed A / D conversion circuit.

FIG. 11 is a diagram illustrating an example of an output of a proposed A / D conversion circuit.

[Description of Signs] AIN Analog voltage input terminals B, B0 to B3 bistable circuits C1 to C5, C01 to C33, Cb0 to Cb3, Cf
1, Cf2 Capacitance INV1, INV2 Inverting amplifier INV01-INV34 Inverter MUX1-MUX6, MUX11-MUX13 Multiplexer Q1, Q2 Quantizer Sh, Sh1, Sh2 Schmitt trigger Sr0-Sr3, Sr11, Sr3 Sr3 Sr3 Sr3 Sr3 Th0-Th3 threshold circuit

Continued on the front page (72) Inventor Chen Ying 3-5-18 Kitazawa, Setagaya-ku, Tokyo Takayama Building Takayamauchi Co., Ltd.

Claims (8)

[Claims] 1. An analog-to-digital conversion circuit for converting an analog input voltage into k-bit (k is an integer) digital data, wherein k threshold values are provided corresponding to each bit of the digital data. And a weighting circuit provided at a stage preceding each of the threshold circuits. The k threshold circuits each have a predetermined output voltage of the weighting circuit. When the voltage is smaller than the predetermined threshold value, a high-level signal is output. When the voltage is equal to or higher than the predetermined threshold value, a low-level signal is output. , A first voltage corresponding to an input lower limit voltage, a second voltage corresponding to an input upper limit voltage, and an output of the threshold circuit corresponding to a bit higher than the threshold circuit. The first or second voltage selected in response to is connected to one terminal, and the other terminal is formed by capacitive coupling composed of a plurality of capacitors connected in common. When the weight for the second voltage is set to 1, the second voltage selected corresponding to the output of the threshold circuit corresponding to a bit higher than the threshold circuit by n bits (n is an integer). When the weight for the first or second voltage is 2 ⁿ and the weight for the output of the threshold circuit corresponding to the most significant bit is 2 ^m , the weight for the analog input voltage is 2 ^{(m + 1)} , An analog-to-digital conversion circuit, wherein each of the input voltages is added. 2. An output of each threshold circuit is supplied to each threshold circuit corresponding to the lower bit via a bistable circuit configured to output the same state as the output. 2. The analog-to-digital conversion circuit according to claim 1, wherein the conversion is performed. 3. The analog-to-digital conversion circuit according to claim 2, wherein said bistable circuit is constituted by even-numbered inverters having different threshold values. 4. The analog-to-digital converter according to claim 2, wherein said bistable circuit is constituted by an even-numbered stage Schmitt trigger circuit. 5. The bistable circuit according to claim 2, wherein the bistable circuit is configured by connecting at least one inverter and one Schmitt trigger circuit in series.
2. The analog-to-digital conversion circuit according to item 1. 6. A switch means connected between an input and an output of an inverter connected to an output of the capacitive coupling of the weighting circuit in each of the threshold circuits, and a capacitance of each of the weighting circuits to each of the input voltages. A switching unit for supplying a reference voltage instead, and the switch unit is closed and the switching unit applies a reference voltage to each of the capacitors to eliminate the residual charge. Claim 1.
2. The analog-to-digital conversion circuit according to item 1. 7. A switch means for connecting an input side of the inverter in each of the threshold circuits to a ground potential or a power supply potential, and closing the switch means puts each of the threshold circuits into a sleep state. 2. The analog-to-digital conversion circuit according to claim 1, wherein: 8. A first input capacitance to which an analog input voltage is input, a first inverting amplifier having a linear characteristic connected to an output of the first input capacitance, and the analog input voltage; A first quantization circuit that outputs a quantized output of the analog input voltage, a capacitive coupling to which the output of the first inverting amplifier and the output of the first quantization circuit are input, and an output of the capacitive coupling And a second inverting amplifier having a linear characteristic, and a second quantizing circuit to which an output of the second inverting amplifier is input and which quantizes an output of the second inverting amplifier. 2. The digital conversion circuit, wherein the first and second quantization circuits are the analog-to-digital conversion circuit according to claim 1, wherein the output of the first quantization circuit has a low level in the capacitive coupling. 3. When the first voltage corresponding to the input lower limit is input at the time of, and the second voltage corresponding to the input upper limit is selected and input at the time of the high level, the output of the first quantization circuit is output. An analog-to-digital conversion circuit characterized in that an analog-to-digital converter is input.