JPH1032217A - Bare chip sealing method and semiconductor device manufacture by the method - Google Patents
Bare chip sealing method and semiconductor device manufacture by the methodInfo
- Publication number
- JPH1032217A JPH1032217A JP18601696A JP18601696A JPH1032217A JP H1032217 A JPH1032217 A JP H1032217A JP 18601696 A JP18601696 A JP 18601696A JP 18601696 A JP18601696 A JP 18601696A JP H1032217 A JPH1032217 A JP H1032217A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- sealing
- bare
- bank
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01039—Yttrium [Y]
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、ベアチップ封止方
法及び該方法により製造された半導体装置に関する。The present invention relates to a bare chip sealing method and a semiconductor device manufactured by the method.
【０００２】[0002]
【従来の技術】図３（ａ）は、従来例の半導体製造方法
により、プラスチック製枠を用いる工程を示す斜視図、
（ｂ）は、（ａ）の後、プラスチック製枠の内側に粘度
の低い樹脂を滴下する工程を示す斜視図である。2. Description of the Related Art FIG. 3A is a perspective view showing a step of using a plastic frame by a conventional semiconductor manufacturing method.
(B) is a perspective view showing a step of dropping a low-viscosity resin inside the plastic frame after (a).
【０００３】図３（ａ），（ｂ）に示すように、従来プ
リント基板１上にベアＩＣチップ２を樹脂封止の際に、
樹脂の拡がりを防止し、封止範囲２１，２２を限定する
ために、プリント基板上の露出パターン８（後述、図４
参照）およびベアＩＣチップ２を囲う最小サイズのプラ
スチック製枠１０をプリント基板１に接着し、その枠１
０内に粘度の低い樹脂５を滴下することにより、ＣＯＢ
（チップオンボード）の樹脂封止が行われてきた。As shown in FIGS. 3A and 3B, when a bare IC chip 2 is resin-sealed on a conventional printed circuit board 1,
In order to prevent the resin from spreading and to limit the sealing ranges 21 and 22, an exposed pattern 8 on the printed circuit board (see FIG.
) And a minimum size plastic frame 10 surrounding the bare IC chip 2 is adhered to the printed circuit board 1, and the frame 1
By dropping the low-viscosity resin 5 into the COB, COB
(Chip-on-board) resin sealing has been performed.
【０００４】[0004]
【発明が解決しようとする課題】この従来の封止範囲を
限定する方式では、多品種のベアＩＣチップに対応する
ためには、多種類のサイズの枠を製作して置く必要があ
るという問題がある。また、プラスチック製枠は、プリ
ント基板上の露出パターンに接触してはならないので、
封止範囲がプラスチック製枠の幅分だけ広くなってしま
うという問題がある。In the conventional method of limiting the sealing range, it is necessary to manufacture frames of various sizes to accommodate various types of bare IC chips. There is. Also, since the plastic frame must not touch the exposed pattern on the printed circuit board,
There is a problem that the sealing range is widened by the width of the plastic frame.
【０００５】そこで、本発明の目的は、封止用樹脂のデ
ィスペンサの軌跡を変えて、封止範囲をフレキシブルに
画成して粘度の高い樹脂と粘度の低い樹脂を使用する方
法をとることにより、プラスチック製枠を用いず、した
がって上述の欠点を解消した、ベアチップ封止方法及び
この方法による半導体装置を提供することにある。An object of the present invention is to provide a method of using a resin having a high viscosity and a resin having a low viscosity by changing the trajectory of a dispenser of a sealing resin to flexibly define a sealing range. Another object of the present invention is to provide a bare chip encapsulation method and a semiconductor device using this method, which do not use a plastic frame and therefore eliminate the above-mentioned disadvantages.
【０００６】[0006]
【課題を解決するための手段】本発明のベアチップ封止
方法は、ベアＩＣチップを基板に対し封止する方法にお
いて、封止用粘性樹脂のディスペンサを基板面にほぼ平
行なＸ軸方向及びＹ軸方向に動かしながら、粘度の高い
樹脂を、封止範囲の周囲に沿って吐出することにより土
手を形成し、形成したこの土手の内側を粘度の低い樹脂
で充填することを特徴としている。A bare chip sealing method according to the present invention is a method for sealing a bare IC chip to a substrate, wherein a dispenser of a sealing viscous resin is moved in the X-axis direction and Y direction substantially parallel to the substrate surface. A bank is formed by discharging a high-viscosity resin along the periphery of the sealing area while moving in the axial direction, and the inside of the formed bank is filled with a low-viscosity resin.
【０００７】また、本発明の半導体装置は、プリント基
板上に直接ベアＩＣチップを実装するＣＯＢ構造の半導
体装置において、樹脂封止範囲の外側と内側が粘度の異
なる樹脂により封止されていることを特徴としている。Further, in the semiconductor device of the present invention, in a semiconductor device having a COB structure in which a bare IC chip is directly mounted on a printed board, the outside and the inside of a resin sealing area are sealed with resins having different viscosities. It is characterized by.
【０００８】[0008]
【発明の実施の形態】次に、本発明の実施の形態につい
て図面を参照して説明する。Next, embodiments of the present invention will be described with reference to the drawings.
【０００９】図１（ａ）は、本発明の半導体製造方法の
一実施形態例により、粘度の高い樹脂により土手を作る
工程を示す斜視図、（ｂ）は、（ａ）の後、土手の内側
に粘度の低い樹脂を滴下する工程を示す斜視図、図２
は、図１（ｂ）の工程終了後の垂直断面図、図４は、本
実施形態例の封止範囲と従来例の封止範囲との比較を示
す図である。FIG. 1A is a perspective view showing a step of forming a bank with a resin having a high viscosity according to an embodiment of the semiconductor manufacturing method of the present invention, and FIG. FIG. 2 is a perspective view showing a step of dropping a low-viscosity resin inside.
FIG. 1B is a vertical cross-sectional view after the process of FIG. 1B is completed, and FIG. 4 is a diagram showing a comparison between the sealing range of the embodiment and the sealing range of the conventional example.
【００１０】図１において、配線パターン（不図示）が
形成されているプリント基板１に少なくとも１つのベア
ＩＣチップ２が搭載されている。この配線パターンとベ
アＩＣチップ２は、金線３により電気的に接続されてい
る。In FIG. 1, at least one bare IC chip 2 is mounted on a printed circuit board 1 on which a wiring pattern (not shown) is formed. The wiring pattern and the bare IC chip 2 are electrically connected by the gold wire 3.
【００１１】粘度の高い樹脂４を入れたディスペンサ６
は、プリント基板面１に平行な２つの方向すなわちＸ方
向およびＹ方向に動作可能なロボット７に取り付けら
れ、プリント基板上の露出パターン８（図４参照）、金
線３およびベアＩＣチップ２を含む封止範囲１１，１２
に沿って、粘度の高い樹脂４を吐出しながら動作し、封
止範囲１１，１２に沿って土手９を形成する。A dispenser 6 containing a high-viscosity resin 4
Is mounted on a robot 7 operable in two directions parallel to the printed circuit board surface 1, that is, in the X and Y directions. The exposed pattern 8 (see FIG. 4) on the printed circuit board, the gold wire 3 and the bare IC chip 2 Including sealing range 11, 12
Along with the resin 4 having a high viscosity, and the bank 9 is formed along the sealing areas 11 and 12.
【００１２】次に、粘度の低い樹脂５をこの土手９の内
側に滴下し、金線３およびベアＩＣチップ２を封止す
る。Next, a low-viscosity resin 5 is dropped inside the bank 9 to seal the gold wire 3 and the bare IC chip 2.
【００１３】図４を参照すれば、上述の封止方法が、従
来技術による封止方法に比し封止範囲を縮小することが
できる状況が判り易く示されている。すなわち、図４に
おいて、従来の方法のプラスチック製枠１０がプリント
基板上に露出しているパターン８よりも外側に配置され
なければならいのに対して、本発明の方法の土手９は、
詳しく云えばこの土手９の外側端が露出パターンの最外
部の上に配置されていればよいので、従来の封止範囲１
１，１２から本発明の封止範囲２１，２２へ、少なくと
もプラスチック製枠１０の幅分だけは縮小され得る。Referring to FIG. 4, it is easy to understand that the above-mentioned sealing method can reduce the sealing range as compared with the conventional sealing method. That is, in FIG. 4, the plastic frame 10 according to the conventional method must be arranged outside the pattern 8 exposed on the printed circuit board, whereas the bank 9 according to the method of the present invention is
More specifically, since the outer end of the bank 9 only needs to be arranged on the outermost part of the exposed pattern, the conventional sealing area 1 is used.
1, 12 to the sealing areas 21, 22 of the invention, at least the width of the plastic frame 10 can be reduced.
【００１４】[0014]
【発明の効果】以上説明したように本発明は、封止用樹
脂のディスペンサの動作する軌跡を変えることにより、
封止範囲をフレキシブルに変えることができるので、多
品種のベアＩＣチップに対応して、多品種のプラスチッ
ク製枠を製作する必要をなくするのみならず、土手を成
す粘度の高い樹脂は、プリント基板上の露出パターンに
接触しても差し支えないので、少なくともプラスチック
製枠分だけ樹脂封止範囲を狭くすることができ、したが
って、小型化ＣＯＢ構造を図るベアチップ封止方法およ
びこれによる半導体装置を提供できる効果がある。As described above, according to the present invention, by changing the trajectory where the dispenser of the sealing resin operates,
Because the sealing range can be changed flexibly, not only does it eliminate the need to manufacture a wide variety of plastic frames to support a wide variety of bare IC chips, but also the high viscosity resin that forms the bank Since the exposed pattern on the substrate may be contacted, the resin sealing area can be narrowed by at least the amount of the plastic frame, and therefore a bare chip sealing method for achieving a miniaturized COB structure and a semiconductor device using the same are provided. There is an effect that can be done.
【図１】（ａ）は、本発明の半導体製造方法の一実施形
態例により、粘度の高い樹脂により土手を作る工程を示
す斜視図、（ｂ）は、（ａ）の後、土手の内側に粘度の
低い樹脂を滴下する工程を示す斜視図である。FIG. 1A is a perspective view showing a step of forming a bank with a resin having a high viscosity according to an embodiment of a semiconductor manufacturing method of the present invention, and FIG. FIG. 6 is a perspective view showing a step of dropping a resin having a low viscosity into the resin.
【図２】図１（ｂ）の工程終了後の垂直断面図である。FIG. 2 is a vertical cross-sectional view after the step of FIG.
【図３】（ａ）は、従来例の半導体製造方法により、プ
ラスチック製枠を用いる工程を示す斜視図、（ｂ）は、
（ａ）の後、プラスチック製枠の内側に粘度の低い樹脂
を滴下する工程を示す斜視図である。FIG. 3A is a perspective view showing a step of using a plastic frame by a conventional semiconductor manufacturing method, and FIG.
It is a perspective view which shows the process of dripping low viscosity resin inside a plastic frame after (a).
【図４】本実施形態例の封止範囲と従来例の封止範囲と
の比較を示す図である。FIG. 4 is a diagram showing a comparison between a sealing range of the embodiment and a sealing range of a conventional example.
【符号の説明】 １ プリント基板 ２ ベアＩＣチップ ３ 金線 ４ 粘度の高い樹脂 ５ 粘度の低い樹脂 ６ ディスペンサ ７ ロボット ８ プリント基板上の露出パターン ９ 土手 １０ プラスチック製枠 １１，１２ 封止範囲（本願） ２１，２２ 封止範囲（従来）[Description of Signs] 1 Printed circuit board 2 Bare IC chip 3 Gold wire 4 High-viscosity resin 5 Low-viscosity resin 6 Dispenser 7 Robot 8 Exposed pattern on printed circuit board 9 Embankment 10 Plastic frame 11, 12 Sealed area (this application ) 21,22 Sealed area (conventional)
Claims (2)
法において、封止用粘性樹脂のディスペンサを基板面に
ほぼ平行なＸ軸方向及びＹ軸方向に動かしながら、粘度
の高い樹脂を、封止範囲の周囲に沿って吐出することに
より土手を形成し、形成した該土手の内側を粘度の低い
樹脂で充填することを特徴とするベアチップ封止方法。In a method of sealing a bare IC chip to a substrate, a high-viscosity resin is sealed while moving a dispenser of a sealing viscous resin in an X-axis direction and a Y-axis direction substantially parallel to the substrate surface. A bare chip sealing method, comprising: forming a bank by discharging along a periphery of a stop range; and filling the inside of the formed bank with a resin having a low viscosity.
実装するＣＯＢ構造の半導体装置において、樹脂封止範
囲の外側と内側が粘度の異なる樹脂により封止されてい
ることを特徴とする半導体装置。2. A semiconductor device having a COB structure in which a bare IC chip is directly mounted on a printed circuit board, wherein the outside and the inside of a resin sealing area are sealed with resins having different viscosities.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18601696A JPH1032217A (en) | 1996-07-16 | 1996-07-16 | Bare chip sealing method and semiconductor device manufacture by the method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18601696A JPH1032217A (en) | 1996-07-16 | 1996-07-16 | Bare chip sealing method and semiconductor device manufacture by the method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH1032217A true JPH1032217A (en) | 1998-02-03 |
Family
ID=16180919
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18601696A Pending JPH1032217A (en) | 1996-07-16 | 1996-07-16 | Bare chip sealing method and semiconductor device manufacture by the method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH1032217A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000260793A (en) * | 1999-03-12 | 2000-09-22 | Miyota Kk | Packaging method for ic chip and its structure |
| CN100386666C (en) * | 2002-11-19 | 2008-05-07 | Lg.菲利浦Lcd株式会社 | Distribution system for LCD board and method for using said system |
| CN100420985C (en) * | 2002-12-20 | 2008-09-24 | 乐金显示有限公司 | Distributor for liquid-crystal display board, and distributing method therewith |
| US8520178B2 (en) | 2006-07-04 | 2013-08-27 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing display device with electrode having frame shape |
| CN116547791A (en) * | 2020-12-16 | 2023-08-04 | 华为技术有限公司 | Chip package and preparation method thereof |
-
1996
- 1996-07-16 JP JP18601696A patent/JPH1032217A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000260793A (en) * | 1999-03-12 | 2000-09-22 | Miyota Kk | Packaging method for ic chip and its structure |
| CN100386666C (en) * | 2002-11-19 | 2008-05-07 | Lg.菲利浦Lcd株式会社 | Distribution system for LCD board and method for using said system |
| CN100420985C (en) * | 2002-12-20 | 2008-09-24 | 乐金显示有限公司 | Distributor for liquid-crystal display board, and distributing method therewith |
| US8520178B2 (en) | 2006-07-04 | 2013-08-27 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing display device with electrode having frame shape |
| CN116547791A (en) * | 2020-12-16 | 2023-08-04 | 华为技术有限公司 | Chip package and preparation method thereof |
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