JPH10322176A - Skew reduction circuit and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain the phase control in a simple circuit constitution by comparing a 1st period covering a leading edge through a trailing edge with a 2nd period covering the trailing edge through the leading edge and equally controlling both the 1st and 2nd periods. SOLUTION: A phase control circuit 11 performs control to relatively advance or delay the leading timing in different directions between leading and trailing edges. For instance, it is possible to relatively advance the trailing timing, while delaying relatively the leading timing. A period comparison circuit 12 detects the relative timing between the leading and trailing edges of a clock signal CLK1, whose phase is controlled and then controls the circuit 11 based on the detected timing. In other words, a period Thigh which covers the leading edge through the trailing edge is compared with a period Tlow covering the trailing edge through the leading edge to decide the longer of the periods. Then the circuit 11 is controlled based on the longer period decided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to an interface circuit, and more particularly to an input / output interface circuit of a semiconductor device.

[0002]

2. Description of the Related Art In a semiconductor device, it is desired to realize a high-speed operation by inputting and outputting data using a high-frequency signal. However, if the frequency of the data input / output signal is increased to achieve higher-speed operation, factors that control the signal frequency become apparent, and it is necessary to eliminate these factors.

[0003]

A major factor that limits the frequency of a data input / output signal is signal skew, that is, a shift in signal timing. For example, if there is a skew in the input clock signal for synchronization, when capturing another signal using the timing of the clock signal, an erroneous signal may be captured due to a timing shift. Since the possibility increases as the signal frequency increases, it becomes difficult to increase the operation speed by increasing the frequency of the signal when there is skew in the signal.

There are several types of skews, and skews of rising and falling edges of the signal have not been taken effectively in the past. This means that the rising timing and falling timing of the signal deviate from the desired timing. FIGS. 24A and 24B are diagrams for explaining rising / falling skew in a clock signal. FIG. 24A shows a case where there is no rise / fall skew, and FIG.
This shows a case where a rising / falling skew exists. In FIGS. 24A and 24B, the reference reference voltage Vref used for comparison by the receiving input buffer is shown together with the clock signal. By comparing the clock signal with the reference voltage Vref, a period during which the clock signal is recognized as a HIGH level is indicated as Thigh, and a period during which the clock signal is recognized as a LOW level is indicated as Tlow.

FIG. 24B shows a case where a skew exists in the clock signal, the transition time of the rise is short (the rise is steep), and the transition time of the fall is long (the fall is slow). Show. In this case, the period Thig
Each of h and the period Tlow deviates from the period shown in FIG. This means that the length of each period deviates from the normal length, and the rising / falling timing deviates from the normal timing.

If the rise / fall timing of the synchronization clock signal is deviated, there is a possibility that a signal is erroneously read when another signal is fetched. Also, if there is a rising / falling skew in a signal such as a data signal, the valid period in which the data is considered valid is limited to the shorter of the periods High and Tlow. For these reasons, when there is a rise / fall skew, it becomes difficult to increase the operation speed by increasing the frequency of the input / output signal.

The rising / falling skew has several causes. First, in the signal output circuit on the output side, the rise / fall transition time is different from each other due to the difference in circuit characteristics, so that the rise / fall skew is already included at the time of signal output. In the input buffer on the input side, if the reference voltage Vref to be compared with the signal input fluctuates for some reason, the period Th
high and the period Tlow will change. Furthermore, the rise / fall transition times differing from each other due to the difference in circuit characteristics in the input buffer also causes rise / fall skew.

It is generally considered that these rise / fall skew causes the same effect on each signal. This is because an output buffer and an input buffer having the same design are generally used for each signal, and the reference reference voltage Vref is commonly used. Therefore, it can be said that the rise / fall skew is a skew common to each signal.

Conventionally, the signal frequency used was not so high, and as a countermeasure against rising / falling skew, a circuit was designed to reduce the rising / falling skew.
However, such countermeasures are not sufficient, and it is necessary to reduce the rise / fall skew, especially in order to increase the signal frequency and realize a higher speed operation.

Accordingly, it is an object of the present invention to provide a circuit for reducing the rise / fall skew.

[0011]

According to a first aspect of the present invention, there is provided a circuit for adjusting a phase with respect to a rising edge and a falling edge of a signal, and adjusting the phase from the first phase adjusting circuit. Receiving the signal, and comparing a first period from the rising edge to the falling edge with a second period from the falling edge to the rising edge, and comparing the first period with the second period. A period comparison circuit for controlling the first phase adjustment circuit so that the period becomes the same is included.

According to a second aspect of the present invention, in the circuit according to the first aspect, the first phase adjusting circuit adjusts a phase by adjusting a transition time between the rising edge and the falling edge. It is characterized by adjusting. According to a third aspect of the present invention, the circuit according to the first aspect further includes a second phase adjustment circuit that adjusts a phase with respect to a rising edge and a falling edge of a signal other than the signal. The period comparison circuit performs the same control as the control on the first phase adjustment circuit on the second phase adjustment circuit.

According to a fourth aspect of the present invention, in the circuit of the first aspect, the period comparison circuit includes a first measurement circuit for measuring the first period and a second measurement period. A second measurement circuit for measuring, a measurement result of the first measurement circuit, and the second measurement circuit;
And a measurement result comparison circuit for comparing the measurement result with the measurement result of the measurement circuit. According to a fifth aspect of the present invention, in the circuit according to the fourth aspect, the first measuring circuit includes a first delay element row including a plurality of delay elements, and the first delay element row. The first period is measured by the number of delay elements through which the signal propagating through the first period passes, and the second measurement circuit includes a second delay element column including a plurality of delay elements. , The signal propagating through the second delay element column passes through the second delay element in accordance with the number of delay elements passing through the second period.
The period is measured.

According to a sixth aspect of the present invention, in the circuit according to the fifth aspect, the first measuring circuit includes a latch corresponding to a delay element through which a signal has passed during the first period. The other latches further include a first latch array comprising latches corresponding to respective delay elements of the first delay element array which hold a second level, and the second measurement circuit A latch corresponding to a delay element through which a signal has passed during the second period holds a first level, and the other latches hold a second level. And a measurement result comparison circuit, wherein the measurement result comparison circuit associates the first latch array with the second latch array for each latch, and latches between the corresponding latches. Based on the information about the level differences held by Characterized in that it comprises a circuit for comparing the period and the second period.

According to a seventh aspect of the present invention, in the circuit according to the first aspect, the period comparison circuit includes a first circuit for measuring the first period and a first circuit for measuring the first period. 1
A second circuit that indicates that the same length of time as the first period measured by the second circuit has elapsed, and a time relationship between the time that the second circuit indicates and the rising edge are compared. It is characterized by including a third circuit.

In a preferred embodiment of the present invention, the period comparison circuit includes a first circuit for measuring the second period and a first circuit for measuring the first period from the rising edge.
A comparison is made between a second circuit indicating that the same length of time as the second period measured by the second circuit has elapsed, and the relationship between the time indicated by the second circuit and the falling edge. And a third circuit.

According to a ninth aspect of the present invention, in the circuit according to the first aspect, the first phase adjusting circuit changes the phase of the rising edge and changes the phase of the falling edge. An edge adjustment circuit, and a phase change amount holding circuit for holding a parameter for determining a phase change amount of the edge adjustment circuit, and sequentially updating the parameter based on a magnitude relationship between the first period and the second period. It is characterized by including.

According to a tenth aspect of the present invention, in the circuit of the ninth aspect, the phase change holding circuit is a shift register. According to a twelfth aspect of the present invention, in the circuit according to the ninth aspect, the edge adjustment circuit receives the signal as an input, and changes an output at a first transition time in response to the rising edge. The output is changed at a second transition time in response to the falling edge, and the first transition time and the second transition time can be adjusted.

According to a twelfth aspect of the present invention, in the circuit according to the eleventh aspect, the edge adjustment circuit changes the first transition time and the first transition time by changing a driving force for driving an output signal. It is characterized in that the second transition time is changed. According to a thirteenth aspect of the present invention, in the circuit according to the twelfth aspect, the edge adjustment circuit includes an inverter including at least one PMOS transistor and at least one NMOS transistor, and the at least one PM transistor.
A first transistor including a plurality of first transistors inserted between an OS transistor and a power supply voltage, and a plurality of second transistors inserted between the at least one NMOS transistor and a ground voltage; By changing the number of transistors to be turned on among the transistors and the number of transistors to be turned on among the second transistors,
The phase of the rising edge is changed, and the phase of the falling edge is changed.

According to a fourteenth aspect of the present invention, a semiconductor device comprises: a first input buffer for receiving a clock signal input from the outside; a rising edge of the clock signal supplied from the first input buffer; A first phase adjustment circuit for adjusting a phase with respect to a falling edge;
Receiving the clock signal of which the phase has been adjusted from the phase adjustment circuit, and comparing a first period from the rising edge to the falling edge with a second period from the falling edge to the rising edge, A period comparison circuit that controls the first phase adjustment circuit so that the first period and the second period are the same.

According to a fifteenth aspect of the present invention, in the semiconductor device according to the fourteenth aspect, a second input buffer for receiving an externally input signal separately from the clock signal;
A second phase adjustment circuit for adjusting a phase with respect to a rising edge and a falling edge of the signal supplied from the second input buffer, wherein the period comparison circuit has the same control as that for the first phase adjustment circuit; Control of the second
Is applied to the phase adjustment circuit.

According to a sixteenth aspect of the present invention, the semiconductor device includes a first phase adjustment circuit for adjusting a phase with respect to a rising edge and a falling edge of a clock signal supplied from the inside, and the first phase adjustment circuit. Receiving the clock signal whose phase has been adjusted from a circuit and comparing a first period from the rising edge to the falling edge with a second period from the falling edge to the rising edge; A period comparing circuit for controlling the first phase adjusting circuit so that the period of the second signal is the same as the second period; and a phase comparator for a rising edge and a falling edge of a signal supplied from the inside separately from the clock signal. A second phase adjustment circuit that adjusts the signal, and an output buffer that outputs the signal whose phase has been adjusted by the second phase adjustment circuit to the outside,
The period comparison circuit performs the same control as the control on the first phase adjustment circuit on the second phase adjustment circuit.

According to a seventeenth aspect of the present invention, in the semiconductor device according to the sixteenth aspect, an output buffer and an input buffer provided between the first phase adjustment circuit and the period comparison circuit are further provided. It is characterized by including. Claims 1 to 13
In the present invention, the period in which the clock signal is at the HIGH level is compared with the period in which the clock signal is at the LOW level, and the phases of the rising edge and the falling edge of the clock signal are adjusted so that both periods are the same. Skew of the clock signal can be reduced. Also, by applying the same phase adjustment as that applied to the clock signal to other signals, it is possible to reduce the rise / fall skew in other signals. The phase adjustment of the rising edge and the falling edge can be easily realized by adjusting the transition time of each edge, and the transition time can be adjusted by changing the signal driving force. With the circuit described above, the phase adjustment function can be realized. Clock signal is HIGH
In the period of the level or the period of the LOW level, a predetermined signal is propagated through the delay element array, and the measurement can be performed based on the number of delay elements through which the signal passes during the period. Therefore, the period measurement / comparison can be realized by a circuit having a relatively simple configuration.

According to the present invention, in the input circuit of the semiconductor device, the period in which the clock signal input from the outside is at the HIGH level and the period in which the clock signal is at the LOW level are compared. By adjusting the phases of the rising edge and the falling edge of the clock signal so that the clock signal becomes the same, the skew of the rising / falling edge of the clock signal can be reduced, and the same phase as the phase adjustment applied to the clock signal can be achieved. By applying the adjustment to another input signal, the rise / fall skew in the other input signal can be reduced.

According to the present invention, in the output circuit of the semiconductor device, the period when the clock signal supplied from the internal circuit is at the HIGH level and the period when the clock signal is at the LOW level are compared. By adjusting the phase of the rising edge and the falling edge of the clock signal so that the period is the same, and applying the same phase adjustment to the output signal as the phase adjustment applied to the clock signal, the rising edge of the output signal / Fall skew can be reduced.

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The principle and embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 shows a configuration of a skew reduction circuit according to the principle of the present invention. The skew reduction circuit 10 of FIG. 1 includes a phase adjustment circuit 11 and a period comparison circuit 12. The phase adjustment circuit 11 receives the clock signal CLK, and adjusts the phase of the clock signal CLK to output the clock signal CLK1 whose phase has been adjusted. The phase-adjusted clock signal CLK1 is supplied to the period comparison circuit 12
Is input to The period comparison circuit 12 performs the period Th in which the phase-adjusted clock signal CLK1 is at the HIGH level.
comparing the high and the low period Tlow,
The phase adjustment circuit 11 is controlled so that both periods are the same.

The phase adjustment circuit 11 has a clock signal CLK.
Has the function of adjusting the rising timing and the falling timing of each of them in different directions. That is,
Control for relatively advancing or delaying the rise timing and control for relatively advancing or delaying the fall timing can be performed in different directions between the rise and the fall. For example, it is possible to relatively advance the falling timing while relatively delaying the rising timing. By such an adjustment, it is possible to adjust the HIGH period Tlow and the LOW period Tlow of the clock signal CLK1 to be equal.

The period comparison circuit 12 detects the relative timing of the rising edge and the falling edge of the clock signal CLK1 whose phase has been adjusted, and controls the phase adjustment circuit 11 based on the detected timing. Specifically, a period Thigh from the rising edge to the falling edge and a period Tl from the falling edge to the rising edge
ow, to determine which period is longer, and control the phase adjustment circuit 11 based on this.

FIG. 2 shows a configuration in which the skew reduction circuit 10 according to the principle of the present invention is applied to skew reduction of signals other than the clock signal CLK. In FIG. 2, the control signal from the period comparison circuit 12 is supplied not only to the phase adjustment circuit 11 receiving the clock signal CLK but also to another phase adjustment circuit 11A receiving another signal. The phase adjustment circuit 11A applies the same phase adjustment as that of the phase adjustment circuit 11 to the input signal.

As described above, the cause of the rise / fall skew is generally the same for each signal, and the rise / fall skew is common to each signal. Therefore, if the phase adjustment for reducing the rising / falling skew of the clock signal CLK is applied to signals other than the clock signal as in the configuration of FIG. Skew can be reduced. In this manner, the rise / fall skew of other signals can be reduced based on the clock signal CLK.

As described above, according to the present invention, the skew reduction circuit includes a phase adjustment circuit for adjusting the phase of the clock signal CLK, a period Thigh from the rising edge to the falling edge, and a period from the falling edge to the rising edge. By providing a period comparison circuit that controls the phase adjustment circuit based on the result of comparison with the period Tlow, the clock signal CLK can be adjusted so that the HIGH period High and the LOW period Tlow of the clock signal CLK1 are equal to each other. , The rise / fall skew of the clock signal CLK can be reduced. Further, utilizing the fact that the rising / falling skew is common to each signal, the clock signal C
Based on the LK, the rise / fall skew of other signals can be reduced.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. FIG. 3 shows an embodiment of the skew reduction circuit according to the present invention. FIG. 4 shows the signals R1, R shown in FIG.
2, CLK, CLK1, / CLK1, and S0 to S7
FIG. The skew reduction circuit in FIG. 3 receives the clock signal CLK and outputs the clock signal CLK1 whose phase has been adjusted.

The skew reduction circuit of FIG. 3 includes the phase adjustment circuit 11 and the period comparison circuit 12 of FIG. The input clock signal CLK is supplied to the phase adjustment circuit 11. The phase adjustment circuit 11 includes a phase adjustment circuit 21 and a shift register 22. The phase adjustment circuit 21 adjusts the phase of the input clock signal CLK, and outputs the clock signal CLK1 whose phase has been adjusted and an inverted clock signal / CLK1 which is an inverted signal thereof. Clock signal CLK1 output from phase adjustment circuit 11 and inverted clock signal / CLK1
Are input to the period comparison circuit 12.

The period comparison circuit 12 includes an edge detection circuit 23
-1 to 23-4, period measuring circuit 24, binary counter 25, NAND circuits 31 to 34, inverters 35 to 39, NOR circuits 39 and 40, and inverter 41
To 47 are included. The operation of the period comparison circuit 12 will be described later in detail. Schematically, as shown in FIG. 4, the edge detection circuits 23-1 to 23-4 of the period comparison circuit 12 include a signal S1 which becomes HIGH at the first rising edge of the clock signal CLK1 and an inverted clock signal / CLK
The signal S2 which becomes HIGH at the first rising edge of 1
And S3, and a signal S4 which becomes HIGH at the second rising edge of the clock signal CLK. The period measurement circuit 24 of the period comparison circuit 12 measures a period Thigh between rising edges of the signals S1 and S2, and
3 and the period Tlow between the rising edges of the signal S4. The period measuring circuit 24 sets one of the signal S5 and the signal S6 to HIGH according to the magnitude relation of the measured periods. Information indicating which of the signal S5 and the signal S6 is HIGH is supplied to the shift register 22 of the phase adjustment circuit 11 when the timing signal S7 is HIGH.

When the period High is longer than the period Tlow, the shift register 22 outputs the clock signal CLK1.
The phase adjustment circuit 21 is controlled so that the rising edge is delayed and the falling edge is advanced. Conversely, when the period High is shorter than the period Tlow as in the case shown in FIG. 4, the phase adjustment circuit 21 causes the rising edge of the clock signal CLK1 to advance and the falling edge to be delayed.
Control. By this control, the clock signal CLK1
Are adjusted so that the period High and Tlow are equal.

Hereinafter, each component of the skew reduction circuit of FIG. 3 will be described. Each of the edge detection circuits 23-1 to 23-4, which are the same circuit, includes NAND circuits 51 to 56 and inverters 57 to 59. In the edge detection circuit 23-1, immediately after the reset signal R1 becomes HIGH, the input of the latch formed by the NAND circuits 51 and 52 is such that the reset signal R1 is HIGH and the clock signal CLK1 is LOW. The outputs of the NAND circuits 51 and 52 hold the states of LOW and HIGH, respectively. This state does not change even if the clock signal CLK1 changes. When the clock signal CLK1 becomes HIGH, the outputs of the NAND circuits 51 and 52 become the NAND circuit 5
The signals are input to the latches composed of NAND circuits 55 and 56 via 3 and 54. Therefore, the NAND circuit 5
The outputs of 5 and 56 are fixed at LOW and HIGH. This state does not change even if the clock signal CLK1 changes. Accordingly, the output of the edge detection circuit 23-1 becomes HIGH at the first rising edge of the clock signal CLK1 after the reset signal R1 becomes HIGH, and thereafter keeps the HIGH level until reset.

In the edge detection circuits 23-2 and 23-3, the reset signal R for the edge detection circuit 23-1 is output.
1, a signal having the same waveform as the signal S1 is input, and an inverted clock signal / CLK is used instead of the clock signal CLK.
1 is input. Therefore, the outputs of the edge detection circuits 23-2 and 23-3 become HIGH at the first rising of the inverted clock signal / CLK1 after the signal S1 becomes HIGH.
It becomes H, and thereafter, it keeps the HIGH level until it is reset.

In the edge detection circuit 23-4, a signal having the same waveform as the signal S3 is input instead of the reset signal R1 to the edge detection circuit 23-1. Therefore, the output of the edge detection circuit 23-4 becomes H at the first rising edge of the clock signal CLK1 after the signal S3 becomes HIGH.
It goes to the high level, and then holds the high level until reset.

As described above, the edge detection circuits 23-1 to 23-4 output the signals S1 to S4 as shown in FIG.
Can be generated. FIG. 5 is a circuit diagram of a first embodiment of the period measuring circuit 24. The period measurement circuit 24 in FIG.
Are inverters 91-1 to 91-n connected in series
(N is an even number), NAND circuits 92-1 to 92-n forming a latch every two, and an inverter connected in series.
93-1 to 93-n, NAND circuits 94-1 to 94-n forming a latch every two, and NAND circuit 9
Inverters 95-1 to 95-n / 2 for inverting outputs from latches formed by 2-1 to 92-n;
Inverters 96-1 to 96-n / 2 for inverting outputs from latches formed by the circuits 94-1 to 94-n;
AND circuits 97-1 to 97-n and a NAND circuit 98
-1 to 98-n.

The row of inverters 91-1 to 91-n in FIG. 5 constitutes a delay element row, and an input signal S1 propagates while being delayed in the delay element row. Inverter 91-1
The signal S2 propagates on the signal line SA in parallel with the delay element arrays 91 to n. That is, the signal S1 propagating with delay in the delay element row and the signal S2 propagating without delay on the signal line SA compete with each other.

The latch group formed by the NAND circuits 92-1 to 92-n latches LOW as an output when the signal S1 becomes HIGH first, and latches HIGH as an output when the signal S2 becomes HIGH first. As shown in FIG. 4, at the time of input, the signal S1 becomes HIGH first, so that the latch group on the left side of FIG. 5 near the input latches LOW. As the signal propagates to the right of FIG.
Since 1 is delayed, the latch group on the right side of FIG. 5 far from the input latches HIGH. The position of the boundary between the latch group that latches LOW and the latch group that latches HIGH indicates the time difference between the edges of the signals S1 and S2. The smaller the time difference, the closer the boundary will be to the input side.

Similarly, NAND circuits 94-1 to 94-n
Latches LOW as an output when the signal S3 goes high first, and the signal S4 goes high first.
When it becomes H, HIGH is latched as an output. As shown in FIG. 4, at the time of input, the signal S3 is first set to HI.
GH, the latch group on the left side of FIG.
Latch OW. Since the signal S3 is delayed as the signal propagates to the right in FIG. 5, the latch group on the right side in FIG. 5 farther from the input latches HIGH. The position of the boundary between the latch group that latches LOW and the latch group that latches HIGH indicates the time difference between the edges of the signal S3 and the signal S4. The smaller the time difference, the closer the boundary will be to the input side.

In the example shown in FIG. 5, the signals S1 and S2
And the time difference between the edges of the NAND circuit 92
The output of the latch consisting of -5 and 92-6 is HIGH, which corresponds to the boundary indicating the time difference. This boundary is defined as a first boundary. The time difference between the edges of the signal S3 and the signal S4 is relatively long, and the NAND circuit 94-n
-3 and 94-n-2 are HIGH.
This HIGH corresponds to the boundary indicating the time difference.
This boundary is defined as a second boundary. In this case, the pair of NAND circuits 97-2x-1 and 97-2x are both HIGH from the right end to the second boundary which is the first boundary.
Is output. However, beyond the second boundary, the pair of NAND circuits 97-2x-1 and 97-2x will output HIGH and LOW. This output is the same after the first boundary, and the final output signals S5 and S6 are HIGH and LOW.

Contrary to the example shown in FIG. 5, the signals S1 and S
2 is longer than the time difference between the edges of the signals S3 and S4, the NAND circuit 97-2x-
Starting from the right side, the pair of 1 and 97-2x outputs LOW and HIGH after a first boundary (a boundary indicating a time difference between the signals S1 and S2). This is propagated to the final output, and the NAND circuits 97-1 and 9-9
The signals S5 and S6, which are the outputs of 7-2, are LOW and H
It becomes IGH.

As described above, if the period measuring circuit 24 shown in FIG. 5 is used, the time difference between the signal S1 and the signal S2 (the period Thig
h) and measuring the time difference (period Tlow) between the signal S3 and the signal S4, and comparing the two time differences, one of the output signals S5 and S6 can be set to HIGH. In the configuration of FIG. 5, when the period High is shorter than the period Tlow, the signal S5 becomes HIGH,
When the period High is longer than the period Tlow, the signal S6
Becomes HIGH.

Referring again to FIG. 3, signals S5 and S6 from period measuring circuit 24 are output from NOR circuits 39 and 40, respectively.
Are supplied to the shift register 22 via a gate group including NAND circuits 31 to 34 and inverters 35 to 38. Each of the NOR circuits 39 and 40 is a gate for passing the signal S5 and the signal S6 only when the timing signal S7 is HIGH. Timing signal S
Reference numeral 7 denotes a signal that goes high when the period measurement circuit 24 outputs valid data of the signals S5 and S6. The timing signal S7 is determined by the period measuring circuit 24 when the period Thigh and the period Tlo of the periodic clock signal CLK1 are changed.
is periodically compared with w to periodically output valid data, and HIGH and LOW are periodically repeated.

FIG. 6 is a timing chart showing the timing signal S7, the signals S8 and S9 output from the NOR circuits 39 and 40, and the output signals S10 and S11 of the binary counter 25 to which the timing signal S7 is input.
Since the signals S8 and S9 correspond to the inversion of the signals S5 and S6 output from the period measurement circuit 24, for example, when the signal S6 is selected, the signal S8 becomes H as shown in FIG.
It becomes IGH. That is, when the period Thigh is longer than the period Tlow, the signal S8 becomes HIGH, and the period Thigh
When h is shorter than the period Tlow, the signal S9 becomes HIGH.

As shown in FIG. 6, the timing signal S7 is a signal which periodically repeats HIGH and LOW. This timing signal S7 is transmitted to the binary counter 25.
Supplied to The binary counter 25 includes NAND circuits 61 to 68 and inverters 69 to 71. Since the operation is within the range of the conventional technology, the description is omitted.
Signals S10 and S1 output from the binary counter 25
1, the timing signal S7 is set to 1 as shown in FIG.
The signal is divided into two and the inverted signal.

The signal S8 is sent from the NOR circuit 39 to the NAND
The signal S9 is supplied to the circuits 31 and 32, and the signal S9 is supplied from the NOR circuit 40 to the NAND circuits 33 and 34. NA
A signal S10 output from the binary counter 25 is supplied to the other inputs of the ND circuits 31 and 33.
The other input of the ND circuits 32 and 34 is supplied with a signal S11 output from the binary counter 25.

Therefore, as in the case of FIG.
When the signal becomes IGH, the signal S8 is output from the inverters 35 and 36 which invert the outputs of the NAND circuits 31 and 32.
Are output alternately. That is, the pulses P1 and P3 shown in FIG.
Circuit 31 and inverter 35 opened by
, And the pulse P2 is output through the NAND circuit 32 and the inverter 36 opened by the signal S11. The same applies to the case where the signal S9 becomes HIGH, and HIGH pulses are alternately output from the inverters 37 and 38.

Therefore, when the period High is longer than the period Tlow, the inverters 35 and 36 output HIGH.
Pulses are output alternately, and the period High is changed to the period Tlo
If it is shorter than w, HI from inverters 37 and 38
GH pulses are output alternately. These pulse signals are supplied to the shift register 22 of FIG. FIG.
2 shows a circuit diagram of a shift register 22. FIG. Shift register 2
2 denotes inverters 101-1 to 101-8, inverters 102-1 to 102-8, and a NAND circuit 103-1
To 103-8, NMOS transistors 104-1 to 104-8, and NMOS transistors 105-1 to 10-10
5-8, NMOS transistors 106-1 to 106-
8, and the NMOS transistors 107-1 to 107-
8 inclusive. When the reset signal R2 is set to LOW, the shift register 22 is reset. That is, when the reset signal R2 becomes LOW, the NAND circuits 103-1 to 103-1
03-8 becomes HIGH, and the inverter 102-
Outputs of 1 to 102-8 become LOW. Each pair of the NAND circuits 103-1 to 103-8 and the inverters 102-1 to 102-8 forms a latch by using their outputs as inputs. Therefore, in the initial state set by the reset signal R2, the reset signal R2 is set to HI.
It is held even after returning to GH.

In this initial state, as shown in FIG. 9, the outputs Q1 to Q4 of the inverters 101-1 to 101-4 are HIGH, and the inverters 101-5 to 101-4 are high.
Outputs Q5 to Q8 of 01-8 are LOW. When the rising edge of the clock signal CLK1 needs to be advanced, a HIGH pulse is supplied to the signal lines A and B alternately. First, when a HIGH pulse is supplied to the signal line B, the NMOS transistor 104-5 is turned on. At this time, since the NMOS transistor 106-5 is on, the output of the NAND circuit 103-5 is connected to the ground, forcibly changing from HIGH to LOW.
Therefore, the output of the inverter 102-5 becomes HIGH,
This state is when the NAND circuit 103-5 and the inverter 102
-5 latch. At this time, the output Q5
Changes from LOW to HIGH. Therefore, in this state, the outputs Q1 to Q5 are HIGH and the outputs Q6 to Q8
Becomes LOW.

Next, when a HIGH pulse is supplied to the signal line A, the NMOS transistor 104-6 is turned on.
At this time, since the NMOS transistor 106-6 is on, the output of the NAND circuit 103-6 is connected to the ground, forcibly changing from HIGH to LOW. Therefore, the output of the inverter 102-6 is HIGH.
, And this state is held in the latch including the NAND circuit 103-6 and the inverter 102-6. At this time, the output Q6 changes from LOW to HIGH. Therefore, in this state, the outputs Q1 to Q6 are HIGH and the output Q7
And Q8 become LOW.

As described above, the signal lines A and B are alternately set to the high level.
By supplying the H pulse, the number of HIGH outputs among the outputs Q1 to Q8 can be increased one by one. Note that among the outputs Q1 to Q8, HIGH outputs are collected on the left side, and LOW outputs are collected on the right side. When it is necessary to delay the rising edge of the clock signal CLK1, the signal lines C and D are alternately set to HIG.
Supply H pulse. First, when a HIGH pulse is supplied to the signal line C in the initial state shown in FIG.
The S transistor 105-4 turns on. At this time, NM
Since OS transistor 107-4 is on, NAN
The output of the D circuit 103-4 is connected to the ground, and is forced to change from HIGH to LOW. Accordingly, the output of the inverter 102-4 becomes HIGH, and this state is held in the latch including the NAND circuit 103-4 and the inverter 102-4. At this time, the output Q4 is
It changes from H to LOW. Therefore, in this state, the output Q
1 to Q3 are HIGH, and outputs Q4 to Q8 are LOW.

Next, when a HIGH pulse is supplied to the signal line D, the NMOS transistor 105-3 is turned on.
At this time, since the NMOS transistor 107-3 is turned on, the output of the NAND circuit 103-3 is connected to the ground, and the output is forcibly changed from HIGH to LOW. Therefore, the output of the inverter 102-3 is HIGH.
And this state is held in the latch including the NAND circuit 103-3 and the inverter 102-3. At this time, the output Q3 changes from HIGH to LOW. Therefore, in this state, the outputs Q1 and Q2 are HIGH and the output Q3
And Q8 become LOW.

As described above, the signal lines C and D are alternately set to the high level.
By supplying the H pulse, the number of outputs that are LOW among the outputs Q1 to Q8 can be increased one by one. Note that among the outputs Q1 to Q8, HIGH outputs are collected on the left side, and LOW outputs are collected on the right side.
By supplying these output signals Q1 to Q8 to the phase adjustment circuit 21 (FIG. 3), the phases of the signals are adjusted.

FIG. 8 shows the phase adjustment circuit 21. The phase adjustment circuit 21 includes the PMOS transistors 111-1 to 111-1.
11-8, PMOS transistors 112-0 to 112
-8, NMOS transistors 113-0 to 113-
8, NMOS transistors 114-1 to 114-8,
And inverters 115 to 120.

Signals Q1 to Q from shift register 22
8 are PMOS transistors 111-1 to 111
-8 and NMOS transistors 114-1 to 114-8
Input to the gate. PMOS transistor 112-
0 to 112-8 and the NMOS transistors 113-0 to 113-8 form one inverter as a whole with the clock signal CLK as a gate input. Therefore, a signal whose phase relationship is inverted with respect to the input signal is output as the inverted clock signal / CLK1, and a signal having the same phase relationship as the input signal is output as the clock signal CLK1.

In an initial state in which the signals Q1 to Q4 are HIGH and the signals Q5 to Q8 are LOW, the PMOS transistors 111-1 to 111-4 are on on the power supply voltage side and the NMOS transistor 114 is on the ground voltage side.
-5 to 114-8 are on. Therefore, when the clock signal CLK becomes HIGH, N
MOS transistors are 113-0 through 113-4 for a total of 5
One. When the clock signal CLK becomes LOW, the PMOS transistor driven by this becomes 11
2-0 and 112-5 through 112-8, for a total of five.
Therefore, the driving force corresponding to the rising edge of the clock signal CLK is equal to the driving force corresponding to the falling edge.

Here, among the signals Q1 to Q8, HIGH
When the number of signals is increased, the number of driven NMOS transistors increases, the driving force corresponding to the rising edge of the clock signal CLK increases, and the number of driven PMOS transistors decreases. The driving force corresponding to the falling edge of is smaller. Therefore, the transition time of the rising edge of the clock signal CLK1 is shortened, and as a result, the rising edge is advanced. Further, the transition time of the falling edge of the clock signal CLK1 becomes longer, and as a result, the falling edge is delayed.

Conversely, when the number of HIGH signals among the signals Q1 to Q8 decreases, the number of NMOS transistors to be driven decreases, the driving force corresponding to the rising edge of the clock signal CLK decreases, and the driving force decreases. The number of PMOS transistors to be performed increases, and the driving force corresponding to the falling edge of the clock signal CLK increases. Therefore, the transition time of the rising edge of the clock signal CLK1 becomes longer, and as a result, the rising edge is delayed. Further, the transition time of the falling edge of the clock signal CLK1 is shortened, so that the falling edge is advanced.

As described above, the period comparison circuit 12 determines which of the period High and the period Tlow of the clock signal CLK1 is longer, and based on the result of this determination, the output signals Q1 to Q8 of the shift register 22. , The number of HIGH signals is adjusted. Signals Q1 through Q
According to the number of HIGH signals among the eight signals, the phase adjustment circuit 21 changes the driving force for the rising edge and the driving force for the falling edge of the clock signal CLK.
Thereby, the clock signal CL is set such that the period High and the period Tlow of the clock signal CLK1 are equal.
The timing of the rising edge and the falling edge of K1 can be adjusted.

FIG. 9 shows a modification of the phase adjustment circuit 21. In FIG. 9, the same components as those in FIG. 8 are referred to by the same numerals. In the phase adjustment circuit 21A of FIG.
OS transistors 112-0 and 112-1 and NMOS
Transistors 113-0 and 113-1 form one inverter. HIGH among the signals Q1 to Q8
Increases, the PMOS transistor 1
Since the number of transistors that are turned on among the transistors 11-1 to 111-8 is reduced, the resistance value present on the power supply voltage side of the inverter is increased, and the fall of the input signal is slow. Also, the NMOS transistors 114-1 to 114-1
Since the number of transistors turned on among the transistors 14-8 increases, the resistance value interposed on the ground side of the inverter decreases, and the rising of the input signal becomes steep. As a result, the rising edge is advanced and the falling edge is delayed.

Conversely, when the number of HIGH signals among the signals Q1 to Q8 decreases, the rising edge of the signal is delayed and the falling edge is advanced. FIG.
Shows a further modification of the phase adjustment circuit 21. 10, the same components as those in FIGS. 8 and 9 are referred to by the same numerals. In the phase adjustment circuit 21B of FIG.
The OS transistor 112-0 and the NMOS transistor 113-0 form one inverter.

When the number of HIGH signals among the signals Q1 to Q8 increases, the PMOS transistor 111-
Since the number of transistors that are turned on among 0 to 111-8 decreases, the resistance value interposed on the power supply voltage side of the inverter increases, and the fall of the input signal becomes slow. In addition, NMOS transistors 114-0 to 114-
Since the number of transistors that are turned on among the eight transistors increases, the resistance value interposed on the ground side of the inverter decreases, and the rising of the input signal becomes steep. As a result, the rising edge is advanced and the falling edge is delayed.

Conversely, when the number of HIGH signals among the signals Q1 to Q8 decreases, the rising edges of the signals are delayed and the falling edges are advanced. FIG. 1
2, the PMOS transistor 111-0 and the NMO
S transistor 114-0 is always on. Therefore, all of the signals Q1 to Q8 are LOW or all are H
Even if it becomes IGH, the operation of the inverter constituted by the PMOS transistor 112-0 and the NMOS transistor 113-0 is not stopped.

FIG. 11 is a circuit diagram of a second embodiment of the period measuring circuit 24. 11, the same elements as those of FIG. 5 are referred to by the same numerals, and a description thereof will be omitted. FIG.
The period measuring circuit 24A of FIG.
The NAND circuits 150-1 to 150-n and the NAND circuits 151-1 to 151-n are used instead of the NAND circuits 98-1 to 97-n and the NAND circuits 98-1 to 98-n.
The operation of the period measuring circuit 24A is the same as that of the period measuring circuit 24 shown in FIG.
Since the operation is almost the same as that described above, the description is omitted.

FIG. 12 is a circuit diagram of a third embodiment of the period measuring circuit 24. 12, the same elements as those of FIG. 5 are referred to by the same numerals, and a description thereof will be omitted. FIG.
The period measurement circuit 24B uses the output on the opposite side of the latch group composed of the NAND circuits 92-1 to 92-n by removing the inverters 95-1 to 95-n / 2 in FIG. 96-n / 2 is removed and the output on the opposite side of the latch group consisting of the NAND circuits 94-1 to 94-n is used. The operation of the period measurement circuit 24B is as follows.
Since the operation is almost the same as that of the period measurement circuit 24 in FIG. 5, the description is omitted.

FIG. 13 is a circuit diagram of a fourth embodiment of the period measuring circuit 24. 13, the same elements as those of FIG. 5 are referred to by the same numerals, and a description thereof will be omitted. FIG.
Is measured by the inverters 95-1 to 95-n / 2 and the inverters 96-1 to 96-n / in FIG.
2 and the circuits having the same configuration as the circuits including the NAND circuits 97-1 to 97-n and the NAND circuits 98-1 to 98-n are replaced with the NAND circuits 152-1 to 152-n.
5 and NAND circuits 153-1 to 153-n, and are arranged in the opposite direction to FIG. The operation of the period measurement circuit 24C is almost the same as the operation of the period measurement circuit 24 in FIG.

FIG. 14 is a circuit diagram of a fifth embodiment of the period measuring circuit 24. 14, the same elements as those of FIG. 5 are referred to by the same numerals, and a description thereof will be omitted. For the sake of simplicity of the description and the drawings, the suffix numbers following the hyphens of the reference numbers of these same elements are omitted. In the period measuring circuit 24 of FIG. 5, the signal propagates from the right side of the drawing to the output signals S5 and S6 on the left side of the drawing through each gate in the circuit composed of the NAND circuits 97 and 98. In order to reduce the time required for signal propagation, FIG.
In the period measuring circuit 24D of No. 4, the three-input NAND circuits 162-1 and 162-2 and the two-input NAND circuit 16
3-1 and 163-2 and a 2-input NAND circuit 164-
1 and 164-2 are used.

The output of the pair of NAND circuits 164-1 and 164-2 jumps over a plurality of gate arrays, and the input of the pair of NAND circuits 162-1 and 162-2 at the next stage and the NAND circuit 163-1 and 162-1. 163-2. The NAND circuits 164-1 and 164-
When both outputs of the pair 2 are HIGH, this HIGH output does not affect the outputs of the NAND circuits 162-1 and 162-2 and the outputs of the NAND circuits 163-1 and 163-2 in the next stage.

When, for example, the output of the NAND circuit 164-1 of the pair of outputs of the NAND circuits 164-1 and 164-2 is LOW, the NAND circuit 162-1 and the NAND circuit 163-1 of the next stage output HIGH. I do. Therefore, the next-stage NAND receiving these two HIGH signals
The circuit 164-1 outputs LOW. That is, the output of the pair of NAND circuits 164-1 and 164-2 is propagated to the output signals S5 and S6 on the left side of FIG. The operations other than those described above are the same as those of the period measurement circuit 24 in FIG.

As described above, the period measuring circuit 24D shown in FIG.
Is compared with the period measurement circuit 24 in FIG.
And S6 can be output in a short time. FIG.
FIG. 10 shows a circuit diagram of a sixth embodiment of the period measurement circuit 24. FIG.
5, the same elements as those in FIG. 5 are referred to by the same numerals,
The description is omitted. For the sake of simplicity of the description and the drawings, the suffix numbers following the hyphens of the reference numbers of these same elements are omitted.

In the period measurement circuit 24E shown in FIG. 15, a plurality of inverters 170 and a plurality of inverters 171 are also inserted as delay elements in the signal lines SA and SB. Here, inverters 170 and 171 have a slightly shorter delay time than inverters 91 and 93. That is, rather than the signal propagating through the inverter 91 or 93, the inverter 1
The signal propagating through 70 or 171 propagates slightly faster. Therefore, for example, when considering the signal S1 propagating through the delay element array of the plurality of inverters 91 and the signal S2 propagating through the plurality of inverters 170, the time difference between the rising edges of the signal S1 and the signal S2 is calculated as shown in FIG. Can be measured with higher accuracy than the period measurement circuit 24.

The operation of the period measuring circuit 24E other than that described above is the same as the operation of the period measuring circuit 24 of FIG. FIG. 16 is a circuit diagram of a seventh embodiment of the period measurement circuit 24. 16, the same elements as those of FIG. 5 are referred to by the same numerals, and a description thereof will be omitted. For the sake of simplicity of the description and the drawings, the suffix numbers following the hyphens of the reference numbers of these same elements are omitted.

The period measuring circuit 24F of FIG. 16 differs from the period measuring circuit 24 of FIG. 5 in that a circuit for propagating a signal from the right side to the left side output signals S5 and S6 in the drawing. This circuit includes a plurality of NAND circuits 172, a plurality of NAND circuits 173, two inverters 174, and two
One NAND circuit 175, one NAND circuit 176, and one inverter 177 are included. The input / output level of each gate shown in FIG. 16 indicates a state in which the signals S1, S2, S3, and S4 have reached the right end of the drawing and the signal line SC is still at the LOW level. When the signal line SC changes to the high level from this state, the output level of the NAND circuit 173 indicated by a circle in the drawing changes to a plurality of Ns equivalently functioning as inverters.
The signal passes through the AND circuits 172 and 173, passes through the inverter 174, and is input to a latch included in the NAND circuit 175. Therefore, in the case of the example shown in FIG. 16, the signal S6 becomes HIGH and the signal S5 becomes LOW. As in the case of FIG. 5, which of the signals S5 and S6 is H
Whether to become IGH is determined by which of the period High and the period Tlow is longer.

As can be seen by comparing the period measurement circuit 24F of FIG. 16 with the period measurement circuit 24 of FIG. 5, the period measurement circuit 24F of FIG. 16 can be realized with a relatively simple circuit configuration. FIG. 17 is a circuit diagram of an eighth embodiment of the period measurement circuit 24. 17, the same elements as those of FIG. 16 are referred to by the same numerals, and a description thereof will be omitted.

In the period measuring circuit 24G of FIG. 17, NAND circuits 181 and 182 and an inverter 183 are used instead of the NAND circuits 172 and 173 of the period measuring circuit 24F of FIG. The basic operation of the period measurement circuit 24G is the same as that of the period measurement circuit 24F, and thus the description is omitted. FIG. 18 is a circuit diagram of a ninth embodiment of the period measurement circuit 24.

The period measuring circuit 24H shown in FIG. 18 includes a plurality of inverters 201, a plurality of NAND circuits 202, a plurality of inverters 203, and a plurality of NAs forming a latch for each pair.
It includes an ND circuit 204, a plurality of NAND circuits 205, a plurality of inverters 206, a plurality of inverters 207, and NAND circuits 208 and 209 forming a latch. FIG.
8, a plurality of inverters 201 and a plurality of NANDs
The circuit 202 forms a delay element array, through which the signal S1 propagates. The signal S2 propagates through the signal line SA arranged in parallel with the delay element row. That is, the signal S1 propagating with delay in the delay element row and the signal S2 propagating without delay on the signal line SA compete with each other.

The latch group formed by the NAND circuit 204 outputs HIGH when the signal S1 becomes HIGH first.
H is latched, and when the signal S2 becomes HIGH first, LOW is latched as an output. As shown in FIG. 4, at the time of input, the signal S1 goes high first, so that the latch group on the left side of FIG. 18 near the input latches HIGH. Since the signal S1 is delayed as the signal propagates to the right in FIG. 18, the latch group on the right side in FIG.
OW will be latched. The position of the boundary between the latch group that latches LOW and the latch group that latches HIGH indicates the time difference between the edges of the signals S1 and S2. The smaller the time difference, the closer the boundary will be to the input side.

The leftmost output of the latch group that latches LOW is indicated by a circle in the drawing, and this LOW output is output by a plurality of NAND circuits 205 and a plurality of inverters 2.
06, and propagates through the NAND circuit 20
8 and 209 are input to the latches. Here, the delay element string including the plurality of NAND circuits 205 and the plurality of inverters 206 is a circuit equivalent to the delay element string including the plurality of inverters 201 and the plurality of NAND circuits 202. Therefore, the speed at which the signal propagates through both delay element arrays is equal.

FIG. 19 is a timing chart showing the relationship between the signals S1, S2, and S4 input to the period measuring circuit 24H of FIG. 18 and the signal SS input to the NAND circuit 208 forming the latch. As can be understood from the above description, the signal S1 propagates through the delay element column for a time Thigh until the signal S2 becomes HIGH, and is latched by the latch including the NAND circuit 204. The latched signal propagates through the delay element array having the same characteristic by the same length, and is input to the NAND circuit 208 as the signal SS. Therefore, as shown in FIG. 19, the signal SS is a signal that rises with a further delay by the time Thigh from the rising of the signal S2.

The latch composed of NAND circuits 208 and 209 latches the earlier rising of signal S4 and signal SS. Therefore, in the case of the example shown in FIG. 19, the signals S5 and S6 are LOW and HIGH, respectively. At this time, as shown in FIG.
The period High of LK1 is shorter than the period Tlow. Conversely, when the period High is longer than the period Tlow,
The relationship between the signals S5 and S6 is also reversed.

As described above, the period measuring circuit 24H shown in FIG.
Can be realized with a simpler circuit configuration as compared with any of the above-described embodiments, and has the advantage that the circuit scale can be reduced. Note that it is needless to say that the two circuits can be compared with each other by using the same circuit even if the period Thigh and the period Tlow are exchanged. FIG. 20 shows an example in which the skew reduction circuit according to the present invention is applied to a semiconductor device. 20 includes an input circuit 301, a core circuit 302,
And an output circuit 303. The input circuit 301 receives an input signal from the outside and converts the received input signal into a core circuit 302.
To supply. An output signal from the core circuit 302 is output to the outside of the semiconductor device 300 via the output circuit 303.

The skew reduction circuit according to the present invention may be used as an input interface circuit for signal input such as the input circuit 301 or may be used as an output interface circuit for signal output such as the output circuit 203. FIG. 21 shows an embodiment in which the skew reduction circuit according to the present invention is used as an input interface circuit for signal input. 21, the same components as those of FIG. 3 are referred to by the same numerals, and a description thereof will be omitted.

The clock signal CLK input from the outside via the input buffer 13 is phase-adjusted by the phase adjusting circuit 21 and supplied to the internal circuit (for example, the core circuit 302 in FIG. 20) as the clock signal CLK1. The phase adjustment circuit 21 is controlled by the period comparison circuit 12 and the shift register 22 so that the period High and the period Tlow of the clock signal CLK1 are equal. Similar phase adjustment by the shift register 22 and the phase adjustment circuit 21 is performed on other input signals SI. As a result, the input signal SI1 with reduced rising / falling skew can be obtained. The input signal SI1 with reduced rising / falling skew is supplied to an internal circuit (for example, the core circuit 302 in FIG. 20).

FIG. 22 shows an embodiment in which the skew reduction circuit according to the present invention is used as an output interface circuit for signal output. 22, the same elements as those of FIG. 3 are referred to by the same numerals, and a description thereof will be omitted. FIG.
The skew reduction circuit of the first embodiment converts the clock signal CLK and the internal signal SI into an internal circuit (for example, the core circuit 302 in FIG. 20)
Supplied from The rising / falling skew included in the clock signal CLK and the internal signal SI is reduced based on the clock signal CLK. The internal signal SI1 whose rising / falling skew has been reduced is output from the phase adjustment circuit 21 to the outside of the device via the output buffer 14.

FIG. 23 shows a modification of the embodiment using the skew reduction circuit according to the present invention as an output interface circuit. 23, the same elements as those of FIG. 22 are referred to by the same numerals, and a description thereof will be omitted. The skew reduction circuit in FIG. 23 is supplied with the clock signal CLK and the internal signal SI from an internal circuit (for example, the core circuit 302 in FIG. 20). On the basis of the clock signal CLK, the rising edge included in the clock signal CLK and the internal signal SI
Reduce falling skew. The internal signal SI1 whose rising / falling skew has been reduced is output from the phase adjustment circuit 21 to the outside of the device via the output buffer 14-1.

The output buffers 14-2 and 14-3, which are the same as the output buffer 14-1, output the clock signal CLK1.
And the inverted clock signal / CLK1. Outputs from the output buffers 14-2 and 14-3 are input to the period comparison circuit 12 via the input buffer 13.
The configuration of FIG. 23 uses the same output buffers 14-2 and 14-3 as the output buffer 14-1 in order to prevent the output signal from containing rising / falling skew due to the output buffer 14-1. Included in the feedback loop for adjustment. That is, the configuration of FIG.
The rising / falling skew of the clock signal CLK1 and the inverted clock signal / CLK1 after passing through the output buffers 14-2 and 14-3 is reduced. As a result, the rising / falling skew of the output signal after passing through the output buffer 14-1 can be reduced. Note that, in the configuration of FIG.
The rise / fall skew generated at
It is assumed to be negligible.

Although the present invention has been described based on the embodiments, the present invention is not limited to the above embodiments.
Various modifications and changes are possible within the scope described in the claims.

[0091]

According to the first to thirteenth aspects of the present invention, the period in which the clock signal is at the HIGH level and the period in which the clock signal is at the LOW level are compared, and the rising edge of the clock signal and the period during which the clock signal is at the same level are the same. By adjusting the phase of the falling edge, the rising / falling skew of the clock signal can be reduced. Also, by applying the same phase adjustment as that applied to the clock signal to other signals, it is possible to reduce the rise / fall skew in other signals. The phase adjustment of the rising edge and the falling edge can be easily realized by adjusting the transition time of each edge, and the transition time can be adjusted by changing the signal driving force. With the circuit described above, the phase adjustment function can be realized. During the period when the clock signal is at the HIGH level or the period when the clock signal is at the LOW level, a predetermined signal is propagated through the delay element array, and the period can be measured by the number of delay elements through which the signal passes. Therefore, the period measurement / comparison can be realized by a circuit having a relatively simple configuration. Claim 1
In the inventions of 4 to 15, in the input circuit of the semiconductor device, a period in which the clock signal input from the outside is at the HIGH level and a period in which the clock signal is at the LOW level are compared so that the two periods are the same. By adjusting the phases of the rising edge and the falling edge of the clock signal, the skew of the rising / falling edge of the clock signal can be reduced, and the same phase adjustment as that applied to the clock signal can be performed on other inputs. By applying to signals, rise / fall skew in other input signals can be reduced.

According to the present invention, in the output circuit of the semiconductor device, the period in which the clock signal supplied from the internal circuit is at the HIGH level and the period in which the clock signal is at the LOW level are compared. By adjusting the phase of the rising edge and the falling edge of the clock signal so that the period is the same, and applying the same phase adjustment to the output signal as the phase adjustment applied to the clock signal, the rising edge of the output signal / Fall skew can be reduced.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a skew reduction circuit according to the principle of the present invention.

FIG. 2 is a configuration diagram when a skew reduction circuit according to the principle of the present invention is applied to skew reduction of signals other than a clock signal.

FIG. 3 is a configuration diagram of an embodiment of a skew reduction circuit according to the present invention.

FIG. 4 is a timing chart showing each signal shown in FIG. 3;

FIG. 5 is a circuit diagram of a first embodiment of the period measurement circuit of FIG. 3;

FIG. 6 shows signals S7, S8, S9, S10 and S in FIG.
FIG.

FIG. 7 is a circuit diagram of the shift register of FIG. 3;

FIG. 8 is a circuit diagram of the phase adjustment circuit of FIG. 3;

FIG. 9 is a circuit diagram showing a modification of the phase adjustment circuit.

FIG. 10 is a circuit diagram showing a further modification of the phase adjustment circuit.

FIG. 11 is a circuit diagram of a second embodiment of the period measurement circuit.

FIG. 12 is a circuit diagram of a third embodiment of the period measurement circuit.

FIG. 13 is a circuit diagram of a fourth embodiment of the period measurement circuit.

FIG. 14 is a circuit diagram of a fifth embodiment of the period measurement circuit.

FIG. 15 is a circuit diagram of a sixth embodiment of the period measurement circuit.

FIG. 16 is a circuit diagram of a seventh embodiment of the period measurement circuit.

FIG. 17 is a circuit diagram of an eighth embodiment of the period measurement circuit.

FIG. 18 is a circuit diagram of a ninth embodiment of the period measurement circuit.

FIG. 19 is a timing chart for explaining the operation of the period measurement circuit of FIG. 18;

FIG. 20 is a diagram illustrating a configuration in a case where a skew reduction circuit according to the present invention is applied to a semiconductor device.

FIG. 21 is a configuration diagram when a skew reduction circuit according to the present invention is used as an input interface circuit for signal input.

FIG. 22 is a configuration diagram when a skew reduction circuit according to the present invention is used as an output interface circuit for signal output.

FIG. 23 is a configuration diagram showing a modification when the skew reduction circuit according to the present invention is used as an output interface circuit.

FIGS. 24A and 24B are diagrams for explaining rising / falling skew in a clock signal.

[Explanation of symbols]

11, 11A Phase adjustment circuit 12 Period comparison circuit 13 Input buffer 14, 14-1, 14-2, 14-3 Output buffer 21 Phase adjustment circuit 22 Shift register 23-1, 23-2, 23-3, 23-4 Edge detection circuit 24 Period measurement circuit 25 Binary counter 300 Semiconductor device 301 Input circuit 302 Core circuit 303 Output circuit

Claims (17)

[Claims] A first phase adjustment circuit for adjusting a phase with respect to a rising edge and a falling edge of a signal; receiving the signal whose phase has been adjusted from the first phase adjustment circuit; A first period until the falling edge is compared with a second period from the falling edge to the rising edge, and the first phase is set so that the first period and the second period are the same. A circuit including a period comparison circuit for controlling an adjustment circuit. 2. The apparatus according to claim 1, wherein the first phase adjustment circuit adjusts a phase by adjusting a transition time between the rising edge and the falling edge.
The described circuit. A second phase adjusting circuit for adjusting a phase with respect to a rising edge and a falling edge of a signal different from the signal, wherein the period comparing circuit has the same control as that for the first phase adjusting circuit. 2. The circuit according to claim 1, wherein said control is performed on said second phase adjustment circuit. 4. The period comparison circuit, comprising: a first measurement circuit for measuring the first period; a second measurement circuit for measuring the second period; and a measurement result of the first measurement circuit. 2. The circuit according to claim 1, further comprising a measurement result comparison circuit that compares the measurement result of the second measurement circuit with the measurement result. 5. The first measuring circuit includes a first delay element row including a plurality of delay elements, and a delay through which a signal propagating through the first delay element row passes within the first period. The first period is measured based on the number of elements, and the second measurement circuit includes a second delay element row including a plurality of delay elements, and a signal propagating through the second delay element row receives the second delay element row. 5. The circuit according to claim 4, wherein the second period is measured based on the number of delay elements passing in the second period. 6. The first measuring circuit, wherein a latch corresponding to a delay element through which a signal has passed during the first period holds a first level, and other latches hold a second level. The semiconductor device further includes a first latch array including latches corresponding to the respective delay elements of the first delay element array, and the second measurement circuit corresponds to a delay element through which a signal has passed during the second period. The latch holds a first level and the other latches hold a second level. The second latch includes a latch corresponding to each delay element in the second delay element row.
The measurement result comparison circuit associates the first latch column with the second latch column for each latch, and stores information on a difference in level held by the latch between the corresponding latches. 6. The circuit according to claim 5, further comprising a circuit for comparing the first period and the second period based on the first period. 7. The period comparison circuit, comprising: a first circuit measuring the first period; and a time having the same length as the first period measured by the first circuit from the falling edge. 2. The circuit according to claim 1, further comprising: a second circuit for indicating that the time has elapsed, and a third circuit for comparing a front-rear relationship between a time indicated by the second circuit and the rising edge. . 8. The period comparison circuit, comprising: a first circuit measuring the second period; and a time having the same length as the second period measured by the first circuit from the rising edge. 2. The circuit according to claim 1, further comprising a second circuit for indicating that the elapsed time has elapsed, and a third circuit for comparing a front-and-rear relationship between the time indicated by the second circuit and the falling edge. . 9. The first phase adjustment circuit includes: an edge adjustment circuit that changes a phase of the rising edge and a phase of the falling edge; and a parameter that determines a phase change amount of the edge adjustment circuit. 2. The circuit according to claim 1, further comprising a phase change amount holding circuit for holding and sequentially updating the parameter based on a magnitude relationship between the first period and the second period. 10. The circuit according to claim 9, wherein said phase change amount holding circuit is a shift register. 11. The edge adjusting circuit receives the signal as an input, changes an output at a first transition time in response to the rising edge, and changes an output in a second transition time in response to the falling edge. The circuit according to claim 9, wherein the first transition time and the second transition time can be adjusted by changing the first and second transition times. 12. The apparatus according to claim 11, wherein said edge adjusting circuit changes said first transition time and said second transition time by changing a driving force for driving an output signal. circuit. 13. An edge adjustment circuit comprising: an inverter including at least one PMOS transistor and at least one NMOS transistor; a plurality of first transistors inserted between the at least one PMOS transistor and a power supply voltage; A plurality of second transistors inserted between the at least one NMOS transistor and a ground voltage, wherein the number of transistors to be turned on among the first transistors and the transistor to be turned on among the second transistors 13. The circuit of claim 12, wherein changing the number changes the phase of the rising edge and the phase of the falling edge. 14. A first input buffer for receiving an externally input clock signal, and a first phase for adjusting a phase with respect to a rising edge and a falling edge of the clock signal supplied from the first input buffer. An adjusting circuit, receiving the clock signal whose phase has been adjusted from the first phase adjusting circuit, a first period from the rising edge to the falling edge, and a second period from the falling edge to the rising edge. And a period comparison circuit for controlling the first phase adjustment circuit so that the first period and the second period are the same. 15. A second input buffer for receiving an externally input signal separately from the clock signal, and adjusting a phase with respect to a rising edge and a falling edge of the signal supplied from the second input buffer. A second phase adjustment circuit, wherein the period comparison circuit performs the same control as the control on the first phase adjustment circuit by the second phase adjustment circuit;
15. The semiconductor device according to claim 14, wherein the semiconductor device is applied to the phase adjusting circuit. 16. A first phase adjustment circuit for adjusting a phase with respect to a rising edge and a falling edge of a clock signal supplied from the inside, and receiving the clock signal whose phase has been adjusted from the first phase adjustment circuit. Comparing a first period from the rising edge to the falling edge with a second period from the falling edge to the rising edge, wherein the first and second periods are the same. A period comparison circuit that controls the first phase adjustment circuit, a second phase adjustment circuit that adjusts the phase with respect to the rising edge and the falling edge of a signal supplied from inside separately from the clock signal, An output buffer for outputting the signal whose phase has been adjusted by the second phase adjustment circuit to the outside, wherein the period comparison circuit controls the first phase adjustment circuit; Wherein a is subjected to one control to the phase adjustment circuit of the second. 17. The semiconductor device according to claim 16, further comprising an output buffer and an input buffer provided between said first phase adjustment circuit and said period comparison circuit.