JP3708284B2 - Skew reduction circuit and semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention generally relates to an interface circuit, and more particularly to an input / output interface circuit of a semiconductor device.
[0002]
[Prior art]
In a semiconductor device, it is desired to realize high-speed operation by inputting / outputting data using a high-frequency signal. However, if the frequency of the data input / output signal is increased with the aim of higher-speed operation, the factors that determine the signal frequency become obvious, and it is necessary to eliminate these factors.
[0003]
[Problems to be solved by the invention]
A major factor that determines the frequency of data input / output signals is signal skew, that is, signal timing shift. For example, if there is a skew in the input clock signal for synchronization, there is a possibility that when a signal is captured using the timing of the clock signal, an erroneous signal is captured due to a timing shift. Since this possibility increases as the signal frequency increases, it becomes difficult to increase the operation speed by increasing the signal frequency when there is a skew in the signal.
[0004]
There are several types of skews, but as a type of skew for which no effective countermeasure has been taken in the past, there are signal rising and falling skews. This means that the rising timing and falling timing of the signal deviate from the desired timing.
FIGS. 16A and 16B are diagrams for explaining the rising / falling skew in the clock signal. FIG. 16A shows a case where there is no rising / falling skew, and FIG. 16B shows a case where there is a rising / falling skew. 16A and 16B, the reference reference voltage Vref used for comparison by the reception input buffer is shown together with the clock signal. Further, by comparing the clock signal with the reference reference voltage Vref, a period in which the clock signal is recognized as HIGH level is indicated as High, and a period in which the clock signal is recognized as LOW level is indicated as Tlow.
[0005]
FIG. 16B shows a case where there is a skew in the clock signal, the rising transition time is short (rise is steep), and the falling transition time is long (falling is slow). In this case, each of the period High and the period Tlow deviates from the period illustrated in FIG. This means that the length of each period deviates from the normal length, and the rising / falling timing deviates from the normal timing.
[0006]
If the rising / falling timing of the synchronization clock signal is shifted, there is a possibility that the signal is erroneously read when another signal is read. In addition, when a rising / falling skew is present in a signal such as a data signal, the effective period during which data is considered valid is limited to the shorter of the periods High and Tlow. For these reasons, when there is a rising / falling skew, it is difficult to increase the operation speed by increasing the frequency of the input / output signal.
[0007]
There are several causes for such rise / fall skew. First, in the signal output circuit on the output side, since the rise / fall transition times are different from each other due to the difference in circuit characteristics, the rise / fall skew is already included at the time of signal output. In the input buffer on the input side, if the reference reference voltage Vref to be compared with the signal input fluctuates for some reason, the period High and the period Tlow change. Furthermore, the rise / fall transition times differ from each other due to differences in circuit characteristics in the input buffer, which also causes rise / fall skew.
[0008]
These rise / fall skew factors are generally considered to have the same effect on each signal. This is because an output buffer and an input buffer having the same design are generally used for each signal, and the reference reference voltage Vref is commonly used. Therefore, it can be said that the rising / falling skew is a skew common to each signal.
[0009]
Conventionally, the signal frequency used was not so high, and as a countermeasure against the rising / falling skew, the circuit was designed to reduce the rising / falling skew. However, such measures are insufficient, and it is necessary to reduce the rising / falling skew, particularly in order to realize a higher speed operation by increasing the signal frequency.
[0010]
Accordingly, it is an object of the present invention to provide a circuit that reduces rising / falling skew.
[0014]
[Means for Solving the Problems]
Claim 1 In the invention, the first phase adjustment circuit for adjusting the phase with respect to the rising edge and the falling edge of the first signal, and the first signal whose phase is adjusted from the first phase adjustment circuit And a timing detection circuit that controls the first phase adjustment circuit so that a relative phase relationship between the rising edge and the falling edge becomes a predetermined phase relationship, and the first signal is a clock signal. The timing detection circuit controls the first phase adjustment circuit to control the first phase adjustment circuit so that a period in which the first signal is at a HIGH level and a period in which the first signal is at a LOW level are substantially the same. The circuit receives the clock signal and a complementary clock signal that is 180 degrees out of phase with the clock signal, and the timing detection circuit receives one of the clock signal and the complementary clock signal as a third signal. A signal, an inverted signal of the other signal is a fourth signal, and the first phase adjustment circuit is controlled so that the third signal and the fourth signal have the same phase. To do.
[0015]
Claim 2 In the invention of claim 1 In the described circuit, the timing detection circuit includes a frequency divider that divides the third signal and the fourth signal, and a circuit that determines a front-to-back relationship of edges between the divided signals. It is characterized by including. Claim 3 In the invention of claim 2 In the described circuit, the first phase adjustment circuit changes an edge adjustment circuit that changes a phase of the rising edge and changes a phase of the falling edge, and determines a phase change amount of the edge adjustment circuit. It includes a phase change amount holding circuit that holds a parameter and sequentially updates the parameter based on the context of the edge.
[0016]
Claim 4 In the invention, the claims 3 In the described circuit, the phase change amount holding circuit is a shift register. Claim 5 In the invention of claim 3 In the circuit described above, the edge adjustment circuit receives the first signal as an input, changes an output corresponding to the rising edge in a first transition time, and outputs an output corresponding to the falling edge. It is possible to adjust the first transition time and the second transition time by changing the second transition time.
[0017]
Claim 6 In the invention of claim 5 In the described circuit, the edge adjustment circuit changes the first transition time and the second transition time by changing a driving force for driving an output signal. Claim 7 In the invention of claim 6 In the described circuit, the edge adjustment circuit includes an inverter including at least one PMOS transistor and at least one NMOS transistor, and a plurality of first transistors inserted between the at least one PMOS transistor and a power supply voltage. A transistor, and a plurality of second transistors inserted between the at least one NMOS transistor and a ground voltage, the number of transistors to be conducted among the first transistors and the conduction among the second transistors By changing the number of transistors to be changed, the phase of the rising edge is changed and the phase of the falling edge is changed.
[0022]
Claims 1 to 7 In this invention, the rising edge of the clock signal is adjusted by adjusting the phase of the rising edge and the falling edge of the clock signal so that the period when the clock signal is at the HIGH level and the period when the clock signal is at the LOW level are the same. / Falling skew can be reduced. Further, by applying the same phase adjustment as the phase adjustment applied to the clock signal to other signals, it is possible to reduce the rising / falling skew in the other signals. The phase adjustment of the rising edge and falling edge can be easily realized by adjusting the transition time of each edge, and the transition time can be adjusted by changing the signal driving force. The phase adjustment function can be realized with this circuit.
[0025]
DETAILED DESCRIPTION OF THE INVENTION
The principles and embodiments of the present invention will be described below with reference to the accompanying drawings.
FIG. 1 shows the configuration of a skew reduction circuit according to the principle of the present invention. The skew reduction circuit 10 in FIG. 1 includes a phase adjustment circuit 11 and a timing detection circuit 12. The phase adjustment circuit 11 receives the clock signal information and adjusts the phase of the clock signal information to output a clock signal whose phase is adjusted. The clock signal whose phase has been adjusted is input to the timing detection circuit 12. The timing detection circuit 12 detects the relative timing of the rising edge and the falling edge of the clock signal whose phase has been adjusted, and the phase adjustment circuit 11 so that a predetermined phase relationship is satisfied between the rising edge and the falling edge. To control. Specifically, the timing detection circuit 12 controls the phase adjustment circuit 11 so that the HIGH period High and the LOW period Tlow of the clock signal output from the phase adjustment circuit 11 are adjusted to be equal.
[0026]
The phase adjustment circuit 11 has a function of adjusting the rising timing and falling timing of the clock signal in different directions. That is, the control for relatively advancing or delaying the rising timing and the control for relatively advancing or delaying the falling timing can be performed in different directions between the rising and falling. For example, it is possible to relatively advance the falling timing while relatively delaying the rising timing. By such adjustment, the HIGH period High and the LOW period Tlow of the clock signal can be adjusted to be equal.
[0027]
As described above, the timing detection circuit 12 detects the relative timing of the rising edge and falling edge of the clock signal whose phase has been adjusted, and controls the phase adjustment circuit 11 based on the detected timing. For example, based on the relative timing of the rising edge and the falling edge, it is determined which period is longer between the HIGH period High and the LOW period Tlow, and the phase adjustment circuit 11 is controlled based on this. Good.
[0028]
FIG. 2 shows a configuration in which the skew reduction circuit 10 according to the principle of the present invention is applied to the skew reduction of signals other than the clock signal. In FIG. 2, the control signal from the timing detection circuit 12 is supplied not only to the phase adjustment circuit 11 that receives clock signal information but also to another phase adjustment circuit 11A that receives another signal. The phase adjustment circuit 11A performs the same phase adjustment as the phase adjustment circuit 11 on the input signal.
[0029]
As described above, the rise / fall skew factor is generally the same for each signal, and the rise / fall skew is common to each signal. Therefore, if the phase adjustment for reducing the rising / falling skew of the clock signal is applied to a signal other than the clock signal as shown in FIG. 2, the rising / falling skew is also applied to this signal. Can be reduced. In this way, the rising / falling skew of other signals can be reduced based on the clock signal information.
[0030]
As described above, in the present invention, the skew reduction circuit includes the phase adjustment circuit that adjusts the phase of the clock signal and the timing detection circuit that controls the phase adjustment circuit based on the relative timing of the rise and fall. By providing the clock signal, the clock signal can be adjusted so that the HIGH period High and the LOW period Tlow of the clock signal are equal to each other, and the rising / falling skew of the clock signal can be reduced. Furthermore, the rising / falling skew of other signals can be reduced based on the clock signal information by utilizing the fact that the rising / falling skew is common to each signal.
[0031]
Embodiments of the present invention will be described below with reference to the accompanying drawings.
FIG. 3 shows an embodiment of a skew reduction circuit according to the present invention. FIG. 4 is a timing chart showing the signals S0 to S9 shown in FIG. In FIG. 4, the left half of the figure shows the phase relationship between the signals before the adjustment is completed, and the right half of the figure shows the phase relationship between the signals after the adjustment.
[0032]
The skew reduction circuit of FIG. 3 receives three inputs of a clock signal CLK, an inverted clock signal / CLK (complementary signal of the clock signal CLK), and an input signal S0, and a signal S9 that reduces the rising / falling skew of the input signal S0. Then, the signal S5 in which the rising / falling skew of the clock signal CLK is reduced is output.
The skew reduction circuit in FIG. 3 includes a phase adjustment circuit 11B that integrates the phase adjustment circuits 11 and 11A in FIG. 2, a timing detection circuit 12, and a plurality of input buffers 13-1 to 13-3. The plurality of input buffers 13-1 to 13-3 are provided for each of the input signal S0, the clock signal CLK, and the inverted clock signal / CLK, and the signals S3, S1, and S2 correspond to the signals. Is output. As shown in FIG. 4, the clock signal CLK, the inverted clock signal / CLK, and the input signal S0 are signals with different rising / falling transition times, and the signals S1 to S3 detected by the input buffer are: The periods High and Tlow are signals different from each other. These signals S1 to S3 are input to the phase adjustment circuit 11B.
[0033]
The phase adjustment circuit 11B includes a plurality of phase adjustment circuits 21-1 to 21-3 and a shift register 22 that controls the phase adjustment circuits 21-1 to 21-3. Each of the phase adjustment circuits 21-1 to 21-3 adjusts the phases of the input signals S3, S1, and S2, and outputs the signals S9, S5, and S7 whose phases are adjusted. That is, the signal S9 is a signal after the phase adjustment of the input signal S0, the signal S5 is a signal after the phase adjustment of the clock signal CLK, and the signal S7 is a signal after the phase adjustment of the inverted clock signal / CLK. Here, the phase adjustment circuits 21-1 to 21-3 are configured to output complementary signals that are inverted with respect to each other as outputs, and are an inverted signal S8 of the signal S9, an inverted signal S4 of the signal S5, and an inverted signal of the signal S7. S6 is output.
[0034]
The signal S5 after the phase adjustment of the clock signal CLK output from the phase adjustment circuit 11B and the inverted signal S6 of the signal after the phase adjustment of the inverted clock signal / CLK are input to the timing detection circuit 12.
The timing detection circuit 12 includes a frequency divider 23, a phase comparison circuit 25, a binary counter 24, NAND circuits 31 to 34, and inverters 35 to 38. The operation of the timing detection circuit 12 will be described in detail later. Schematically, the timing detection circuit 12 detects the timing relationship between the rising edges of the signal S5 and the signal S6 as shown in FIG. 4, and whether the rising edge of the signal S5 is ahead of the rising edge of the signal S6. Determine if you are late. An output from the timing detection circuit 12 indicating the determination result is input to the shift register 22 of the phase adjustment circuit 11B.
[0035]
When the rising edge of the signal S5 is advanced from the rising edge of the signal S6, the shift register 22 sets the phase adjustment circuits 21-1 to 21-3 so that the rising edge of the signal S5 is delayed and the falling edge is advanced. Control. Conversely, as shown in FIG. 4, when the rising edge of the signal S5 is delayed from the rising edge of the signal S6, the phase adjustment circuit 21- is set so that the rising edge of the signal S5 advances and the falling edge is delayed. 1 to 21-3 are controlled.
[0036]
FIG. 5 is a diagram for explaining this phase adjustment. FIG. 5 shows a case where the rising edge of the signal S5 is delayed from the rising edge of the signal S6, as in FIG. Signal S5 is a signal corresponding to clock signal CLK, and signal S6 is a signal obtained by inverting signal S7 corresponding to inverted clock signal / CLK. Therefore, when there is no rising / falling skew in the clock signal CLK, the signal S5 and the signal S6 should be the same signal. As shown in FIG. 5, when the rising edge of the signal S5 is behind the rising edge of the signal S6, the period High of the signal S5 is shorter than the correct period (1/2 cycle), while the period Tlow is the correct period. It shows that it is longer than (1/2 cycle). Therefore, the signal S5 is adjusted so that the rising edge is advanced and the falling edge is delayed. At this time, among the signals S4 to S9, the non-inverted signals S5, S7, and S9 are adjusted in the same manner. Therefore, in the inverted signals S4, S6, and S8, the rising edge has a delayed falling edge. It will be adjusted to go forward. Accordingly, when the signal S5 and the signal S6 are adjusted so that the rising edges are aligned, the correct periods High and Tlow are obtained.
[0037]
By this control, as shown in the right half of FIG. 4, the rising edges of the signal S5 and the signal S6 are aligned, and the periods High and Tlow are adjusted to be equal in each of S4 to S9.
Hereinafter, each component of the skew reduction circuit of FIG. 3 will be described.
FIG. 6 shows a circuit configuration of the input buffer 13 corresponding to the input buffers 13-1 to 13-3. That is, the input buffer 13 of FIG. 6 is used as each of the input buffers 13-1 to 13-3.
[0038]
The input buffer 13 includes PMOS transistors 71 and 72, NMOS transistors 73 to 77, and an inverter 78. The signal input voltage is compared with the reference reference voltage Vref, and when the signal input voltage is larger, the signal output is output. When HIGH and the signal input voltage is smaller, the signal output is LOW. Since the input buffer 13 is a current mirror buffer that is usually used and is a conventional one, detailed description thereof is omitted.
[0039]
FIG. 7 shows the configuration of the frequency divider 23 of the timing detection circuit 12 of FIG. The frequency divider 23 includes two identical frequency dividers 26 that divide the input frequency by half. The frequency divider 26 includes NAND circuits 81 to 88 and inverters 89 and 90. One frequency divider 26 receives the signal S5 and outputs a signal whose frequency is divided by half. The other frequency divider 26 receives the signal S6 and outputs a signal whose frequency is divided by half. The frequency divider 23 divides the signal S5 and the signal S6 that are signal inputs to the timing detection circuit 12, thereby facilitating timing comparison between the rising edges of the two. In other words, since the period of each signal becomes longer by dividing the frequency, the edges between the signals S5 and S6 are not erroneously associated with each other, and the timing comparison can be reliably performed between the correctly corresponding edges. Since the 1/2 frequency divider 26 is within the range of the prior art, a detailed description of its operation is omitted.
[0040]
With reference to FIG. 3 again, the operation of the timing detection circuit 12 will be described below. FIG. 8 is a timing chart showing signal changes at the nodes N1 to N9 in the timing detection circuit 12 shown in FIG.
The signals S5 and S6 (N1 and N2 in FIG. 8) input to the timing detection circuit 12 are divided by 1/2 by the frequency divider 23 to become signals indicated by N3 and N4 in FIG. As shown in FIG. 8, the edge to be compared in the output of the frequency divider 23 is a falling edge. The signals N3 and N4 are input to the phase comparison circuit 25.
[0041]
The phase comparison circuit 25 includes NAND circuits 41 to 45 and inverters 46 to 49. NAND circuits 44 and 45 constitute a latch, and as shown in FIG. 3, in the initial state, two inputs are LOW and two outputs are HIGH. As shown in FIG. 8, since the falling edge to be compared is earlier for the N4 signal, the output of the NAND circuit 43 becomes HIGH before the output of the NAND circuit 42. Accordingly, the output of the NAND circuit 45 becomes LOW, and the output of the NAND circuit 44 remains HIGH. Since this state is latched, the state does not change even if the output of the NAND circuit 42 becomes HIGH due to the falling edge of the N3 signal. Therefore, the signal N5, which is the output of the phase comparison circuit 25, remains LOW, and the signal N6 changes from LOW to HIGH. If the falling edge to be compared is N3 earlier, the N5 signal changes to HIGH, and the N6 signal remains LOW.
[0042]
Therefore, it is possible to determine which of the rising edges of the input signals S5 and S6 to the phase detector precedes which of the N5 signal and the N6 signal becomes HIGH. When the signal of N5 becomes HIGH, it indicates that the rising edge of the signal S5 is preceded, and when the signal of N6 becomes HIGH, it indicates that the rising edge of the signal S6 is preceded. In other words, when the signal N5 becomes HIGH, it is necessary to delay the rising edge of the signal S5. When the signal N6 becomes HIGH, the rising edge of the signal S5 needs to be advanced.
[0043]
Here, the signal from the inverter 46 serves to return the latch state to the initial state by simultaneously setting the outputs of the NAND circuits 42 and 43 to LOW at an appropriate timing. Otherwise, after the outputs of the NAND circuits 42 and 43 become HIGH, the signal of N4 returns to HIGH before the signal of N3, so that the latch state is reversed, and the signal of N5 becomes HIGH. turn into. In order to avoid this, the outputs of the NAND circuits 42 and 43 are simultaneously set to LOW.
[0044]
As shown in FIG. 8, the N7 signal is a NAND of the N3 signal and the N4 signal (the delay is ignored in the figure). The N7 signal is supplied to the binary counter 24. N8 and N9 are outputs of the binary counter 24, and a signal obtained by dividing the N7 signal by 1/2 and its inverted signal appear.
The binary counter 24 includes NAND circuits 51 to 58 and inverters 59 to 61. Since the operation is within the range of the prior art, the description is omitted. The output of the binary counter 24 is shown at N8 and N9 in FIG.
[0045]
The signal N5 is supplied to the NAND circuits 31 and 32, and the signal N6 is supplied to the NAND circuits 33 and 34. The other input of the NAND circuits 31 and 33 is supplied with an N8 signal that is the output of the binary counter 24, and the other input of the NAND circuits 32 and 34 is an N9 signal that is the output of the binary counter 24. Is supplied.
[0046]
Therefore, as shown in FIG. 8, when the N6 signal becomes HIGH, the inverters 37 and 38 that invert the outputs of the NAND circuits 33 and 34 alternately output the N6 HIGH pulse. . That is, the pulse P1 shown in FIG. 8 passes through the NAND circuit 33 and the inverter 37 opened by the signal N8, and the pulse P2 passes through the NAND circuit 34 and the inverter 38 opened by the signal N9. Is output. The same applies to the case where the signal N5 becomes HIGH, and HIGH pulses are alternately output from the inverters 35 and 36.
[0047]
Therefore, when it is necessary to delay the rising edge of the signal S5, HIGH pulses are alternately output from the inverters 35 and 36, and when it is necessary to advance the rising edge of the signal S5, the HIGH signals from the inverters 37 and 38 are output. Pulses are output alternately. These pulse signals are supplied to the shift register 22 of FIG.
[0048]
FIG. 9 shows a circuit diagram of the shift register 22. The shift register 22 includes inverters 101-1 to 101-8, inverters 102-1 to 102-8, NAND circuits 103-1 to 103-8, NMOS transistors 104-1 to 104-8, and NMOS transistors 105-1 to 105-8. -8, NMOS transistors 106-1 to 106-8, and NMOS transistors 107-1 to 107-8. When the reset signal RESET is set to LOW, the shift register 22 is reset. That is, when the reset signal RESET becomes LOW, the outputs of the NAND circuits 103-1 to 103-8 become HIGH, and the outputs of the inverters 102-1 to 102-8 become LOW. Each pair of the NAND circuits 103-1 to 103-8 and the inverters 102-1 to 102-8 forms a latch by using their outputs as inputs. Therefore, the initial state set by the reset signal RESET is maintained even when the reset signal RESET returns to HIGH.
[0049]
In this initial state, as shown in FIG. 9, the outputs Q1 to Q4 of the inverters 101-1 to 101-4 are HIGH, and the outputs Q5 to Q8 of the inverters 101-5 to 101-8 are LOW.
When it is necessary to delay the rising edge of the signal S5, HIGH pulses are alternately supplied to the signal lines A and B. First, when a HIGH pulse is supplied to the signal line B, the NMOS transistor 104-5 is turned on. At this time, since the NMOS transistor 106-5 is on, the output of the NAND circuit 103-5 is connected to the ground, and is forcibly changed from HIGH to LOW. Therefore, the output of the inverter 102-5 becomes HIGH, and this state is held in the latch composed of the NAND circuit 103-5 and the inverter 102-5. At this time, the output Q5 changes from LOW to HIGH. Therefore, in this state, the outputs Q1 to Q5 are HIGH and the outputs Q6 to Q8 are LOW.
[0050]
Next, when a HIGH pulse is supplied to the signal line A, the NMOS transistor 104-6 is turned on. At this time, since the NMOS transistor 106-6 is on, the output of the NAND circuit 103-6 is connected to the ground and is forcibly changed from HIGH to LOW. Therefore, the output of the inverter 102-6 becomes HIGH, and this state is held in the latch composed of the NAND circuit 103-6 and the inverter 102-6. At this time, the output Q6 changes from LOW to HIGH. Therefore, in this state, the outputs Q1 to Q6 are HIGH, and the outputs Q7 and Q8 are LOW.
[0051]
Thus, by alternately supplying HIGH pulses to the signal lines A and B, the number of HIGH outputs among the outputs Q1 to Q8 can be increased one by one. Of the outputs Q1 to Q8, HIGH outputs are grouped on the left side, and LOW outputs are grouped on the right side.
When the rising edge of the signal S5 needs to be advanced, HIGH pulses are alternately supplied to the signal lines C and D. First, in the initial state shown in FIG. 9, when a HIGH pulse is supplied to the signal line C, the NMOS transistor 105-4 is turned on. At this time, since the NMOS transistor 107-4 is on, the output of the NAND circuit 103-4 is connected to the ground and is forcibly changed from HIGH to LOW. Therefore, the output of the inverter 102-4 becomes HIGH, and this state is held in the latch composed of the NAND circuit 103-4 and the inverter 102-4. At this time, the output Q4 changes from HIGH to LOW. Therefore, in this state, the outputs Q1 to Q3 are HIGH and the outputs Q4 to Q8 are LOW.
[0052]
Next, when a HIGH pulse is supplied to the signal line D, the NMOS transistor 105-3 is turned on. At this time, since the NMOS transistor 107-3 is on, the output of the NAND circuit 103-3 is connected to the ground, and is forcibly changed from HIGH to LOW. Therefore, the output of the inverter 102-3 becomes HIGH, and this state is held in the latch composed of the NAND circuit 103-3 and the inverter 102-3. At this time, the output Q3 changes from HIGH to LOW. Therefore, in this state, the outputs Q1 to Q2 are HIGH, and the outputs Q3 and Q8 are LOW.
[0053]
Thus, by alternately supplying the HIGH pulses to the signal lines C and D, the number of outputs that are LOW among the outputs Q1 to Q8 can be increased one by one. Of the outputs Q1 to Q8, HIGH outputs are grouped on the left side, and LOW outputs are grouped on the right side.
By supplying these output signals Q1 to Q8 to the phase adjustment circuits 21-1 to 21-3, the phase of the signal is adjusted.
[0054]
FIG. 10 shows the phase adjustment circuit 21 corresponding to the phase adjustment circuits 21-1 to 21-3. That is, the phase adjustment circuit 21 is used as each of the phase adjustment circuits 21-1 to 21-3.
The phase adjustment circuit 21 includes PMOS transistors 111-1 to 111-8, PMOS transistors 112-0 to 112-8, NMOS transistors 113-0 to 113-8, NMOS transistors 114-1 to 114-8, and inverters 115 to 120 is included.
[0055]
Signals Q1 to Q8 from the shift register 22 are input to the gates of the PMOS transistors 111-1 to 111-8 and the NMOS transistors 114-1 to 114-8, respectively. The PMOS transistors 112-0 to 112-8 and the NMOS transistors 113-0 to 113-8 form an inverter as a whole by using the input signal as a gate input. Therefore, a signal whose phase relationship with the input signal is inverted is output as the output signal / OUT, and a signal having the same phase relationship as the input signal is output as the output signal OUT.
[0056]
In an initial state in which the signals Q1 to Q4 are HIGH and the signals Q5 to Q8 are LOW, the PMOS transistors 111-1 to 111-4 are on on the power supply voltage side and the NMOS transistors 114-5 to 114 are on the ground voltage side. 114-8 is on. Therefore, when the input signal becomes HIGH, a total of five NMOS transistors 113-0 to 113-4 are driven. When the input signal becomes LOW, a total of five PMOS transistors 112-0 and 112-5 to 112-8 are driven. Therefore, the driving force corresponding to the rising edge of the input signal is equal to the driving force corresponding to the falling edge.
[0057]
Here, when the number of HIGH signals among the signals Q1 to Q8 increases, the number of NMOS transistors to be driven increases, the driving force corresponding to the rising edge of the input signal increases, and the driven PMOS transistor. And the driving force corresponding to the falling edge of the input signal is reduced. Therefore, the transition time of the rising edge of the input signal is shortened, and as a result, the rising edge advances. Further, since the transition time of the falling edge of the input signal becomes long, the falling edge is delayed as a result.
[0058]
On the contrary, when the number of HIGH signals among the signals Q1 to Q8 decreases, the number of NMOS transistors to be driven decreases, the driving force corresponding to the rising edge of the input signal decreases, and the driven PMOS transistor. And the driving force corresponding to the falling edge of the input signal increases. Therefore, the transition time of the rising edge of the input signal becomes long, and as a result, the rising edge is delayed. Also, since the transition time of the falling edge of the input signal is shortened, the falling edge is advanced as a result.
[0059]
As described above, the timing detection circuit 12 determines which leading edge precedes the signal S5 and the signal S6, and based on the result of this determination, among the output signals Q1 to Q8 of the shift register 22, HIGH Adjust the number of signals that are In accordance with the number of signals that are HIGH among the signals Q1 to Q8, the phase adjustment circuits 21-1 to 21-3 change the driving force for the rising edge and the driving force for the falling edge. Thus, the timing of the rising edge and the falling edge of each signal can be adjusted so that the period High and the period Tlow of the clock signal CLK are equal.
[0060]
FIG. 11 shows a modification of the phase adjustment circuit 21. In FIG. 11, the same components as those of FIG. 10 are referred to by the same numerals. In the phase adjustment circuit 21A of FIG. 11, the PMOS transistors 112-0 and 112-1 and the NMOS transistors 113-0 and 113-1 form one inverter.
When the number of signals that are HIGH among the signals Q1 to Q8 increases, the number of transistors that are turned on among the PMOS transistors 111-1 to 111-8 decreases. Therefore, the resistance value that is interposed on the power supply voltage side of the inverter Becomes larger and the input signal falls slowly. Further, since the number of transistors that are turned on among the NMOS transistors 114-1 to 114-8 increases, the resistance value interposed on the ground side of the inverter decreases, and the rising of the input signal becomes steep. As a result, the rising edge is advanced and the falling edge is delayed.
[0061]
Conversely, when the number of HIGH signals among the signals Q1 to Q8 decreases, the rising edge of the signal is delayed and the falling edge is advanced.
FIG. 12 shows a further modification of the phase adjustment circuit 21. In FIG. 12, the same components as those in FIGS. 10 and 11 are referred to by the same numerals. In the phase adjustment circuit 21B of FIG. 12, the PMOS transistor 112-0 and the NMOS transistor 113-0 form one inverter.
[0062]
When the number of signals that are HIGH among the signals Q1 to Q8 increases, the number of transistors that become conductive among the PMOS transistors 111-0 to 111-8 decreases, so that the resistance value that is interposed on the power supply voltage side of the inverter Becomes larger and the input signal falls slowly. Further, since the number of transistors that are turned on among the NMOS transistors 114-0 to 114-8 is increased, the resistance value interposed on the ground side of the inverter is reduced, and the rising of the input signal becomes steep. As a result, the rising edge is advanced and the falling edge is delayed.
[0063]
Conversely, when the number of HIGH signals among the signals Q1 to Q8 decreases, the rising edge of the signal is delayed and the falling edge is advanced.
In FIG. 12, the PMOS transistor 111-0 and the NMOS transistor 114-0 are always in a conductive state. Accordingly, even if all of the signals Q1 to Q8 are LOW or all are HIGH, the operation of the inverter constituted by the PMOS transistor 112-0 and the NMOS transistor 113-0 is not stopped.
[0064]
Although the above embodiment shows an example in which the skew reduction circuit according to the present invention is used as an input interface for signal input, the skew reduction circuit according to the present invention may be used as an output interface for signal output.
FIG. 13 shows an example in which the skew reduction circuit according to the present invention is applied to a semiconductor device. A semiconductor device 200 in FIG. 13 includes an input circuit 201, a core circuit 202, and an output circuit 203. The input circuit 201 receives an input signal from the outside and supplies the received input signal to the core circuit 202. An output signal from the core circuit 202 is output to the outside of the semiconductor device 200 via the output circuit 203. In the above-described embodiment, a configuration in which the skew reduction circuit according to the present invention is used for, for example, the input circuit 201 is shown. However, the skew reduction circuit according to the present invention may be used as an output interface for signal output such as the output circuit 203.
[0065]
FIG. 14 shows an embodiment in which the skew reduction circuit according to the present invention is used as an output interface for signal output. 14, the same components as those in FIG. 3 are referred to by the same numerals, and a description thereof will be omitted.
The skew reduction circuit of FIG. 14 is supplied with a clock signal CLK, an inverted clock signal / CLK, and an internal signal used inside the apparatus. As in the previous embodiment, the rising / falling skew included in the clock signal CLK, the inverted clock signal / CLK, and the internal signal is reduced based on the information included in the clock signal CLK and the inverted clock signal / CLK. The internal signal with the rising / falling skew reduced is output from the phase adjustment circuit 21-1 to the outside of the apparatus as an output signal via the output buffer 14-1.
[0066]
FIG. 15 shows a modification of the embodiment in which the skew reduction circuit according to the present invention is used as an output interface. In FIG. 15, the same components as those of FIG. 14 are referred to by the same numerals, and a description thereof will be omitted.
The skew reduction circuit in FIG. 15 is supplied with a clock signal CLK, an inverted clock signal / CLK, and an internal signal used inside the apparatus. As in the embodiment of FIG. 14, the rising / falling skew included in the clock signal CLK, the inverted clock signal / CLK, and the internal signal is reduced based on the information included in the clock signal CLK and the inverted clock signal / CLK. The internal signal in which the rising / falling skew is reduced is output as an output signal from the phase adjustment circuit 21-1 to the outside of the apparatus via the output buffer 14-1. Also, the same output buffers 14-2 and 14-3 as the output buffer 14-1 serve as the phase adjustment circuit 21-2 that adjusts the phase of the clock signal CLK and the phase adjustment circuit 21-3 that adjusts the phase of the inverted clock signal / CLK. It is connected. Outputs from the output buffers 14-2 and 14-3 are input to the frequency divider 23 of the timing detection circuit 12 through the input buffer 13.
[0067]
In the configuration of FIG. 15, in order to prevent the output signal from including rising / falling skew due to the output buffer 14-1, the output buffers 14-2 and 14-3, which are the same as the output buffer 14-1, are phase-shifted. It is included in the feedback loop for adjustment. That is, the configuration of FIG. 15 reduces the rising / falling skew with respect to the clock signal CLK and the inverted clock signal / CLK after passing through the output buffers 14-2 and 14-3. As a result, the rising / falling skew can be reduced in the output signal after passing through the output buffer 14-1. In the configuration of FIG. 15, it is assumed that the rising / falling skew generated in the input buffer 13 is negligible.
[0068]
As mentioned above, although this invention was demonstrated based on the Example, this invention is not limited to the said Example, A various deformation | transformation and change are possible within the range as described in a claim.
[0069]
【The invention's effect】
Claims 1 to 7 In this invention, the rising edge of the clock signal is adjusted by adjusting the phase of the rising edge and the falling edge of the clock signal so that the period when the clock signal is at the HIGH level and the period when the clock signal is at the LOW level are the same. / Falling skew can be reduced. Further, by applying the same phase adjustment as the phase adjustment applied to the clock signal to other signals, it is possible to reduce the rising / falling skew in the other signals. The phase adjustment of the rising edge and falling edge can be easily realized by adjusting the transition time of each edge, and the transition time can be adjusted by changing the signal driving force. The phase adjustment function can be realized with this circuit.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a skew reduction circuit according to the principle of the present invention.
FIG. 2 is a configuration diagram when a skew reduction circuit according to the principle of the present invention is applied to skew reduction of signals other than a clock signal.
FIG. 3 is a configuration diagram of an embodiment of a skew reduction circuit according to the present invention.
4 is a timing chart showing signals S0 to S9 shown in FIG.
5 is a diagram for explaining phase adjustment in the phase adjustment circuit of FIG. 3; FIG.
6 shows a circuit configuration of the input buffer shown in FIG. 3;
7 is a circuit diagram showing a configuration of a frequency divider of the timing detection circuit of FIG. 3; FIG.
8 is a timing chart showing signal changes at nodes N1 to N9 in the timing detection circuit shown in FIG. 3;
9 is a circuit diagram of the shift register of FIG. 3. FIG.
10 is a circuit diagram of the phase adjustment circuit of FIG. 3;
FIG. 11 is a circuit diagram showing a modification of the phase adjustment circuit.
FIG. 12 is a circuit diagram showing a further modification of the phase adjustment circuit.
FIG. 13 is a diagram for explaining a configuration when a skew reduction circuit according to the present invention is applied to a semiconductor device;
FIG. 14 is a configuration diagram when the skew reduction circuit according to the present invention is used as an output interface for signal output.
FIG. 15 is a configuration diagram showing a modification when the skew reduction circuit according to the present invention is used as an output interface;
FIGS. 16A and 16B are diagrams for explaining rising / falling skews in a clock signal.
[Explanation of symbols]
11, 11A, 11B Phase adjustment circuit
12 Timing detection circuit
13, 13-1, 13-2, 13-3 Input buffer
14-1, 14-2, 14-3 Output buffer
21, 21-1, 21-2, 21-3 Phase adjustment circuit
22 Shift register
23 divider
24 binary counter
25 Phase comparison circuit
200 Semiconductor device
201 Input circuit
202 core circuit
203 Output circuit

Claims (7)

A first phase adjustment circuit for adjusting a phase with respect to a rising edge and a falling edge of the first signal;
  Receiving the first signal of which phase is adjusted from the first phase adjustment circuit, so that the relative phase relationship between the rising edge and the falling edge is a predetermined phase relationship; Timing detection circuit for controlling the adjustment circuit
Including
  The first signal is a clock signal, and the timing detection circuit controls the first phase adjustment circuit so that a period in which the first signal is at a HIGH level and a period in which the first signal is at a LOW level are substantially the same. And
  The first phase adjustment circuit receives the clock signal and a complementary clock signal that is 180 degrees out of phase with the clock signal, and the timing detection circuit receives one of the clock signal and the complementary clock signal as a third signal. And the inverted signal of the other signal is a fourth signal, and the first phase adjustment circuit is controlled so that the third signal and the fourth signal have the same phase. circuit.   The timing detection circuit includes a frequency divider that divides the third signal and the fourth signal, and a circuit that determines a front-rear relationship of edges between the frequency-divided signals. Item 1. The circuit according to Item 1. The first phase adjustment circuit holds an edge adjustment circuit that changes the phase of the rising edge and changes the phase of the falling edge, and a parameter that determines a phase change amount of the edge adjustment circuit, and 3. The circuit according to claim 2, further comprising a phase change amount holding circuit that sequentially updates the parameter based on the context of the two. 4. The circuit according to claim 3, wherein the phase change amount holding circuit is a shift register. The edge adjustment circuit receives the first signal as an input, and changes an output at a first transition time corresponding to the rising edge, and changes an output at a second transition time corresponding to the falling edge. 4. The circuit according to claim 3, wherein the first transition time and the second transition time are adjustable. 6. The circuit according to claim 5, wherein the edge adjustment circuit changes the first transition time and the second transition time by changing a driving force for driving an output signal. The edge adjustment circuit includes an inverter including at least one PMOS transistor and at least one NMOS transistor, a plurality of first transistors inserted between the at least one PMOS transistor and a power supply voltage, and the at least one transistor. Including a plurality of second transistors inserted between the NMOS transistor and the ground voltage, and changing a number of transistors to be conducted among the first transistors and a number of transistors to be conducted among the second transistors. 7. The circuit according to claim 6, wherein the phase of the rising edge is changed and the phase of the falling edge is changed.

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