JPH10320350A - Remote pio control system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To detect the unfairness of a process data reception order generated due to a difference between a DMA transfer completion order and the activation order of a DMA control part or the omission of process data generated due to the error of a DMA control part, and to quickly restore an error. SOLUTION: A host device 1 is provided with an IO control part 11. In this case, the IO control part 11 activates plural DMA control parts 32-34 in a prescribed order, receives data transfer completion communication from each of those plural DMA control parts 32-34, compares the order in which the completion communication is received with the order in which those DMA control parts 32-34 are activated, and re-activates all the DMA control parts 32-34 in the prescribed order after operating a prescribed processing when those orders are made equal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a process input / output (hereinafter referred to as "PIO") for inputting / outputting process data such as temperature, pressure and voltage of a system such as a plant.
The present invention relates to a remote PIO control system that controls a device via a PIO control device as an adapter.

[0002]

2. Description of the Related Art FIG. 6 is a block diagram showing a conventional remote PIO control device. In FIG. 6, reference numeral 61 denotes a host device such as a controller, 64 denotes a data buffer for temporarily storing process data, and 65 denotes a process buffer. A main storage device 651 that can be stored for a long period of time is provided in the main storage device 65, a DMA transfer area for exchanging data with a PIO control device 63, which will be described later, and a data transfer device 62 is commonly used by each component. A common bus that performs Data buffer 6
4 and the main storage device 65 are provided in the host device 61.

A PIO control device 63 controls a PIO device (not shown) via a PIO bus 64 described later.
Reference numeral 631 denotes a common bus control unit for controlling transfer of process data via the common bus 62, and reference numerals 632 to 634 denote IO control units 6 to be activated by the host device 61 and to process data.
DMA control units for performing transfer control of DMA transfer for transferring data from 35 to the main storage device 65 are provided in a number corresponding to the number of the PIO devices. 635 is a DMA control unit 632
An I / O control unit 636 for notifying the process data arrival to the order determined by the remote PIO control system to 634, temporarily holds the process data input via the PIO bus 64, and holds the process data on a first-in first-out basis. This is a FIFO unit that outputs process data. Common bus control unit 631, DMA control units 632 to 634, I
The O control unit 635 and the FIFO unit 636 are provided in the PIO control device 63. Reference numeral 64 denotes a PIO bus for transferring process data, and a plurality of PIO devices (not shown) are connected to the PIO bus 64.

Next, the operation will be described. First, the host device 61 prepares a DMA transfer area 651 on the main storage device 65 in synchronization with the initialization processing of the PIO control device 63, and stores the address and size of the DMA transfer region 651 in the PIO control device 63.
Notify the O control unit 635.

[0005] At the time of initial startup, the PIO controller 63
DMA control units 632 to 634
Is set in what order the process data reception notification is performed. In this conventional example, the DMA control units 632, 6
The setting is made so that the reception notification is performed in the order of 33 and 634. The DMA transfer area 651 specified by the higher-level device 61 is
When each DMA control unit is equally divided and each DMA control unit is started, the start address and size of the divided area are set to DM
A control units 632 to 634 are designated.

Next, the IO control unit 635 activates the DMA control unit 632 in accordance with the activation order determined at the time of the initial activation, and waits for the arrival of process data. The started DMA control unit 632 waits for a process data reception notification from the IO control unit 635.

When the process data arrives at the PIO controller 63 via the PIO bus 64, the IO controller 635 stores the process data arrived at the FIFO 636,
After confirming that the DMA control unit 632 is in the process data reception notification waiting state, the DMA control unit 632 notifies the DMA control unit 632 of the data reception. Thereafter, the IO control unit 635 activates the DMA control unit 633 and waits for the next process data to arrive.

The DMA control unit 63 that has received the data reception notification
2 retrieves the process data from the FIFO unit 636 and performs DMA transfer to the DMA transfer area 651 on the main storage device 65 via the common bus control unit 631. When the DMA transfer is completed, the common bus control unit 631 notifies the host device 61 of the completion of the transfer together with the start address and the size of the DMA transfer area 651 on the main storage device 65.
When the host device 61 receives this notification, it reads process data from the DMA transfer area 651 and writes the process data to the data buffer 64 in time series.

[0009] As described above, the IO control unit 635 controls the DM
DMA control unit 6 in the order of A control units 632, 633, and 634
Activate 32-634.

[0010]

SUMMARY OF THE INVENTION Conventional Remote PIO
Since the control system is configured as described above, in the remote PIO system in which the process data reception interval is short, the IO control unit 635 includes the DMA control units 632 to 6.
34 may be different from the order in which the DMA transfer is completed by each DMA control unit.
When a loss of process data occurs due to an error in the A control units 631 to 634, the higher-level device 61 can detect an abnormality, but the DMA control units 632 to 632 in the PIO control device 63.
634 cannot be controlled, so the IO control unit 63
5, there is a problem that the error recovery processing takes time.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an incorrect process data reception order or a DMA control unit error caused by a difference between the DMA transfer completion order and the activation order of the DMA control unit. An object of the present invention is to provide a remote PIO control system that can detect a loss of process data caused by an error and can quickly recover from the error.

Further, the present invention can also process process data received during error recovery, and can further shorten the data loss period.
The aim is to obtain an O control system.

Further, the present invention is capable of receiving process data from a plurality of PIO controllers, and
An object of the present invention is to provide a remote PIO control system capable of writing process data to a data buffer in a time series without deteriorating data consistency between IO control devices.

A further object of the present invention is to provide a remote PIO control system capable of reliably capturing important data and quickly accessing desired data.

[0015]

According to a first aspect of the present invention, there is provided a remote PIO control system comprising: a PIO control device having a first IO control unit and a plurality of DMA control units; Transfers the process data to the main storage unit of the host device, the first IO control unit notifies the plurality of DMA control units of the arrival of the process data in a predetermined order, and notifies the host device of the main storage unit A second IO control unit, a data processing unit, and a data buffer are provided, and the second IO control unit
When the plurality of DMA control units are activated in a predetermined order, and when the data transfer completion notification is received from each of the plurality of DMA control units, the order in which the completion notification is received is compared with the activation order. When they are equal, after performing a predetermined process, all the DMA control units are restarted in a predetermined order, and the data processing unit stores the process data transferred to the main storage unit in the data buffer in time series. Things.

[0016] The remote PIO according to the second aspect of the present invention.
In the control system, the predetermined process performed when the order in which the second IO control unit receives the completion notification is not equal to the order in which the second IO control unit is activated is a process for stopping all the activated DMA control units.

[0017] The remote PIO according to the third aspect of the present invention.
The control system performs a predetermined process when the order in which the second IO control unit receives the completion notification is not equal to the order in which the second IO control unit starts up, until the operation of all the DMA control units during startup is completed. This is a process for causing the processing unit to perform a process of accumulating process data to which a warning flag is added in a data buffer.

[0018] The remote PIO according to the fourth aspect of the present invention.
The control system is provided with an IO control unit and a data buffer corresponding to each PIO control device in a host device, and writes process data received from each PIO control device to the data buffer in a time-series manner.

A remote PIO according to the invention of claim 5
The control system has a host device provided with a plurality of data buffers.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. Embodiment 1 FIG. FIG. 1 is a configuration diagram showing a remote PIO control system according to a first embodiment of the present invention. In the figure, reference numeral 1 denotes a higher-level device such as a controller, and 11 activates DMA control units 32 to 34 to be described later, Part 32
, The data transfer completion notification is received from each of the DMA control units 32 to 34, and the order in which the completion notification is received and the order in which the completion notification is received are determined. IO control unit for controlling restart (second
An IO control unit), 12 is a data processing unit that performs processing for accumulating process data transferred to a main storage device 15 described later in a data buffer 14 described later in time series, and 13 is a data processing unit via a common bus 2 described later. A common bus controller for controlling transfer; 14 a data buffer for temporarily storing process data; 15 a main memory (main memory) capable of storing process data for a long period; 151 a main memory 15
A DMA transfer area 2 provided therein for directly exchanging data with a PIO control device 3 to be described later without passing through the IO control unit 11 is a common bus for performing data transfer using each component in common. IO control unit 11, data processing unit 1
2. The common bus control unit 13, the data buffer 14, and the main storage device 15 are provided in the host device 1.

A PIO controller 3 controls a PIO device (not shown) via a PIO bus 4 described later.
Is a common bus control unit that controls the transfer of process data via the common bus 2, and 32 to 34 are DMA transfer transfers that are started by the host device 1 and transfer process data from the IO control unit 35 to the main storage device 15, which will be described later. DMA controllers for controlling the number of the PIO devices are provided in a number corresponding to the number of the PIO devices. An IO control unit (first IO control unit) 35 notifies the DMA control units 32-34 of the arrival of process data in the order determined by the remote PIO control system,
Reference numeral 36 denotes a FIFO unit which temporarily stores process data input via the PIO bus 4 and outputs the process data stored in a first-in first-out manner. The common bus control unit 31, the DMA control units 32-34, the IO control unit 35, and the FIFO unit 36 are provided in the PIO control device 3. 4 is a PIO for transferring process data.
A plurality of PIO devices (not shown) are connected to the PIO bus 4 via a bus.

Next, the operation will be described with reference to the flowchart of FIG. First, the IO control unit 11 of the host device 1 activates the DMA control units 32 to 34 in the PIO control device 3 via the common bus control unit 13 in the order determined by the remote PIO control system (step ST).
1). Here, it is assumed that the DMA control units 32, 33, and 34 are activated in this order. Thereby, the DMA control unit 32
To 34 are in a state of waiting for a process data reception notification from the IO control unit 35. At this time, the DMA transfer area 151 on the main storage device 15 for each DMA control unit is designated by the IO control unit 11 as an area previously fixedly secured for each DMA control unit.

When process data arrives at the PIO controller 3 from a PIO device (not shown) via the PIO bus 4, the IO controller 35 temporarily stores the process data in the FIFO unit 36 and sends the process data to the DMA controller 32. Notify that it was received. As a result, the DMA control unit 32 reads out the process data accumulated from the FIFO unit 36 in a first-in first-out manner, and
1. The read process data is transferred to the DMA transfer area 151 of the main storage device 15 via the common bus 2, and when the transfer is completed, the DMA transfer is completed to the IO control unit 11 via the common bus control unit 31. Notify that.

When the IO control unit 11 receives the DMA transfer completion notification (step ST2), the IO control unit 11 sets the data transfer completion order to D
It is checked whether the activation order of the MA control units 32-34 is equal (step ST3). In this case, since the order of activation and the order of completion are the same, it is determined that data consistency is maintained, and the data processing unit 12 sends the DMA
The start address and data size on the transfer area 151 are notified, and a data processing request is issued.

When the data processing unit 12 writes the process data transferred to the specified address in the DMA transfer area 151 on the main storage device 15 into the data buffer 14 (step ST4), the IO control unit 11 executes the DMA control unit. 32
Is restarted (step ST5), and the next DMA transfer completion notification is waited for.

Thereafter, the IO control unit 11
Receiving the DMA transfer completion notification from the data processing units 2 to 34, a data processing request to the data processing unit 12, and D which has completed the data transfer.
The restart of the MA control unit is repeated.

Further, as in the case where the IO control unit 11 activates the next DMA control unit before the transfer operation of the DMA control unit during the process data transfer is completed, the result of the comparison in step ST3 is a DMA transfer. Control units 32-34
If the start order of the data transfer is not equal to the data transfer completion order, the IO control unit 11 determines that data consistency is not maintained, and forcibly activates all the active DMA control units. (Step ST6), and activate the DMA control units 32-34 in the order defined by the remote PIO control system (in this embodiment, the order of the DMA control units 32, 33, and 34) (step ST1). , Again D
It waits for a data transfer completion notification from the MA control unit 32.

As described above, according to the first embodiment, if the order in which the data transfer completion notices are received from the DMA controllers 32 to 34 and the order in which the DMA controllers 32 to 34 are activated are the same, the data processor 12 To process the data,
If they are not equal, after stopping all the active DMA control units, the DMAs are executed in the order determined by the remote PIO control system.
Since the control unit is restarted, it is possible to detect an incorrect process data reception order caused by a difference between the DMA transfer completion order and the start order of the DMA control unit and a loss of process data caused by an error in the DMA control unit. And an effect that the error can be quickly recovered.

Embodiment 2 FIG. 3 is a flowchart showing the operation of the remote PIO control system according to the second embodiment of the present invention. In the figure, the same operation steps as those of the first embodiment shown in FIG. And the description is omitted. The configuration of the second embodiment is the same as the configuration of the first embodiment shown in FIG.

In the first embodiment, the IO control unit 11
Indicates the order in which the DMA control unit was started and the DM of the process data.
When it is detected that the A transfer completion order is not equal, all the active DMA control units are forcibly stopped. In the second embodiment, the IO control unit 11
When it is detected that the order of activation of the DMA control units 32 to 34 is different from the order of notification of the completion of the transfer of the process data, thereafter, until the process data transfer processing of all the active DMA control units is completed, the process is simply performed. It only causes the data processing unit 12 to perform data processing, and does not check the start order of the DMA control unit and the order of notification of the completion of the process data transfer, and does not restart the DMA control unit.

Next, the operation will be described with reference to the flowchart of FIG. As in the first embodiment, the IO controller 11 controls the DMA controllers 32 to 34
Start up in the order determined by the IO control system (step S
T1) First, the DMA transfer area 151 of the DMA control unit 32
Transfer of the process data to the IO control unit 11 is completed.
Is notified that the DMA transfer has been completed (step S
T2), the IO control unit 11 determines the data transfer completion order and the DM
It is checked whether the order in which the A control units 32 to 34 are activated is the same (step ST3).

The order in which the DMA controllers 32 to 34 are activated and D
If the order in which the MA transfer is completed is the same, the data processing unit 1
2 writes process data from the DMA transfer area 151 to the data buffer 14 (step ST4),
The control unit 11 restarts the DMA control unit 32 (Step S
T7) Wait for the next DMA transfer completion notification.

Thereafter, the IO control unit 11
Receiving the DMA transfer completion notification from the data processing units 2 to 34, the data processing request to the data processing unit 12, and the DM that has completed the data transfer.
The restart of the control unit A is repeated.

If the order of activation of the DMA controllers 32 to 34 is not equal to the order of completion of data transfer, the IO controller 11 determines that data consistency is not maintained, and
The data processing unit 12 is notified that the data reception time is incorrect. When the data processing unit 12 is notified that the data reception time is invalid, the data transfer unit 1
A warning flag indicating that the reception time is invalid is added to the process data read from the data buffer 51, and is written to the data buffer 14 as warning data (step ST).
8). In this way, the data processing unit 12 is caused to perform data processing, and the DMA control units 32 to 34 until the process data transfer processing of all the active DMA control units is completed.
And the DMA transfer unit are not restarted (steps ST9 and ST1).
0).

When the process data transfer processing of all the active DMA control units is completed (step ST9), the IO
The control unit 11 restarts the DMA control units 32 to 34 in the order determined by the remote PIO control system (step ST5), and waits for a data transfer completion notification from the DMA control unit 32 again.

As described above, according to the second embodiment, when the order in which the DMA controllers 32 to 34 are activated is different from the order in which data transfer is completed, a warning flag is simply added to the transfer processing data. Since the DMA control units are restarted in the order determined by the remote PIO control system after the process data transfer processing of all the active DMA control units is completed, the DMA transfer completion order and the DMA control unit Error in the order of receiving process data caused by a difference in the startup order of the process data and loss of process data caused by an error in the DMA control unit, and the error can be quickly recovered, and received during error recovery. Since the process data can also be processed, the effect of shortening the data loss period can be obtained.

Embodiment 3 FIG. 4 is a configuration diagram showing a remote PIO control system according to Embodiment 3 of the present invention. In the figure, the same components as those of Embodiment 1 of FIG. Is omitted.

In FIG. 4, reference numeral 1a denotes a host device, and reference numerals 5 and 6 denote PIO control devices having the same configuration as the PIO control device 3.
The O control device 3 is connected between the common bus 2 and the PIO bus 4 in parallel. 16 and 17 are IO control units 11
Control unit that performs the same operation as (second IO control unit)
Then, activation of the DMA control units of the PIO controllers 5 and 6, reception of the data transfer completion notification, determination of the difference between the order in which the completion notifications were received and the order of activation, instruction of data processing to the data processing unit, DMA control Controls stop and restart of the unit.

Next, the operation will be described. In the third embodiment, a plurality of IOs provided in the host
The control units 11, 16, and 17 control the operation of the associated PIO control device among the plurality of PIO control devices 3, 5, and 6, respectively.

As described above, according to the third embodiment, process data can be received from a plurality of PIO control devices, and time series can be performed without impairing data consistency between the PIO control devices. Thus, the effect that the process data can be written in the data buffer 14 can be obtained.

Embodiment 4 FIG. FIG. 5 is a configuration diagram showing a remote PIO control system according to Embodiment 4 of the present invention. In the drawing, the same components as those of Embodiment 1 of FIG. Is omitted.

In FIG. 5, reference numeral 1b denotes a host device, and reference numeral 18 denotes a data buffer for temporarily storing process data. In the fourth embodiment, two data buffers are provided.

Next, the operation will be described. In the fourth embodiment, when process data is transferred from the DMA transfer area 151 to the data buffers 14 and 18, which data buffer is to be transferred is determined according to the contents of the data. For example, data having a large data capacity but a low importance is transferred to the data buffer 14, and data having a small data capacity but a high importance is transferred to the data buffer 1.
8. This prevents a small amount of important data from being missed due to a large amount of less important data.

As described above, according to the fourth embodiment, since the process data is distributed to the data buffers, it is possible to obtain an effect that important data can be reliably captured. Although two data buffers are provided in the fourth embodiment, the number of data buffers is not limited to two, and a plurality of data buffers may be provided according to the type of process data to be taken. Can be. As a result, the process data can be classified according to the remote PIO control system, and the effect of quickly accessing desired data can be obtained.

[0045]

As described above, according to the first aspect of the present invention, if the order in which the data transfer completion notification is received from the DMA control unit and the order in which the DMA control unit is activated are the same, the data processing unit performs data processing. Since all the DMA control units are restarted in a predetermined order after performing a predetermined process if they are not equal, the DMA transfer completion order and the DMA
There is an effect that an error in the order of receiving process data, which occurs due to a difference in the activation order of the control unit, or a loss of process data, which occurs due to an error in the DMA control unit, can be detected, and the error can be quickly recovered.

According to the second aspect of the present invention, the second IO
Since the predetermined processing to be performed when the order in which the control unit receives the completion notification is not equal to the order in which the DMA control units are activated is configured to be a process for stopping all the active DMA control units, D
Due to the difference between the MA transfer completion order and the activation order of the DMA control unit, incorrect process data reception order or DMA
There is an effect that a loss of process data caused by an error in the control unit can be detected and the error can be quickly recovered.

According to the third aspect of the present invention, the second IO
A predetermined process to be performed when the order in which the control unit receives the completion notification is not equal to the order in which the activation notification is started is performed by all of the DMs being activated.
Until the operation of the A control unit is completed, the process is a process of simply accumulating the process data obtained by adding the warning flag to the transfer processing data in the data buffer. Error in the order of receiving process data caused by a difference in the startup order of the process data and loss of process data caused by an error in the DMA control unit, and the error can be quickly recovered, and received during error recovery. Since the process data can also be processed, the data missing period can be shortened.

According to the fourth aspect of the present invention, an IO control unit and a data buffer corresponding to each PIO control device are provided in the host device, and process data received from each PIO control device is stored in the data buffer in time series. Since it is configured to write data, it is possible to receive process data from a plurality of PIO controllers, and to write process data to a data buffer in a time series without losing data consistency between the PIO controllers. is there.

According to the fifth aspect of the present invention, since a plurality of data buffers are provided in the host device, important data can be reliably taken in, and the process data corresponding to the remote PIO control system can be stored. Classification can be performed, and there is an effect that desired data can be quickly accessed.

[Brief description of the drawings]

FIG. 1 shows a remote PI according to a first embodiment of the present invention.
It is a block diagram showing an O control system.

FIG. 2 is a flowchart showing an operation of the first embodiment in FIG. 1;

FIG. 3 shows a remote PI according to a second embodiment of the present invention;
It is a flowchart which shows operation | movement of an O control system.

FIG. 4 shows a remote PI according to a third embodiment of the present invention.
It is a block diagram showing an O control system.

FIG. 5 shows a remote PI according to a fourth embodiment of the present invention.
It is a block diagram showing an O control system.

FIG. 6 is a configuration diagram showing a conventional remote PIO control system.

[Explanation of symbols]

1, 1a, 1b Host device, 3, 5, 6 PIO control device, 4 PIO bus, 11, 16, 17 IO control unit (second IO control unit), 12 data processing unit, 14, 1
8 data buffers, 15 main storage devices (main storage unit),
32, 33, 34 DMA control unit, 35 IO control unit (first IO control unit).

Claims (5)

[Claims] 1. A remote PIO control system comprising a host device and a PIO control device controlled by the host device, wherein the remote PIO control system processes time-series process data from a PIO received via a PIO bus. A first IO control unit and a plurality of DMs
A control unit, wherein the plurality of DMA control units transfer the process data to a main storage unit of the higher-level device, and the first IO control unit transmits the process data to the plurality of DMA control units. Notifying the arrival of the process data in a predetermined order; providing the main storage unit, a second IO control unit, a data processing unit, and a data buffer in the host device, wherein the second IO control unit Are started in a predetermined order, and when the data transfer completion notices are received from each of the plurality of DMA control units, the order in which the completion notices are received is compared with the order in which they are started, and these orders are equal. Sometimes, the data processing unit performs data processing, and when these orders are not equal, after performing predetermined processing, restarts all the DMA control units in a predetermined order, and the data processing unit In the memory A remote PIO control system, wherein the transferred process data is stored in the data buffer in time series. 2. The method according to claim 1, wherein the predetermined process performed when the order in which the second IO control unit receives the completion notification is not equal to the order in which the second IO control unit is activated is a process for stopping all the activated DMA control units. The remote PIO control system according to claim 1, wherein 3. The predetermined processing to be performed when the order in which the second IO control unit receives the completion notification is not equal to the order in which the second IO control unit is started up is performed until the operation of all the active DMA control units is completed. 2. The remote PI according to claim 1, wherein the process is a process of causing a data processing unit to perform a process of accumulating process data to which a warning flag is added in the data buffer.
O control system. 4. A remote PIO control system having a host device and a plurality of PIO control devices controlled by the host device and processing time-series process data from a PIO received via a PIO bus, A remote PIO control system, comprising: an I / O control unit and a data buffer corresponding to each PIO control device provided in the host device; and writing process data received from each of the PIO control devices to the data buffer in chronological order. 5. A remote PIO control system, comprising a host device and a PIO control device controlled by the host device, wherein the remote PIO control system processes the process data from the PIO received via a PIO bus in time series. A remote PIO control system, wherein a plurality of data buffers are provided.