JPH10320302A - Information processor - Google Patents

Information processor

Info

Publication number
JPH10320302A
JPH10320302A JP9131901A JP13190197A JPH10320302A JP H10320302 A JPH10320302 A JP H10320302A JP 9131901 A JP9131901 A JP 9131901A JP 13190197 A JP13190197 A JP 13190197A JP H10320302 A JPH10320302 A JP H10320302A
Authority
JP
Japan
Prior art keywords
memory
power
main storage
switch
transfer means
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9131901A
Other languages
Japanese (ja)
Inventor
Kazunori Iwabuchi
一則 岩渕
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP9131901A priority Critical patent/JPH10320302A/en
Publication of JPH10320302A publication Critical patent/JPH10320302A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To return to a state just before power is turned off when the power is on by providing a nonvolatile storage memory and a main storage transfer means and making the main storage transfer means transfer memory contents between main storage memory and the nonvolatile storage memory each time a power off switch and a power on which are pressed down. SOLUTION: When a user depresses a hibernation shift switch 1A with an AP, etc., started after an OS starts after starting through a power switch 3, a data transfer means between main storage flash memories 4 writes a memory image on a main storage to a flash memory 2, makes a hibernation flag 1 and turns off the power. After that, when the switch 3 is depressed, the main storage flash memory inter-data transfer means fetches the memory image from the memory 2 and stores it in the main storage when the hibernation flag is 1. Also, when the hibernation flag is 0, it performs normal start of the OS.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、電源オフの直前の
使用状態へ電源オンのときに戻す必要があるノートパソ
コンなどの情報処理装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus such as a notebook personal computer which needs to return to a use state immediately before power off when power on.

【0002】[0002]

【従来の技術】近年、コンピュータ、特にパーソナルコ
ンピュータ(以下、PCと記す)の性能は飛躍に向上
し、主記憶メモリの値段の低下から、主記憶メモリの最
大容量は年々増加をたどっている。
2. Description of the Related Art In recent years, the performance of computers, especially personal computers (hereinafter, referred to as PCs) has been dramatically improved, and the maximum capacity of the main memory has been increasing year by year due to the decrease in the price of the main memory.

【0003】電源オフ直前の使用状態に電源オンのとき
に戻すような仕組みを備えたPCとしてノートパソコン
のハイバネーション機能があり、この仕組みを備えたも
のとして、例えばIBM社のThinkPadと呼ばれるノート
PC必ず備えている。
There is a hibernation function of a notebook personal computer as a PC having a mechanism for returning to a use state immediately before the power is turned off when the power is turned on. For example, a notebook PC called an IBM ThinkPad is necessarily provided with this mechanism. Have.

【0004】[0004]

【発明が解決しようとする課題】ところが、ハイバネー
ション機能を利用する際、主記憶メモリのすべての情報
をHDDなどの2次記憶装置に格納したり、あるいは読
み出したりさせるために、HDDの特定エリアを主記憶
分消費してしまい、実装メモリ容量が増えているため、
その場所が大きくなる一方である。また、その分、情報
の転送に時間がかかり、特にHDDが動作中なため、す
ぐに使用を止めたい、あるいはすぐに使用可能な状態に
しようと思っても、ノートPCをすぐに持ち運ぶとHD
Dに衝撃を与えるため危険なため、使用者はその間待た
されるといった点において配慮が不足していた。
However, when the hibernation function is used, a specific area of the HDD is required to store or read out all information of the main memory from or to a secondary storage device such as an HDD. Because the main memory is consumed and the mounting memory capacity is increasing,
The place is getting bigger. In addition, it takes time to transfer information, and in particular, since the HDD is in operation, even if you want to stop using it immediately or make it ready for use, if you carry the notebook PC immediately,
D is dangerous because it gives a shock to D, so that the user is not sufficiently careful in that he waits during that time.

【0005】[0005]

【課題を解決するための手段】そこで、本発明ではHD
Dなど駆動回転するような機械部品を持つ2次記憶装置
の代わりに、フラッシュメモリに代表される機械部品を
備えない不揮発性メモリを用い、主記憶転送手段を備
え、電源オフ、電源オンの時に高速なデータ転送を行
い、データ転送期間を短くするものである。また、高速
なデータ転送を保証するために主記憶メモリと同様に、
メモリ基板上に実装された不揮発性メモリを用いる。
Therefore, in the present invention, the HD
In place of a secondary storage device having mechanical parts such as D for driving rotation, a non-volatile memory having no mechanical parts such as a flash memory is used, and a main memory transfer unit is provided. High-speed data transfer is performed to shorten the data transfer period. Also, like main memory, to guarantee high-speed data transfer,
A non-volatile memory mounted on a memory substrate is used.

【0006】[0006]

【発明の実施の形態】上記発明の具体的な実施の形態に
ついて、以下に図を用いて説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Specific embodiments of the above invention will be described below with reference to the drawings.

【0007】図1は、本発明の実施例を示すシステムブ
ロック図である。同図において、ハイバネーション移行
SW1、フラッシュメモリ2、電源SW3、主記憶フラ
ッシュメモリ4間のデータ転送手段とより成る。
FIG. 1 is a system block diagram showing an embodiment of the present invention. In the figure, the system comprises a hibernation switch SW1, a flash memory 2, a power supply SW3, and a data transfer means between the main memory flash memory 4.

【0008】この動作は、PCにおいて電源SW3によ
る起動後、OSが起動した後、APなどを起動した状態
において、ハイバネーション移行SW1Aがユーザによ
って押されると、主記憶上のメモリイメージを主記憶フ
ラッシュメモリ4間データ転送手段がフラッシュメモリ
2に書き出し、ハイバネーションフラグを1にして電源
をオフにする。
This operation is performed when the hibernation switch SW1A is pressed by the user in the state where the PC is activated by the power supply SW3, the OS is activated, the AP is activated, etc. The four-way data transfer means writes the data to the flash memory 2, sets the hibernation flag to 1, and turns off the power.

【0009】その後、電源SWが押されると、ハイバネ
ーションフラグが1の時にはフラッシュメモリに主記憶
のメモリイメージが格納されているので主記憶フラッシ
ュメモリ間データ転送手段はフラッシュメモリから主記
憶のメモリイメージを取り出し、主記憶に格納する。
Thereafter, when the power switch is pressed, when the hibernation flag is 1, since the main memory image is stored in the flash memory, the main memory flash memory data transfer means transfers the main memory image from the flash memory. Retrieve and store in main memory.

【0010】ハイバネーションフラグが0の時には、通
常のOSの起動を行う。フラッシュメモリはCPU、メ
モリなどが搭載された回路基板上に固定されている。フ
ラッシュメモリはPCカードなど、脱着可能な形態で使
用されている主記憶とフラッシュメモリは、直接バスに
よって接続されており、主記憶フラッシュメモリ転送手
段はアドレスバス、データバスを出力しDMA転送する
ものである。フラッシュメモリは主記憶と同じSIMM,DI
MMのようなユーザによって増設可能な状態で実装されて
いる。
When the hibernation flag is 0, the normal OS is started. The flash memory is fixed on a circuit board on which a CPU, a memory, and the like are mounted. The flash memory is used in a removable form such as a PC card. The main memory and the flash memory are directly connected by a bus, and the main memory flash memory transfer means outputs an address bus and a data bus to perform DMA transfer. It is. Flash memory is the same SIMM and DI as main memory
It is mounted so that it can be added by users such as MM.

【0011】[0011]

【発明の効果】以上のような構成を備えることで、主記
憶メモリと不揮発性メモリとの間で高速にデータ転送を
行い、電源オフ直前の状態へ電源オンのときに復帰させ
ることが可能である。
With the above configuration, it is possible to perform high-speed data transfer between the main memory and the non-volatile memory, and to return to the state immediately before the power is turned off when the power is turned on. is there.

【図面の簡単な説明】[Brief description of the drawings]

【図1】図1は本発明の全体構成を示すシステムブロッ
ク図。
FIG. 1 is a system block diagram showing an overall configuration of the present invention.

【図2】図2は本発明を備えたPC。FIG. 2 is a PC equipped with the present invention.

【図3】図3は本発明の図1における不揮発性メモリの
概観図。
FIG. 3 is a schematic view of a nonvolatile memory in FIG. 1 of the present invention.

【符号の説明】[Explanation of symbols]

1A…ハイバネーション移行SW、 2…フラッシュメ
モリ、 3…電源SW、 4…主記憶フラッシ
ュメモリ。
1A: Hibernation transition SW, 2: Flash memory, 3: Power switch, 4: Main memory flash memory.

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】主記憶メモリ、CPU、電源オフスイッ
チ、電源オンスイッチを備えた情報処理装置において、
不揮発性記憶メモリ、主記憶転送手段を備え、電源オフ
スイッチと電源オンスイッチを押されるごとに主記憶転
送手段によって主記憶メモリと不揮発性記憶メモリとの
間でメモリ内容の転送を行う情報処理装置。
1. An information processing apparatus comprising a main memory, a CPU, a power-off switch, and a power-on switch.
An information processing apparatus including a nonvolatile storage memory and a main storage transfer unit, wherein the main memory transfer unit transfers memory contents between the main storage memory and the nonvolatile storage memory each time a power off switch and a power on switch are pressed. .
【請求項2】請求項1の不揮発性記憶メモリは主記憶メ
モリと同様な基板上に実装され、主記憶メモリと同じデ
ータバス幅を持ち、主記憶転送手段から直接読み書き可
能な不揮発性記憶メモリ。
2. The nonvolatile storage memory according to claim 1, wherein said nonvolatile storage memory is mounted on a substrate similar to said main storage memory, has the same data bus width as said main storage memory, and is readable and writable directly from main storage transfer means. .
JP9131901A 1997-05-22 1997-05-22 Information processor Pending JPH10320302A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9131901A JPH10320302A (en) 1997-05-22 1997-05-22 Information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9131901A JPH10320302A (en) 1997-05-22 1997-05-22 Information processor

Publications (1)

Publication Number Publication Date
JPH10320302A true JPH10320302A (en) 1998-12-04

Family

ID=15068825

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9131901A Pending JPH10320302A (en) 1997-05-22 1997-05-22 Information processor

Country Status (1)

Country Link
JP (1) JPH10320302A (en)

Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100630129B1 (en) * 2005-03-28 2006-09-27 삼성전자주식회사 Method for saving data of hard disk drive in wireless terminal
JP2011508341A (en) * 2007-12-28 2011-03-10 インテル コーポレイション System and method for fast platform hibernation and resume
JP2012514787A (en) * 2009-01-05 2012-06-28 マーベル ワールド トレード リミテッド Hibernate or suspend method and system utilizing non-volatile memory device
US8443187B1 (en) 2007-04-12 2013-05-14 Marvell International Ltd. Authentication of computing devices in server based on mapping between port identifier and MAC address that allows actions-per-group instead of just actions-per-single device
US8510560B1 (en) 2008-08-20 2013-08-13 Marvell International Ltd. Efficient key establishment for wireless networks
US8839016B2 (en) 2007-07-23 2014-09-16 Marvell World Trade Ltd. USB self-idling techniques
US8843686B1 (en) 2007-04-05 2014-09-23 Marvell International Ltd. Processor management using a buffer
US8984316B2 (en) 2011-12-29 2015-03-17 Intel Corporation Fast platform hibernation and resumption of computing systems providing secure storage of context data
US9032139B2 (en) 2012-12-28 2015-05-12 Intel Corporation Memory allocation for fast platform hibernation and resumption of computing systems
US9141394B2 (en) 2011-07-29 2015-09-22 Marvell World Trade Ltd. Switching between processor cache and random-access memory
US9436629B2 (en) 2011-11-15 2016-09-06 Marvell World Trade Ltd. Dynamic boot image streaming
US9436251B2 (en) 2011-10-01 2016-09-06 Intel Corporeation Fast platform hibernation and resumption of computing systems
US9575768B1 (en) 2013-01-08 2017-02-21 Marvell International Ltd. Loading boot code from multiple memories
US9652249B1 (en) 2008-09-18 2017-05-16 Marvell World Trade Ltd. Preloading an application while an operating system loads
US9736801B1 (en) 2013-05-20 2017-08-15 Marvell International Ltd. Methods and apparatus for synchronizing devices in a wireless data communication system
US9836306B2 (en) 2013-07-31 2017-12-05 Marvell World Trade Ltd. Parallelizing boot operations
US9860862B1 (en) 2013-05-21 2018-01-02 Marvell International Ltd. Methods and apparatus for selecting a device to perform shared functionality in a deterministic and fair manner in a wireless data communication system
US10979412B2 (en) 2016-03-08 2021-04-13 Nxp Usa, Inc. Methods and apparatus for secure device authentication

Cited By (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100630129B1 (en) * 2005-03-28 2006-09-27 삼성전자주식회사 Method for saving data of hard disk drive in wireless terminal
US8843686B1 (en) 2007-04-05 2014-09-23 Marvell International Ltd. Processor management using a buffer
US9253175B1 (en) 2007-04-12 2016-02-02 Marvell International Ltd. Authentication of computing devices using augmented credentials to enable actions-per-group
US8443187B1 (en) 2007-04-12 2013-05-14 Marvell International Ltd. Authentication of computing devices in server based on mapping between port identifier and MAC address that allows actions-per-group instead of just actions-per-single device
US8839016B2 (en) 2007-07-23 2014-09-16 Marvell World Trade Ltd. USB self-idling techniques
JP2011508341A (en) * 2007-12-28 2011-03-10 インテル コーポレイション System and method for fast platform hibernation and resume
US9769653B1 (en) 2008-08-20 2017-09-19 Marvell International Ltd. Efficient key establishment for wireless networks
US8510560B1 (en) 2008-08-20 2013-08-13 Marvell International Ltd. Efficient key establishment for wireless networks
US9652249B1 (en) 2008-09-18 2017-05-16 Marvell World Trade Ltd. Preloading an application while an operating system loads
JP2012514787A (en) * 2009-01-05 2012-06-28 マーベル ワールド トレード リミテッド Hibernate or suspend method and system utilizing non-volatile memory device
US8443211B2 (en) 2009-01-05 2013-05-14 Marvell World Trade Ltd. Hibernation or suspend using a non-volatile-memory device
US9141394B2 (en) 2011-07-29 2015-09-22 Marvell World Trade Ltd. Switching between processor cache and random-access memory
US9436251B2 (en) 2011-10-01 2016-09-06 Intel Corporeation Fast platform hibernation and resumption of computing systems
US9436629B2 (en) 2011-11-15 2016-09-06 Marvell World Trade Ltd. Dynamic boot image streaming
US10275377B2 (en) 2011-11-15 2019-04-30 Marvell World Trade Ltd. Dynamic boot image streaming
US8984316B2 (en) 2011-12-29 2015-03-17 Intel Corporation Fast platform hibernation and resumption of computing systems providing secure storage of context data
US9032139B2 (en) 2012-12-28 2015-05-12 Intel Corporation Memory allocation for fast platform hibernation and resumption of computing systems
US9575768B1 (en) 2013-01-08 2017-02-21 Marvell International Ltd. Loading boot code from multiple memories
US9736801B1 (en) 2013-05-20 2017-08-15 Marvell International Ltd. Methods and apparatus for synchronizing devices in a wireless data communication system
US9860862B1 (en) 2013-05-21 2018-01-02 Marvell International Ltd. Methods and apparatus for selecting a device to perform shared functionality in a deterministic and fair manner in a wireless data communication system
US9836306B2 (en) 2013-07-31 2017-12-05 Marvell World Trade Ltd. Parallelizing boot operations
US10979412B2 (en) 2016-03-08 2021-04-13 Nxp Usa, Inc. Methods and apparatus for secure device authentication

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