JPH10319091A - Fail analysis memory, semiconductor test system using it, and semiconductor test method using them - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an analytic memory capable of shorting the time required for a test by storing the fail information of defective result obtained from signal comparing process in a second memory means, reading the fail information in parallel to index process, and storing it in a second memory in conformation to a fail generating position. SOLUTION: A fail analysis memory 37 stores the function fail every wafer by setting the input of a multiplexer 28 before test start on a side (a). When a fail occurs after the test start, the fail information is successively stored in an address memory 19 and a fail pin data memory 20. Since the fail information is read in parallel to the processing of wafer index in an LSI test, the test can be performed at high speed regardless of the test time per sample, and the test time can be significantly shortened. Accordingly, the time can be shortened by storing the fail information in the second memory every body to be tested and reading it in parallel to the index process.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a measuring device, a measuring system using the same, a measuring method using the same,
In particular, the present invention relates to a fail analysis memory, a semiconductor test system using the same, and a semiconductor test method using the same.

[0002]

2. Description of the Related Art In recent years, the degree of integration of semiconductor devices has been increasing at an accelerating rate, and as LSIs and VLSIs have become ULSIs,
The functions of integrated circuits have become more and more complex, and the study of high-speed and high-precision test methods has been emphasized in order to provide inexpensive and highly reliable semiconductor devices. In particular, for logic products that are mass-produced, failure analysis is performed based on the failure information of the test results, and defects on the circuit are discovered early,
Implementing design changes is crucial to increasing product reliability, improving manufacturing yields and reducing manufacturing costs, and the development of methods and test equipment to perform testing with high efficiency is strongly required. Is desired.

Here, a test method for mass production of a logic LSI will be described with reference to the drawings.

In the following drawings, the same portions are denoted by the same reference numerals, and the description thereof will be omitted.

FIG. 10 is a block diagram showing an outline of a logic test method in a general-purpose LSI function test.

First, the logic pattern generating means 124 generates a test logic pattern and an expected value pattern as a reference for pass / fail judgment. Next, the LSI under test 300 (hereinafter referred to as DU)
T: Device Under Test. ) Is input to the input terminal 290.

Further, the DU driven by the power supply 190
The pattern which the logic circuit of T300 outputs to the output terminal 310 according to the logic pattern is compared with the pattern comparing means 1
45 is compared with the expected value pattern supplied from the expected value pattern supply means 126, and the pass / fail determination means 400 makes a pass / fail judgment.

In a semiconductor test system which performs a test using such a method, when a failure occurs during the test, a failure analysis memory is a storage means for storing a failure location and the content of the failure for each logic pattern.

[0009] One of the conventional fail analysis memories
The configuration of a specific example will be described with reference to the block diagram of FIG.

The logic pattern generator 2 is a logic pattern generation means for generating a logic pattern and an expected value pattern in synchronization with a test cycle. Logical comparison circuit 6
Is a pass / fail determination unit that compares the comparison result of the pattern comparison unit 145 with the expected value pattern supplied from the pattern generator 2 and determines pass / fail. The storage means for storing the fail pin data from the logical comparison circuit 6 and the counter value of the pattern generator 2 is the fail analysis memory 7. CP
A U (Central Processing Unit) 8 is a control unit that controls the entire system and extracts fail information stored in the fail analysis memory 7.

The fail analysis memory 7 includes an address counter 21 for setting an address of a defective portion, an address memory 19 for storing a counter value supplied from the pattern generator 2 according to an address signal supplied from the address counter 21, Similarly, a fail pin data memory 20 is provided for storing fail pin data, which is the DUT failure content supplied from the logical comparison circuit 6 according to the address signal supplied from the address counter 21.

The operation of the fail analysis memory 7 is as follows.

When a function file indicating a logic test failure occurs during testing of a DUT sample,
First, the test is terminated. Next, the logical comparison circuit 6
A fail signal is sent to the clock input of the address counter 21, and the address counter 21 counts up the addresses of the address memory 19 and the fail pin data memory 20. The logic pattern generator 2 stores a counter value 25 such as a pattern address counter or an index counter in the address memory 19 simultaneously with the operation of the address counter 21. Similarly, the logical comparison circuit 6
The fail pin data 24 such as the number of the tester pin in which the failure has occurred and the output result of the DUT is stored in the fail pin data memory 20 at the designated address. Next, the CPU 8
Designates an address, retrieves the fail information stored in the address memory 19 and the fail pin data memory 20, and stores it in an auxiliary storage device such as a hard disk. Thereafter, when the CPU 8 moves the tester pin to the next sample and the test of the next sample starts, a test start signal is input to the clock input of the address counter 21. In response to this, the address counter 21 sets the address memory 19 and the fail signal. The contents stored in the pin data memory 20 are erased.

As described above, in a conventional semiconductor test system using a fail analysis memory, fail information is extracted for each sample and before the chip index processing.

[0015]

However, due to the recent increase in the degree of integration of semiconductor devices and the increase in the number of pins, it has been taking a long time to perform a test per sample. On the other hand, in order to perform failure analysis at high speed, fail information of a quantity that can be analyzed is required, and for that purpose, fail information at the time of mass production needs to be accumulated.

On the other hand, in the semiconductor test method using the above-described semiconductor test system based on the prior art, when obtaining the fail information, as described above, 1
Since the fail memory address counter is cleared each time a sample test is started, fail information must be extracted before chip index processing every time one sample test is completed, and the entire test time becomes longer. It takes time, and there is a problem that the throughput of the semiconductor test decreases.

The present invention has been made in view of the above circumstances, and has as its object to provide a fail analysis memory capable of shortening the time required for testing in semiconductor device test evaluation, a semiconductor test system using the same, and a semiconductor test system using the same. And a semiconductor test method using the same.

[0018]

The present invention is to solve the above-mentioned problems by the following means.

That is, according to the present invention (claim 1), a logic pattern input step of inputting a test logic pattern signal to a first device under test, and a signal output from the first device under test. A signal comparison step of comparing the result of the test with a pattern signal serving as a criterion of pass / fail, and a first pass / fail result stored in the first storage means.
And storing the fail information, which is the content of the failure result obtained in the signal comparing step, in the second storage means for each of the second devices having the plurality of first devices. In parallel with the indexing step of replacing the second device under test with the next second device under test, and the fail information stored in the second storage means. Then pull out the first
A fail information extracting step to be stored in the storage means, and the fail information extracted by the fail information extracting step and the fail information and a location where a failure has occurred are made to correspond to each other based on the result of the test pass / fail. A semiconductor test method is provided which includes a step of specifying a failure occurrence location stored in a storage means.

Further, according to the present invention (claim 2), from the setting for storing fail information, which is the content of a failure result in a semiconductor test, in the first storage means for each first device under test, A preparatory step for selectively switching to a setting stored in the first storage means for each of the second DUTs having a plurality of DUTs;
A logic pattern input step of inputting a signal to the device under test, a signal comparing process of comparing a signal output from the first device under test with a pattern signal serving as a criterion of pass / fail, and a signal comparing process. A first storing step of storing the result of the pass / fail of the test in the second storing means, and a step of storing the fail information obtained in the signal comparing step in the first storing means for each of the second DUTs; An index process of replacing the second device under test with a next second device under test, and extracting the fail information stored in the first storage means in parallel with the index process. A step of extracting fail information stored in the second storage means; and a step of generating the fail information and a failure based on the fail information extracted in the fail information extracting step and the result of the test pass / fail. The semiconductor test method comprising a fail-source identifying process in which a portion in correspondence stored in the second storage means.

According to one embodiment of the present invention, the second
The device under test is a semiconductor wafer, and the first device under test is a semiconductor chip arranged and formed on the semiconductor wafer.

According to another embodiment of the present invention,
The first device under test is a semiconductor wafer, and the second device under test is a lot including a predetermined number of the semiconductor wafers.

According to the present invention (claim 5), a test logic pattern signal is input to a semiconductor device under test, and a signal output from the semiconductor device under test is compared with a determination reference pattern. The semiconductor device under test is used in a semiconductor test system for determining the quality of the semiconductor device under test and extracting fail information which is the content of the failure result. The storage means for storing the fail information, and the fail information stored in the storage means is stored in the second memory. There is provided a fail analysis memory device comprising: a fail information storage amount control unit that stores a plurality of one DUTs for each second DUT.

According to the present invention (claim 6), a test logic pattern signal is input to a semiconductor device under test, and the signal output from the semiconductor device under test is compared with a determination reference pattern. It is used in a semiconductor test system for judging pass / fail of the semiconductor device under test and extracting fail information which is the content of a failure result, and stores a first storage area for storing the fail information and an address of the fail information. A storage unit having a second storage area; an address setting unit for setting the address; and an address set by the address setting unit are set for each of the second DUTs having a plurality of first DUTs. A fail analysis memory device having an address control means is provided.

As a preferred embodiment of the present invention, the storage means further has a third storage area for storing a pattern number of a test logic pattern signal, and the address setting means comprises It is desirable to set the above address.

As a more preferred embodiment of the present invention, the address control means includes a delay circuit for delaying a test end signal detected from the second device under test;
A delayed test end signal supplied from the delay circuit and a first DUT that is tested first among second new DUTs that are tested next to the second DUT. It is desirable to include an AND circuit that outputs a logical AND with the detected test start signal.

In a further preferred aspect of the present invention, the address control means sets a first address based on a test start signal detected from the first DUT; It is desirable to further include switching means for selectively supplying a signal for setting a second address based on a signal supplied from the integrated circuit to the address setting means.

Preferably, the switching means is a multiplexer.

According to one embodiment of the present invention, the second
The device under test is a semiconductor wafer, and the first device under test is a semiconductor chip arranged and formed on the semiconductor wafer.

According to another embodiment of the present invention,
The first device under test is a semiconductor wafer, and the second device under test is a lot including a predetermined number of the semiconductor wafers.

Further, according to the present invention (claim 13), a CPU for issuing various command signals and controlling the entire system.
A storage unit for storing test pass / fail result information and other various information, a control unit having an input / output unit for operating the CPU and displaying information, an internal power supply unit,
Logic pattern generating means for generating a test pattern signal and an expected value pattern signal according to the command of the CPU;
A timing signal generating means for generating a clock pulse for determining a test timing according to a command from the CPU; and a waveform of a test pattern signal supplied from the pattern generating means in accordance with a timing signal supplied from the timing signal generating means. Format control means for outputting the test pattern signal supplied from the format control means by an input driver. A semiconductor test head for outputting to a device under test, comparing a signal inputted from the first device under test with a reference voltage by the signal comparator and outputting the result, and a digital signal supplied from the CPU Is converted into an analog signal, and a reference voltage of the output signal and the input signal is set to thereby set the reference voltage for the semiconductor test. A D / A converter for controlling an input driver and a signal comparator of the semiconductor memory, and a comparator for comparing a comparison result signal supplied from the semiconductor test head with an expected value pattern signal supplied from the logic pattern generator; A measurement unit having pattern value comparison means for outputting information on the result of the pass / fail result and fail information as failure content when a failure has occurred, and a measurement unit having the fail analysis memory device according to claim 5, Provides a semiconductor test system that extracts fail information stored in the fail analysis memory device and stores the fail information in the storage device in parallel with an index process for exchanging the second test object mounted on the prober. Is done.

Further, according to the present invention (claim 14),
CP that controls the entire system by issuing various command signals
U, a storage unit for storing test pass / fail result information and other various information, a control unit having an input / output unit for operating the CPU and displaying information, an internal power supply unit, Logic pattern generating means for generating a test pattern signal and an expected value pattern signal in accordance with a command, timing signal generating means for generating a clock pulse for determining a test timing in accordance with a command of the CPU, and supplied from the timing signal generating means Format control means for shaping and outputting a waveform of a test pattern signal supplied from the pattern generating means by a timing signal, and a prober for mounting a second DUT having a plurality of the first DUTs, The test driver supplies the test pattern signal supplied from the format control means to a first A semiconductor test head that outputs a signal input from the first device under test to a reference voltage by the signal comparator and outputs the result, and a digital signal supplied from the CPU. DA conversion means for controlling the input driver and the signal comparator of the semiconductor test head by setting the reference voltage of the output signal and the input signal by converting the analog signal into an analog signal, and a comparison supplied from the semiconductor test head Pattern value comparing means for comparing a result signal with an expected value pattern signal supplied from the logic pattern generating means, and outputting information of a pass / fail result and fail information which is failure content when a failure occurs, A measurement unit having the fail analysis memory device according to any one of claims 6 to 12;
U is a semiconductor test system that extracts fail information stored in the fail analysis memory device and stores it in the storage device in parallel with an index process for exchanging the second device under test mounted on the prober. Provided.

According to the present invention, the failure information can be extracted in parallel with the index processing of the second DUT only by adding a simple circuit to the conventional fail analysis memory. Fail information can be extracted without depending on the length of the test time of the device under test.

[0034]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Some embodiments of the present invention will be described below with reference to the drawings.

First, a first embodiment of the fail analysis memory according to the present invention will be described with reference to FIG.

FIG. 4 is a circuit diagram including a fail analysis memory 37 which is a first embodiment of the fail analysis memory according to the present invention.

As shown in FIG. 4, the failure analysis memory 3
Reference numeral 7 denotes an address memory 19, a fail pin data memory 20, and an address counter 21 provided in the conventional fail analysis memory shown in FIG. 11, as well as a delay circuit 26 and an AND circuit 27, which are three circuits characteristic of the present invention. And a multiplexer 28.

The delay circuit 26 receives the wafer end signal detected and supplied by the tester pin when all the samples in one wafer have been tested, delays the wafer end signal by a predetermined time, and supplies it to the AND circuit 27. I do.

The AND circuit 27 receives the sample test start signal and the delay signal of the wafer end signal supplied from the delay circuit 26, and outputs a signal of the logical product of these signals, that is, the test start of the first sample after switching the wafer. Only the signal is supplied to the multiplexer 28.

The multiplexer 28 has an input terminal from the AND circuit 27 and a direct input terminal for a test start signal from a sample. One of the two input terminals is selected by a selection signal 29 supplied from the CPU 8. , And supplies a clear signal to the address counter 21 to clear the address counter 21 based on the signal. That is, the multiplexer 28
Switching between clearing the fail information at each test start of the sample and at each test start of the wafer is performed.

The operation of the fail analysis memory 37 shown in FIG. 4 is as follows.

That is, first, as preparation before starting the test, the input of the multiplexer 28 is switched by the CPU. When performing a test based on a test method according to the present invention described later, the input of the multiplexer 28 is switched to the a side. By setting the input of the multiplexer 28 to the a side, the fail analysis memory 37 can store a function fail for each wafer.

When a function failure occurs after the start of the test, the failure information is sequentially stored in the address memory 19 and the fail pin data memory 20.

When the test for one wafer is completed, the test process shifts to the wafer indexing process. In parallel with the indexing process, the CPU 8 causes the fail memory for one wafer stored in the address memory 19 and the fail pin data memory 20 to fail. Extract information. Although it depends on the performance of the tester pin prober, the wafer indexing process generally requires 1 to 2 minutes,
Extraction of fail information is sufficiently possible within this time.

As described above, by performing the fail information extraction processing in parallel during the wafer index processing,
Test time is significantly reduced compared to the prior art. The effect will be specifically described with reference to FIG.

FIG. 6 shows the total wafer processing time when a wafer composed of n samples is tested by the conventional technique in the upper part, and the wafer processing time when the same wafer is tested by the method according to the present invention in the lower part. FIG. In the conventional technique, fail information is extracted after the chip index processing, so that the total processing time T _P is T _P = (T ₁ + T ₂ + T ₃ ) × n + T ₅ .

On the other hand, in the present invention, since the fail information extraction processing is performed in parallel with the wafer index processing, the total processing time T _I becomes T _I = (T ₁ + T ₃ ) × n + T ₅ , and T _P − The processing time can be reduced by T _I = T ₂ × n [s].

Returning to FIG. 4, fail information is extracted.
When the wafer indexing process is completed, a test start signal for the first sample of a new wafer is input to the multiplexer 28, whereby the multiplexer 28 outputs a clear signal. The data stored in the fail pin data memory 20 is erased.

The operation of outputting the data clear signal will be described with reference to the time chart of FIG.

When the input of the multiplexer 28 is set to the a side by the CPU 8, the test start signal for each sample is input not to the multiplexer 28 but to the AND circuit 27.
6, the output of the AND circuit 27 is "0".
And the multiplexer 28 includes the address counter 21
Does not output a clear signal.

When all the samples in the wafer have been tested, a wafer end signal that outputs “1” during the wafer index is input to the delay circuit 26.

Immediately after the wafer index is completed and the wafer end signal becomes “0”, a test start signal for the first sample is input to the AND circuit 27.
Since it is input to the AND circuit 27 with a delay of T seconds, AND
The circuit 27 outputs the logical product “1” to the multiplex circuit 28.
Thus, the multiplexer 28 outputs a clear signal to the address counter 21.

As described above, the fail analysis memory according to the present invention is provided with the switching means for selecting the storage of the fail information for each sample and the storage of the fail information for each wafer, so that the fail information is stored for each wafer. Can be done. Further, since the extraction of the stored fail information is performed in parallel with the processing of the wafer index, a highly efficient semiconductor test can be performed without being affected by the test time of the sample.

Next, an embodiment of a semiconductor test system according to the present invention will be described with reference to the drawings.

FIG. 7 is a block diagram showing the configuration of the first embodiment of the semiconductor test system according to the present invention.

The semiconductor test system 80 shown in FIG.
It comprises a measuring unit 100 for measuring various characteristics of the DUT and a control unit 200 for controlling the same.

The control unit 200 includes a CPU 8 such as a microprocessor, a storage device 220 such as a magnetic disk device and a hard disk device, and an input / output device 230 such as a keyboard and a line printer.

The measuring section 100 is a logic pattern generator 1 for generating a test pattern signal according to a command from the CPU 8.
20, a timing generator 110 for generating a clock pulse for determining test timing, a timing generator 11
A format controller 130 for shaping the waveform of the test pattern signal based on the pulse signal of 0, a DA converter 170 for converting a digital signal supplied from the CPU 8 into an analog signal, and outputting the test pattern signal to the DUT and incorporating the same. DUT by signal comparators 155 and 156
Semiconductor test head 150 for comparing a signal input from the device with a reference voltage, a pattern value comparator 140 for comparing and analyzing a signal of the comparison result with an expected value pattern signal, and a fail analysis memory for storing information of the analysis result 37 and a programmable power supply 190.

The logic pattern generator includes the logic pattern generator 2 shown in FIG. 4, and the pattern value comparator 140 has the logic comparison circuit 6 shown in FIG.

The operational relationship between the components is as follows.

First, in response to a command from the CPU 8, the logic pattern generator 120 generates a pattern signal for a functional test and sends it to the format controller 130. The logic pattern generator 120 drives a signal to the DUT and also outputs a signal as to whether or not to compare the signal from the DUT with an expected value for each pattern.

The timing generator 110 has a CPU
In response to the instruction of No. 8, a functional test cycle and timing pulses for rising and falling of the clock pulse are generated and sent to the format controller 130.

Next, the format controller 130
Is used to shape a test pattern signal of logic “1” and logic “0” generated from the logic pattern generator 120 into a predetermined waveform mode by a timing pulse supplied from the timing generator 110, and to the semiconductor test head 150. send.

On the other hand, the DA converter 170 converts the digital signal supplied from the CPU 8 into an analog signal,
The level of the input pattern to the DUT 300 of the semiconductor test head 150 and the determination level of the output pattern from the DUT 300 are set. Next, the semiconductor test head 1
Reference numeral 50 designates the voltage level of the test pattern signal supplied from the format controller 130 by the test pattern input driver 151 whose level is set by the DA converter 170, and the DU is set via a tester pin (not shown).
Apply to input pin of T300.

Further, the semiconductor test head 150 has a D
The signal output from the UT 300 in response to the input test pattern signal is received via a tester pin (not shown), and is compared by the signal comparators 155 and 156 with the reference voltage set by the DA converter 170. The comparison result is sent to the pattern value comparator 140. At this time, among the input signals from the DUT, a high level signal is a high level signal comparator 155.
, And the low-level input signal is compared and determined by the low-level signal comparator 156.

Next, the pattern value comparator 140 compares the comparison result signal supplied from the signal comparators 155 and 156 of the semiconductor test head 150 with the expected value, and sends the comparison result to the fail analysis memory 37. The expected value includes a logic “1”, a logic “0”, and a high impedance state. In addition, the information on the comparison result includes information on a test result of pass / fail of each pin, an address position of a test pattern in which a defect occurs, and the like.

The fail analysis memory 37 stores the information of the comparison result supplied from the pattern value comparator 140.

The CPU 8 retrieves the fail information stored in the fail analysis memory 37 for each DUT sample or wafer and stores it in the storage device 220.

Thereafter, the information is used for failure analysis of the DUT 300, debugging of a functional test pattern, and the like, and is used for research and development.

By repeating the above operation for various logic patterns, the quality of the DUT is determined.

Since the semiconductor test system 80 shown in FIG. 7 employs the fail analysis memory 37 according to the present invention shown in FIG. 4 as the fail analysis memory, fail information can be stored for each wafer. Since the failure information can be extracted in parallel with the wafer index processing, highly efficient semiconductor testing can be performed regardless of the length of the test time per DUT.

Next, a first embodiment of the semiconductor test method using the semiconductor test system according to the present invention will be described with reference to the flowchart of FIG.

First, as a test preparation, the CPU 8 sets the input of the multiplexer 28 provided in the fail analysis memory 37 to the fail information storage for each wafer in the semiconductor test system 80 shown in FIG. 7 (step S100). The test is started by setting the DUT in (steps S105 and S110).

The pass / fail record in the test is shown in FIG.
Is performed using a wafer matrix 30 shown in FIG.

That is, in each test order, a data array of numbers and the like in which the addresses of the samples and the results of the pass / fail are classified by category are set in advance, and these are made to correspond to the results of the test. The data is stored in the storage device 220 (step S210). In this embodiment, as shown by an arrow 31 in FIG. 9A, the sample (1, 1) to the sample (1, 3)
The test is performed in the right direction, and then the test is continued to the rightmost sample (2, 5) in the second stage from the closest top stage, and then the test continues in the left direction in the same stage. Also,
The test result passes the pass: “00”, DC fail,
That is, a failure in a DC test in which a current is applied to a DUT to measure a voltage or a voltage is applied and a current is measured is classified into “01”, and a failure in a logic test is classified into an FC failure: “10”. ing.

As described above, when a defect occurs while recording the test results for each sample (step S
120), and stop the logic test (step S13)
0), the contents of the fail are recorded in the address memory 19 of the fail analysis memory 37 and the fail pin data memory 20 (step S140). In FIG. 9A,
It is shown that a DC failure occurred in samples (1, 2) and an FC failure occurred in samples (1, 3) and (2, 5), while a failure occurred at address 1 in FIG. It can be seen that fail information 2 is stored in information 1 and address 2.

When the test of all the samples in the wafer is completed (steps S150 and S160), the failure information stored in the failure analysis memory 37 is taken out in parallel with the wafer index processing (step S300) (step S400). The contents of the wafer map, which is the entire test result stored in the storage device 220, are associated with the fail information (step S410), and are stored in another storage area different from the storage area of the wafer map (step S410). S420).

In the example of FIG. 9, the sample (1, 3) is stored in the other storage area corresponding to the fail information 1 and the sample (2, 5) is stored in the other storage area corresponding to the fail information 2.

As described above, even if the fail analysis memory stores only the fail information which is the contents of the failure, the fail of any sample can be determined by associating with the pass / fail result recorded in the wafer map. The occurrence can be recorded. When the wafer index process is completed and the test start signal of the first sample of the next wafer is detected (step S310), the address counter 21 sets the information stored in the address memory 19 and the fail pin data memory 20 of the fail analysis memory 37. Is cleared (step S320).

Thereafter, the fail information corresponding to the sample address is taken out after all the tests are completed, and is used as important data for failure analysis / debugging.

As described above, in the semiconductor test method according to the present invention, the fail information is taken out in parallel with the processing of the wafer index, so that a high-speed wafer test can be performed regardless of the test time per sample. Test time can be greatly reduced. Further, since the location where the extracted fail information is generated can be easily specified by the wafer map, the fail analysis can be performed at a high speed.

Next, a second embodiment of the fail analysis memory according to the present invention will be described with reference to FIG.

In the first embodiment, it is assumed that one test pattern is tested by one test number. However, today, when the degree of integration of a semiconductor device as a DUT has become extremely high, a plurality of test patterns are often tested with one test number. The fail analysis memory 37 according to the first embodiment cannot determine which pattern the extracted fail memory corresponds to.

Therefore, the fail analysis memory 47 according to the second embodiment facilitates the correspondence between the fail information extracted when a plurality of test patterns are tested and the test patterns.

FIG. 1 is a circuit diagram including the fail analysis memory 47.

In FIG. 1, a register 32 is a register for storing a pattern name to be tested, and a register memory 33 provided in a fail analysis memory 47 is a memory for storing the contents of the register 32. That is, the fail analysis memory 47 has a configuration in which the register memory 33 is further provided in the fail analysis memory 37 according to the first embodiment described above.

Fail analysis memory 4 in this embodiment
7 is basically the same as that of the fail analysis memory 37 of the first embodiment described above, except that the pattern name to be tested is always stored in the memory of the register memory 33. is there. That is, the failed test pattern name is stored in the register memory 33, and the fail information extraction processing performed in parallel with the wafer index processing is performed in the register memory together with the fail information stored in the address memory 19 and the fail pin data memory 20. The test pattern name stored in 33 is extracted at the same time.

As described above, according to the fail analysis memory 47 according to the second embodiment of the present invention, even in a semiconductor test in which a plurality of test patterns are tested with one test number, a failure is determined for each wafer. Since information can be stored and fail information including the test pattern name can be extracted in parallel with the wafer index processing, a highly efficient test can be performed without being affected by test time even in a complicated semiconductor test. Can be implemented.

Next, a second embodiment of the semiconductor test system according to the present invention will be described with reference to FIG.

FIG. 2 is a block diagram showing a configuration of a semiconductor test system 90 provided with the above-mentioned fail analysis memory 47.

The semiconductor test system 90 shown in FIG.
It has substantially the same configuration as the above-described semiconductor test system 80, and its operation is also substantially the same. The difference is that the above-described fail analysis memory 47 is provided as a fail analysis memory.

Therefore, the semiconductor test system 90 of the present embodiment can obtain the same effects as those of the semiconductor test system 80 in a semiconductor test in which a plurality of test patterns are tested with one test number.

Next, the second method of the semiconductor test method according to the present invention will be described.
An embodiment will be described with reference to the drawings.

The semiconductor test method according to the present embodiment
This is a test method when a plurality of test patterns are tested with one test number, and is performed using the semiconductor test system 90 which is the second embodiment of the semiconductor test system according to the present invention. Therefore, the procedure itself is substantially the same as the procedure shown in the flowchart of FIG. 9, but it is necessary to associate the name of the test pattern with the stored fail information. Are different from each other.

FIG. 3 shows the wafer matrix 40 used in the semiconductor test method according to the present embodiment and the corresponding fail information stored in the register memory 33, the address memory 19 and the fail pin data memory 20 in the fail analysis memory 47. FIG.

In this embodiment, as a data array in which the results of the pass / fail of the test are classified so as to include the test pattern names, “10” to “19” are DC fail, and “2” are “2”.
“0” to “29” are set as FC failures. FIG. 3A shows the DC failure “1” in the sample (1, 2).
0 ”occurs, the sample (1, 3) has an FC fail“ 20 ”, and the sample (2, 5) has an FC fail“ 2 ”.
1 ”has occurred, while FIG.
It can be seen that fail information 1 is stored at address 1 and fail information 2 is stored at address 2.

Therefore, after the fail information is taken out in parallel with the wafer index processing, the fail information shown in FIG. 3B corresponds to the contents of the wafer map 40 shown in FIG. Is stored in

In the example of FIG. 3, as in the example of FIG.
The sample (1, 3) is stored in another storage area corresponding to the fail information 1 and the sample (2, 5) is stored in the other storage area corresponding to the fail information 2.

As described above, in the second embodiment of the semiconductor test method according to the present invention, even in a semiconductor test having a plurality of test patterns, the fail information is taken out in parallel with the wafer index processing. A high-speed wafer test can be performed regardless of the test time per unit. As a result, the entire test time can be significantly reduced. Further, since the location of the extracted fail information and the test pattern can be easily specified by the wafer map, the fail analysis can be performed at a high speed.

In the above embodiment, the case where the fail information is stored for each wafer and the fail information is extracted in parallel with the processing of the wafer index has been described. For example, in the test process in the case of mass production, Fail information may be stored for each lot, and fail information of a lot that has already been tested may be extracted in parallel with the index processing of the next lot.

[0101]

As described above in detail, the fail analysis memory according to the present invention, the semiconductor test system using the same, and the semiconductor test method using the same have the following effects.

That is, in the semiconductor test method according to the present invention (claim 1), the fail information is stored in the second
And the fail information thus stored is retrieved in parallel with the indexing process, so that a high-speed test can be performed on the second DUT regardless of the test time of the first DUT. This makes it possible to significantly reduce the overall test time. Further, since the location where the extracted fail information is generated can be easily specified by associating it with the test result stored in the first storage means, there is an effect that the fail analysis can be performed at a high speed.

Further, in the semiconductor test method according to the present invention (claims 2 to 4), the failure information is selectively set from the setting for storing the fail information for each first test object to the setting for storing the fail information for each second test object. Since the method further includes a preparation process for switching to the conventional method, the semiconductor test method having the above-described effect can be selectively used with the conventional test method.

The present invention (claims 5, 6, 8 to 1)
According to 2), the fail information stored in the storage means is stored in the first
Is provided for each of the second DUTs having a plurality of DUTs, regardless of the test time of the first DUT. , A high-speed test can be performed, the entire test time can be greatly reduced, and a fail analysis memory device with high throughput can be provided.

The present invention (claims 7, 8 to 12)
According to the above, in addition to the above-described effects, fail information is stored for each pattern name of a logic pattern. Therefore, even in a semiconductor test in which a plurality of test patterns are tested with one test number, a fail for each second test object is performed. Since the information can be stored, there is an effect that a fail analysis memory device capable of performing a high-speed test without being affected by a test time even in a complicated semiconductor test is provided.

Further, in the fail analysis memory device according to the present invention (claims 9 to 12), switching between storage of fail information for each first test object and storage of fail information for each second test object is performed. Since there is provided the means, there is an effect that a fail analysis memory device which can be used for both the semiconductor test method according to the prior art and the semiconductor test method according to the present invention is provided.

Further, according to the present invention (claims 13 and 14), a fail analysis memory device having the above effect is provided, and fail information is taken out in parallel with the index processing, so that the test time of the first DUT is reduced. Regardless of the magnitude of the test, the second test object can be tested at high speed, and the overall test time can be significantly reduced.
There is an effect that a semiconductor test system with high throughput is provided.

[Brief description of the drawings]

FIG. 1 is a circuit diagram including a fail analysis memory according to a second embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a second embodiment of the semiconductor test system according to the present invention.

FIG. 3 is a conceptual diagram for explaining a semiconductor test method according to a second embodiment of the present invention. That is, FIG.
FIG. 3 is a conceptual diagram showing a wafer matrix used in the semiconductor test method according to the present embodiment, and FIG.
FIG. 4 is a conceptual diagram showing fail information stored in a fail analysis memory.

FIG. 4 is a circuit diagram including a first embodiment of a fail analysis memory according to the present invention.

FIG. 5 is a time chart showing an operation relationship among a delay circuit, an AND circuit, and a multiplexer.

FIG. 6 is an explanatory diagram showing a comparison between a test time in a test method according to a conventional technique and a test time in a test method according to the present invention.

FIG. 7 is a block diagram showing a configuration of a first embodiment of a semiconductor test system according to the present invention.

FIG. 8 is a flowchart illustrating a procedure of an embodiment of a semiconductor test method using the semiconductor test system according to the present invention.

FIG. 9 is a conceptual diagram for describing a first embodiment of a semiconductor test method according to the present invention. That is, FIG.
FIG. 9 is a conceptual diagram showing a wafer matrix used in the semiconductor test method according to the present embodiment, and FIG.
FIG. 4 is a conceptual diagram showing fail information stored in a fail analysis memory.

FIG. 10 is a block diagram schematically illustrating a logic test method in a general-purpose LSI function test.

FIG. 11 is a block diagram showing a configuration of one specific example of a fail analysis memory according to a conventional technique.

[Explanation of symbols]

2 Logic Pattern Generator 6 Logic Comparison Circuit 7 Fail Analysis Memory by Conventional Technique 8 CPU 19 Address Memory 20 Fail Pin Data Memory 21 Address Counter 26 Delay Circuit 27 AND Circuit 28 Multiplexer 32 Register 33 Register Memory 37 Fail Analysis According to the Present Invention The first embodiment of the memory 47 The second embodiment of the fail analysis memory according to the present invention 80 The first embodiment of the semiconductor test system according to the present invention 90 The second embodiment of the semiconductor test system according to the present invention Embodiments 100 and 101 Measuring Unit 110 Timing Generator 120 Logic Pattern Generator 130 Format Controller 140 Pattern Value Comparator 150 Semiconductor Test Head 151 Test Pattern Input Driver 155 High Level Comparator 56 low level comparator 170 D-A converter 180 DC test unit 190 the programmable power supply 200 controller 220 storage 230 output device 300 DUT

Claims (14)

[Claims] 1. A logic pattern input step of inputting a test logic pattern signal to a first device under test, and comparing a signal output from the first device under test with a pattern signal serving as a criterion of pass / fail. A signal comparison process to be performed, and the result of the test pass / fail obtained by the signal comparison process is
A first storage step of storing in a storage means, and fail information, which is the content of the failure result obtained in the signal comparing step, is stored in a second storage unit for each of the second DUTs having a plurality of the first DUTs. A second storage step of storing in the storage means, an indexing step of replacing the second DUT for which the test has been completed with a next second DUT, and the second storage step of storing in the second storage means. Fail information extracting step of extracting fail information in parallel with the indexing step and storing it in the first storage means; and fail information based on the fail information extracted in the fail information extracting step and the result of the test pass / fail. And a failure occurrence location specifying step of storing the failure occurrence location in the first storage means in association with the failure occurrence location. 2. A second test apparatus having a plurality of first test objects from a setting for storing fail information, which is the content of a failure result in a semiconductor test, in first storage means for each first test object. A preparatory step for selectively switching to a setting stored in the first storage means for each body; a logic pattern inputting step of inputting a test logic pattern signal to the first DUT; A signal comparing step of comparing a signal output from the test body with a pattern signal serving as a criterion of pass / fail, and a result of the test pass / fail obtained in the signal comparing step is referred to as a second
A first storing step of storing the fail information obtained in the signal comparing step in the first storing means for each of the second DUTs; An index step of replacing the second DUT with the next second DUT; and extracting the fail information stored in the first storage means in parallel with the indexing step, and extracting the fail information to the second storage means. A fail information extracting step to be stored; fail information extracted in the fail information extracting step; and storing the fail information and a location where a failure has occurred in the second storage means in correspondence with the result of the test pass / fail. A semiconductor test method including a step of identifying a failure occurrence location. 3. The semiconductor device according to claim 1, wherein the second device under test is a semiconductor wafer, and the first device under test is a semiconductor chip arranged on the semiconductor wafer. 3. The semiconductor test method according to 2. 4. The device according to claim 2, wherein the first device under test is a semiconductor wafer, and the second device under test is a lot including a predetermined number of the semiconductor wafers. Semiconductor test method. 5. A test logic pattern signal is input to a semiconductor device under test, and a signal output from the semiconductor device under test is compared with a determination reference pattern to determine pass / fail of the semiconductor device under test. A second storage unit that is used in a semiconductor test system that extracts fail information that is the content of a failure result and that stores the fail information; A fail analysis memory device comprising: a fail information storage amount control unit that stores the information for each test object. 6. A test logic pattern signal is input to the semiconductor device under test, and the signal output from the semiconductor device under test is compared with a judgment reference pattern to determine pass / fail of the semiconductor device under test. Storage means for use in a semiconductor test system for extracting fail information as the content of a failure result, the storage means having a first storage area for storing the fail information, and a second storage area for storing an address of the fail information; A fail analysis memory device comprising: an address setting means for setting the address; and an address control means for setting an address set by the address setting means for each of the second DUTs having a plurality of first DUTs. . 7. The storage means further includes a third storage area for storing a pattern number of a test logic pattern signal, and wherein the address setting means sets the address for each of the pattern numbers. The fail analysis memory device according to claim 6, wherein: 8. An address control means, comprising: a delay circuit for delaying a test end signal detected from the second device under test; a delayed test end signal supplied from the delay circuit; An AND circuit that outputs an AND with a test start signal detected from a first new DUT that is tested first among second new DUTs that are tested next to the DUT. The fail analysis memory device according to claim 6 or 7, further comprising: 9. The address control means according to claim 1, wherein said address control means comprises:
And a switch for selectively supplying a signal for setting a second address to the address setting means based on a signal supplied from the AND circuit. The fail analysis memory device according to claim 6. 10. The fail analysis memory device according to claim 9, wherein said switching means is a multiplexer. 11. The semiconductor device according to claim 1, wherein the second device under test is a semiconductor wafer, and the first device under test is a semiconductor chip arranged on the semiconductor wafer. 11. The fail analysis memory device according to 9 or 10. 12. The semiconductor device according to claim 9, wherein the first device under test is a semiconductor wafer, and the second device under test is a lot including a predetermined number of the semiconductor wafers.
3. The fail analysis memory device according to 1. 13. A CPU for controlling the entire system by issuing various command signals, a storage means for storing information on results of pass / fail of tests and other various information, and an input / output device for operating the CPU and displaying information. A control unit having an output unit; an internal power supply unit; a logic pattern generating unit configured to generate a test pattern signal and an expected value pattern signal according to a command from the CPU; and a clock pulse determining a test timing according to the command from the CPU. , A format control means for shaping and outputting a waveform of a test pattern signal supplied from the pattern generation means according to a timing signal supplied from the timing signal generation means, A prober for mounting a second test object having a plurality of test objects; The test pattern signal supplied from the means is output to a first device under test by an input driver, a signal input from the first device under test is compared with a reference voltage by the signal comparator, and the result is compared. A semiconductor test head to be output; a digital signal supplied from the CPU being converted into an analog signal to set a reference voltage of an output signal and an input signal to control an input driver and a signal comparator of the semiconductor test head; A DA converter, comparing the comparison result signal supplied from the semiconductor test head with an expected value pattern signal supplied from the logic pattern generator; Pattern value comparing means for outputting fail information indicating the content of the failure, and a measuring unit having the fail analysis memory device according to claim 5. A CPU that extracts fail information stored in the fail analysis memory device and stores the failed information in the storage device in parallel with an index process for exchanging the second test object mounted on the prober Test system. 14. A CPU for issuing various command signals to control the entire system, a storage means for storing information on the results of pass / fail of tests and other various information, and an input / output device for operating the CPU and displaying information. A control unit having an output unit; an internal power supply unit; a logic pattern generating unit configured to generate a test pattern signal and an expected value pattern signal according to a command from the CPU; and a clock pulse determining a test timing according to the command from the CPU. , A format control means for shaping and outputting a waveform of a test pattern signal supplied from the pattern generation means according to a timing signal supplied from the timing signal generation means, A prober for mounting a second test object having a plurality of test objects; The test pattern signal supplied from the means is output to a first device under test by an input driver, a signal input from the first device under test is compared with a reference voltage by the signal comparator, and the result is compared. A semiconductor test head to be output; a digital signal supplied from the CPU being converted into an analog signal to set a reference voltage of an output signal and an input signal to control an input driver and a signal comparator of the semiconductor test head; A DA converter, comparing the comparison result signal supplied from the semiconductor test head with an expected value pattern signal supplied from the logic pattern generator; 13. A fail analysis memory device according to claim 6, further comprising: a pattern value comparing unit that outputs fail information that is the content of the failure. A measurement unit having the following. The CPU extracts the fail information stored in the fail analysis memory device in parallel with an index process for exchanging the second test object mounted on the prober, and A semiconductor test system stored in a storage device.