JPH10313230A - Filter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an all-pass filter which can stably operate without being affected by external impedance by connecting a secondary network to the univerted input side of an operational amplifier and a delay circuit to the inverted input side. SOLUTION: The secondary network 102 is connected to the univerted input side of the operational amplifier 101 and the delay circuit 103 is connected to the inverted input side. Equivalent resistors 104 and 105 and an equivalent inductor 106 are controlled from the outside to control the frequency characteristics and group delay characteristics of the filter. A delay in the network 102 is caused by the equivalent resistor 104, so the equivalent resistor 105 of the same constitution with the equivalent resistor 104 is used as the delay circuit 103. Consequently, the delay of a signal in the net work 102 is canceled and secondary all-pass characteristics which are excellent up to a high frequency range can be obtained on the whole.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a filter, and more particularly, to a filter having an operational amplifier.

[0002]

2. Description of the Related Art FIG. 12 shows the principle of a conventional all-pass filter.

In the figure, 101 is an operational amplifier, 102
Is a network, and R1 and R2 are resistors of the same magnitude. When the circuit network 102 has the configuration as shown in FIG. 13 and has the second-order characteristics shown by the equation (1), the entire circuit of FIG. 12 is a second-order all-pass filter shown by the equation (2). .

[0004]

[Outside 1]

[0005]

However, when the above-mentioned all-pass filter is realized by a transistor circuit, it is difficult to obtain good characteristics up to a high frequency range because the circuit network 102 is not an ideal LCR. Was.

An object of the present invention is to solve the above-mentioned problems.

Another object of the present invention is to provide a filter which can operate stably without being affected by external impedance.

[0008]

In order to solve the above problems and achieve the object, the present invention relates to a filter having an operational amplifier, wherein a secondary network is connected to a non-inverting input side of the operational amplifier. , And a delay circuit connected to the inverting input side.

[0009]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a principle diagram of an all-pass filter to which the present invention is applied.

In the drawing, reference numeral 103 denotes a delay circuit having an impedance corresponding to the resistance R1 in FIG.

FIG. 2 shows an actual circuit configuration.

In FIG. 2, reference numerals 104 and 105 denote equivalent resistances, and 106 denotes an equivalent inductor. By controlling each equivalent resistance and the equivalent inductor from the outside as described later,
The frequency characteristic and the group delay characteristic of the filter can be controlled.

Hereinafter, the equivalent resistance and the equivalent inductor in FIG. 2 will be described.

FIG. 3 is a principle diagram of the equivalent resistors 104 and 105.

In FIG. 3, reference numeral 201 denotes a voltage-to-current conversion element, which converts a voltage between the terminals 1a and 1b into a current and allows the current to flow through the terminal 1b. The terminal 1c is virtually grounded to the midpoint potential of the terminals 1a and 1b.
G ₁ a conversion gain of 01, the current flowing into the terminal 1a i
_11, when the current flowing from the terminal 1b and i _12, the following relationship is established in the circuit of FIG.

I ₁₁ = 0 (3) i ₁₂ = G ₁ × v ₁ (4) Therefore, the impedance seen from the input is

[0018]

[Outside 2] It can be seen that it looks like a resistor from the outside. In the circuit of FIG. 3, the gain of the voltage-current conversion element can be controlled from the CONT terminal.

Next, the equivalent inductor 106 will be described.

FIG. 4 is a principle diagram of the equivalent inductor 106.

In FIG. 4, reference numerals 301 to 303 denote voltage-current conversion elements, respectively. Reference numeral 301 converts a voltage between the terminal 10a and the virtual ground 10c to flow a current to the terminal 20a. Reference numeral 302 converts a voltage between the virtual ground 10c and the terminal 10b to cause a current to flow through the terminal 20b. Further, 303 converts the voltage between the terminals 20a and 20b and
Apply current to

The terminal 10c is virtually grounded to the midpoint potential of the terminals 10a and 10b, and the terminal 20c is connected to the terminals 20a and 2b.
0b is virtually grounded to the midpoint potential.

Here, the conversion gain of 301 and 302 is G
The conversion gain of ₂₀ and 303 is G ₁₀ , the voltage on the primary side is v ₁ ,
The current flowing into the terminal 10a is i ₁₁ , the current flowing out of the terminal 10b is i ₁₂ , the voltage on the secondary side is v ₂ , the current flowing in the terminal 20a is i ₂₁ , and the current flowing out of the terminal 20b is i ₂₂
Then, the following relationship holds in the circuit of FIG.

[0024]

[Outside 3] Therefore, the impedance seen from the primary side when a capacitor is connected to the secondary side is

[0025]

[Outside 4] (8), indicating the characteristics of the inductor. In the circuit of FIG. 6, the gain of the voltage-current converter can be controlled from the CONT terminal.

As described above, in the equivalent resistance shown in FIG. 3 and the equivalent inductor shown in FIG. 4, since the current output terminal is only 1b or 10b, it is hardly affected by the external impedance of the terminal 1a or 10a, and stable operation is achieved. It becomes possible. Therefore, by using the inductor of the present embodiment, a filter whose characteristics are stable up to a high frequency region can be used as an I
It becomes possible to integrate in a C chip.

In FIG. 2, since the delay in the circuit network 102 is generated by the equivalent resistance 104, an equivalent resistance having the same configuration as that of the delay circuit 104 is used as the delay circuit 103. As a result, the signal delay in the circuit network 102 is canceled, and a good second-order all-pass characteristic can be obtained as a whole up to a high frequency range.

Next, FIG. 5 shows the principle of an all-pass filter according to another embodiment of the present invention. In this embodiment, the resistance R
1 and a delay circuit 107 is provided in series.

FIG. 6 shows an actual circuit configuration.

In FIG. 6, R
4. A low-pass filter composed of C2 is used.
Here, the impedance of the low-pass filter 107 is represented by R
If it is made sufficiently smaller than 1, it is possible to obtain the characteristics of a secondary all-pass filter having no practical problem up to a high frequency range.

Next, a digital VTR to which the filter of the above embodiment is applied will be described.

FIG. 7 is a diagram showing a configuration of a digital VTR to which the present invention is applied.

In FIG. 7, a magnetic head 4 for tracing a magnetic tape 401 on which data such as images and sounds is recorded.
02 from the head amplifier 40
3. The signal is amplified by 50 to 60 dB.

The reproduction signal from the head amplifier 403 has its frequency and amplitude characteristics controlled by a reproduction equalizer 404 having a configuration described later, and is output to a data detection circuit 405.

The data detection circuit 405 includes the reproduction equalizer 4
The digital data is detected by comparing the level of the data equalized by 04 with a predetermined threshold, and is output to the D-flip-flop 410 and the phase detection circuit 406.

The phase detection circuit 406 is the data detection circuit 40
The phase difference between the output data from S.5 and the clock from the multiplication circuit 409 is detected and output to the loop filter 407 as a phase error signal.

The loop filter 407 performs a filtering process on the phase error signal and negatively feeds back to the oscillator 408 and the reproduction equalizer 404. The signal output from the oscillator 408 is multiplied by a frequency multiplier 409 to double the frequency, and the D-flip-flop 410 and the demodulator 41
It is output as one operation clock.

With this configuration, a clock phase-synchronized with the reproduced data can be stably obtained.

The D flip-flop 410 latches the output data of the data detection circuit 405 according to the above-mentioned clock, and outputs the latched data to the demodulator 411. The demodulator 411 performs digital demodulation processing on the latched data and outputs the data to the error correction decoding circuit 412.

The error correction decoding circuit 412 corrects an error in the reproduced data using the parity data added at the time of recording, and the signal processing circuit 413 performs inverse quantization opposite to that at the time of recording.
The reproduction data is restored by performing processing such as inverse DCT.

Next, the equalizer 404 in FIG. 7 will be described.

FIG. 8 is a diagram showing the configuration of the reproduction equalizer 404. In a digital VTR, a wide band pulse waveform is transmitted, so that a group delay characteristic in a pass band in an equalizer needs to be as flat as possible. If the group delay characteristic is not flat, distortion on the screen such as ringing and smear is conspicuous, and a satisfactory filter circuit is not obtained simply by satisfying the specification of the amplitude characteristic.

Therefore, in the present embodiment, as shown in FIG. 8, a group delay filter is provided after the one-stage LC network, and the group delay characteristic of the amplitude filter is corrected. It is assumed that the amplitude and group delay characteristics of the amplitude filter of FIG. 8 are shown in FIGS. 9A and 9B. In order to correct the group delay characteristic of this amplitude filter, a parallel LC network and a two-stage group delay filter composed of an operational amplifier and a parallel LC network are used, and the group delay characteristic shown in FIG. , And a ripple remains in the band as shown in FIG. 9D as a total characteristic, but an approximately flat group delay characteristic can be obtained.

In the equalizer of FIG. 8, a resistor network is provided in which an equivalent resistor ER1517 is connected in series with the resistor R1501 of the amplitude filter, and the equivalent resistor of this resistor network is constituted by the equivalent resistor shown in FIG. 3 to control the resistance value. It is possible.

The group delay filter 1 and the group delay filter 2 are constituted by the all-pass filter shown in FIG. 2, and R ₂ 505, R ₄ 507, L ₂ 508 and
R ₅ 511, R ₇ 513, L ₃ 514 of the group delay filter 2
Can be controlled. Next, the cutoff frequency f ₀ and Q (Quality Factor) of the amplitude filter shown in FIG.

[0046]

[Outside 5] By controlling the equivalent resistance ER ₁ and the equivalent inductor L ₁ , the cutoff frequency and Q value of the amplitude filter can be controlled.

That is, for example, when the cutoff frequency of the amplitude filter is changed by controlling the inductance to achieve the target frequency characteristic, the value of Q greatly changes depending on the inductance. As a result, will produce a peak in gain at the cutoff frequency, in this embodiment, since the control equivalent resistance ER ₁ using the same control signal as the control signal of the equivalent inductor, with the change of the cutoff frequency It is possible to prevent the value of Q from greatly changing.

The cutoff frequency f _{0 of the} group delay filter 1
And Q are

[0049]

[Outside 6] By controlling the equivalent resistance R4 and the equivalent inductor L2, the cutoff frequency and Q of the group delay filter can be controlled.

As described above, since the equivalent resistance R4 is controlled using the same control signal as that of the equivalent inductor also for the group delay filter, the value of Q greatly varies with the change of the cutoff frequency. Can be prevented.

Therefore, the cut-off frequency can be adjusted to the target frequency by the feedback loop, and the fluctuation of Q can be suppressed to a small value. Thus, a filter circuit having excellent amplitude characteristics and group delay characteristics can be realized on an integrated circuit. Can be.

Since the circuit shown in FIG. 2 is used as the all-pass filter, the influence of external impedance can be reduced, and an equalizer with stable characteristics up to a high frequency range can be realized.

FIG. 10 is a diagram showing the configuration of the oscillator 408 in the present embodiment.

In FIG. 10, a voltage-controlled current source 520 drives a secondary filter (resonant circuit) using L ₄ and C ₄ ,
The resonance frequency of the secondary filter

[0055]

[Outside 7] To oscillate.

When the reference current of the gyrator shown in FIG. 4 is the center value, the frequency characteristic of the filter 4 that determines the oscillation frequency of the oscillator 408 is as shown in FIG. ) Since the characteristic has a sharp peak at fb / 2 which is 1/2 of fb, fb
It oscillates with / 2 as the center frequency. And the oscillator 40
8 is multiplied by a frequency multiplier 209 to double the frequency.
The clock b is supplied to the digital circuit for reproduction.

In this embodiment, the inductor L ₄ of FIG. 10 is constituted by the equivalent inductor shown in FIG.
04 and controls the oscillation frequency by controlling the inductor L ₄ by the same output of the loop filter 407,
A clock synchronized with the reproduction data can be obtained.

If the values of the capacitors C ₃ and C ₄ used in the group delay filters 2 and ₄ are the same,
The cutoff frequency of the group delay filter 2 including the stray capacitance of the gyrator can always be fb / 2, and the value C ₂ of the capacitor used in the group delay filter 1 can be easily obtained based on the group delay filter 2. it can.

As described above, the equivalent resistance and the equivalent inductor of each filter are the equivalent resistance and the equivalent inductor shown in FIGS. 3 and 4, and the variation of the absolute value of the R value and the C value of each filter is used for data detection. Oscillator 40 obtained from the PLL circuit of FIG.
8 by controlling the gyrator and the equivalent resistance in each filter of the reproduction equalizer by using the same control signal as the control current of the gyrator (inductor), which is the control signal of No. 8, and adjusting the cutoff frequency to a regular frequency. A change in characteristics can be reduced, and stable characteristics up to a high frequency range can be realized.

[0060]

As described above, according to the present invention,
Since a delay circuit is connected to the non-inverting input side of the operational amplifier,
A filter with good high-frequency characteristics can be realized.

[Brief description of the drawings]

FIG. 1 is a principle diagram of an all-pass filter as an embodiment of the present invention.

FIG. 2 is a diagram illustrating a configuration of a circuit in FIG. 1;

FIG. 3 is a principle diagram of equivalent resistance of the circuit of FIG. 2;

FIG. 4 is a principle diagram of an equivalent inductor of the circuit of FIG. 2;

FIG. 5 is a diagram showing a configuration of an all-pass filter as another embodiment of the present invention.

FIG. 6 is a diagram showing a configuration of the circuit of FIG. 5;

FIG. 7 is a diagram showing a configuration of a digital VTR as an embodiment of the present invention.

FIG. 8 is a diagram showing a configuration of a reproduction equalizer in FIG. 7;

FIG. 9 is a diagram for explaining characteristics of the equalizer of FIG. 8;

FIG. 10 is a diagram showing a configuration of an oscillator in FIG. 7;

FIG. 11 is a diagram for explaining the operation of the circuit in FIG. 10;

FIG. 12 is a diagram showing a configuration of a conventional all-pass filter.

FIG. 13 is a diagram showing a configuration of the circuit of FIG. 12;

[Explanation of symbols]

 104 Equivalent resistance 106 Equivalent inductor

Claims (6)

[Claims] 1. A filter having an operational amplifier, wherein a secondary circuit network is connected to a non-inverting input side of the operational amplifier, and a delay circuit is connected to an inverting input side. 2. The two-terminal circuit according to claim 1, wherein the delay circuit has one terminal and a second terminal, and has a differential configuration with respect to an input. And a voltage-current converter having a current output connected to the second terminal, wherein the first terminal is not connected to a current output of the voltage-current conversion element. The filter according to claim 1, further comprising an equivalent resistance circuit described above. 3. The filter according to claim 2, wherein a secondary network connected to the non-inverting side has the equivalent resistance. 4. The filter according to claim 3, further comprising control means for controlling an equivalent resistance in the delay circuit and an equivalent resistance in the secondary network. 5. The filter according to claim 4, wherein said control means controls a conversion gain of said current-voltage conversion means. 6. The secondary circuit network connected to the non-inverting input side further includes a plurality of voltage-current conversion means, and both the primary side and the secondary side have a differential configuration with respect to the input. A two-terminal pair circuit, wherein the third terminal and the fourth terminal
A secondary terminal is constituted by the fifth terminal and the sixth terminal, and a voltage between the third terminal and the virtual ground on the primary side is input, and a current is supplied to the secondary terminal. A second voltage-current converter having an output connected to the fifth terminal, and a voltage between the virtual ground on the primary side and the fourth terminal, and a current output corresponding to the sixth voltage. A voltage between the fifth terminal and the sixth terminal, and a current output connected to the fourth terminal. A fourth voltage-to-current converter, an equivalent inductor having the third terminal not connected to the current output of any of the voltage-current converters in the circuit, Controlling the equivalent inductor by the same control signal as the control signal. Filter according to Motomeko 5.