JPH10313096A - Complementary semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable a complementary semiconductor device to be lessened in power consumption and enhanced in operation speed by a method wherein a source, a drain, and a gate electrode are provided to each semiconductor layer of a P-type channel and an N-type channel respectively, and the source and drain region of a field effect transistor is formed of a semiconductor layer of low resistance. SOLUTION: A first I-GaAs layer 11 as a buffer layer, an I-InGaAs layer 12 as a P-type channel layer, a P-AlGaAs barrier 13, a second I-GaAs layer 14 as an isolation layer, and an I-InGaAs layer 15 as an N-type channel layer are sequentially formed on a semi-insulating GaAs substrate 10. The I-InGaAs layer 15 and the second I-GaAs layer 14 are removed through selective etching, their surfaces are exposed like stepped surfaces, a source, a drain, and gate electrodes, 40 and 41, are formed, and impurities are heavily doped to a source and a drain region for the formation of a P<+> -GaAs contact layer 30 of low resistance.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a complementary semiconductor device and a method for manufacturing the same. For more information,
The present invention relates to a complementary semiconductor device using a group III-V compound semiconductor which can operate at high speed with low power consumption and a method for manufacturing the same.

[0002]

2. Description of the Related Art At present, complementary circuits (CMOS) using Si-MOS are widely used as devices with high integration because of low power consumption.

On the other hand, from the demand for further lower power consumption,
2. Description of the Related Art Conventionally, a complementary element using a compound semiconductor that can operate at high speed with low power consumption has been actively developed.

[0004] The problem here is to improve the performance of the p-type element. For example, in the case of GaAs, the mobility of electrons is several times faster than that of Si, but the mobility of holes is the same as that of Si or becomes slower than Si when doped.
The high speed of the mold element cannot be utilized.

In order to improve the mobility of the p-type element,
HEMT (High Electron Mobi) using 3D electron gas
AlGaAs / GaAs as in the case of the Altitude Transistor)
To form a two-dimensional hole gas,
Using this method (RAKiehl et al., IEEE Electron
Device Letters EDL-5 p521, 1984) and a method of improving the mobility of p-type impurities by changing the band structure using a strained lattice (PPRuden et al. IEEE Transaction on Electrode).
n Device Vol. 36, p2371, 1989) has been attempted, and a performance higher than that of p-type Si has been obtained.

A problem in the process of manufacturing a compound complementary element is to perform element formation so that both p / n elements operate with high performance.
For this reason, as shown in FIG. 12, RPDaniels et al. Make a heterostructure with intrinsic (i-) GaAs and i-AlGaAs, and make p / n-type devices by ion implantation of p / n dopants (see FIG. 12). IEDM Technical Digest, p4
48,1986). Fabrication by ion implantation is also performed by a Si process, and is the most effective method in terms of ease of fabrication.

As a method of not performing ion implantation, Hiraoka (Japanese Patent Application Laid-Open No. 61-147577) and Kuroda (Japanese Patent Application Laid-Open No.
No. 1-274369), Al
A p-type (p-) field-effect transistor (FET) and an n-type (n-) PET are formed in a laminated structure with a GaAs / GaAs-based material, and a part of the substrate is etched to form a stepped p / n element. It is a common method to make differently. FIG.
FIG. 3 shows an example of this. In this case, for example, citric acid or CC
If selective etching of AlGaAs / GaAs using l ₂ F ₂ or the like is performed, fabrication is easy.

[0008]

However, the conventional method of manufacturing a complementary element has the following problems.

In the ion implantation method, a p / n-FET can be manufactured only by separately p / n-type dopants on the same substrate, so that a complementary element can be manufactured most easily. The epi-structures of the n-FETs have the same structure, and there is a restriction that it is not possible to take the respective optimum structures for high performance. As a more serious problem, in ion implantation, it is necessary to perform high-temperature annealing at least at 800 ° C. or higher after ion implantation in order to activate a dopant. The threshold value (V _T ) is shifted due to a change in the ion implantation profile. Therefore, the use of the ion implantation method is disadvantageous in terms of ensuring the reliability of the device.

On the other hand, in a method in which a p-PET and an n-FET are formed in a laminated structure and formed separately in a stepped shape using, for example, selective etching, the problem relating to ion implantation is eliminated, but the following problem occurs. is there. First, in the case where AlGaAs is used for the barrier layer, a low-resistance semiconductor layer (for example, p ⁺ -GaAs) doped at a high concentration is usually provided on the barrier layer as a cap layer in order to make contact with the ohmic metal. , AlGaAs / GaAs
When it is manufactured using s-based selective etching, AlGaAs
The layer becomes a surface layer, and it is extremely difficult to form a contact on the AlGaAs layer. The method of leaving p ⁺ -GaAs without using selective etching does not have this problem,
A new problem arises in that the fabrication process is complicated.
In the case of a p-FET, when a metal Schottky gate is used, there is a problem that gate leakage is apt to occur, and it is necessary to take measures such as using AlGaAs having a high Al composition ratio as a barrier layer in order to suppress gate leakage. However, when AlGaAs having a high Al composition ratio is used as a barrier layer, the resistance becomes extremely high, and even if a cap layer is provided, the source resistance becomes high, resulting in deterioration of device characteristics.

SUMMARY OF THE INVENTION An object of the present invention is to provide a high-performance semiconductor device which solves the above-described problems, is easy to manufacture, and can operate at high speed with low power consumption.

[0012]

Means for Solving the Problems The present inventor has made various studies in order to achieve the above object, and as a result, completed the present invention.

A first aspect of the present invention is a complementary semiconductor device using a III-V compound semiconductor in which an n-type channel field effect transistor and a p-type channel field effect transistor are formed on the same substrate. And a semiconductor layer for an n-type channel are laminated, and the surfaces of both of these semiconductor layers are exposed in a step-like manner, and a source, a drain and a gate electrode are provided respectively. And a source / drain region of a field-effect transistor located below and having a structure formed of a low-resistance semiconductor layer doped with impurities at a high concentration.

According to a second aspect of the present invention, a p-type channel field effect transistor is provided below a stepped stacked structure, and is formed of at least two types of semiconductor layers having different electron affinities, and a semiconductor layer having a large electron affinity. The present invention relates to a complementary semiconductor device according to the first invention, which has a structure in which a semiconductor layer to which a p-type impurity is added and a small electron affinity is provided as a barrier layer is provided immediately below a gate as a channel layer.

According to a third aspect of the invention, a p-type channel field effect transistor is provided below a stepped stacked structure, and is formed of at least two types of semiconductor layers having different electron affinities, and a semiconductor layer having a large electron affinity. The present invention relates to a complementary semiconductor device according to the first invention, which has a structure in which a non-doped channel layer is used, and a semiconductor layer having a small electron affinity has a barrier layer formed by adding a p-type impurity to generate a two-dimensional hole gas.

According to a fourth aspect of the present invention, an n-type channel field effect transistor is provided below a stepped stacked structure, and is formed of at least two types of semiconductor layers having different electron affinities, and a semiconductor layer having a large electron affinity. The present invention relates to a complementary semiconductor device according to the first invention, which has a structure in which an n-type impurity is added as a channel layer and a semiconductor layer having a small electron affinity is provided immediately below a gate as a barrier layer.

According to a fifth aspect of the present invention, an n-type channel field effect transistor is provided below a stepped stacked structure, and is formed of at least two types of semiconductor layers having different electron affinities, and a semiconductor layer having a large electron affinity. The present invention relates to a complementary semiconductor device according to the first invention, which has a structure in which a non-doped channel layer is used and a semiconductor layer having a small electron affinity has an n-type impurity added as a barrier layer to generate a two-dimensional electron gas.

According to a sixth aspect of the present invention, a first i-GaAs layer as a buffer layer and a p-GaAs layer or p-InGaAs as a p-type channel layer are formed on a semi-insulating GaAs substrate.
Layer, barrier layer, i-AlGaAs layer or i-In
A GaP layer, a second i-GaAs layer as a separation layer, an n-GaAs layer or n-InGaAs as an n-type channel layer
Sequentially growing layers, removing the n-type channel layer and the second i-GaAs layer by selective etching while leaving a region where an n-type element is to be formed, and exposing the surface of the barrier layer; A complementary semiconductor device comprising: a step of forming ap ⁺ -GaAs layer in a region where a source and a drain of a p-type element are to be formed by selective growth; and a step of forming a gate electrode and an ohmic electrode in each element. It relates to a manufacturing method.

According to a seventh aspect of the present invention, an i-type p-type channel layer is provided.
The present invention relates to a method for manufacturing a complementary semiconductor device according to a sixth aspect of the present invention, comprising a step of growing a GaAs layer or an i-InGaAs layer and a p-AlGaAs layer or a p-InGaP layer as a barrier layer.

The eighth invention is characterized in that it has a step of growing a semiconductor layer having a smaller electron affinity than the channel layer and a semiconductor layer doped with a high concentration of n-type impurities on the n-type channel layer. The present invention relates to a method for manufacturing a complementary semiconductor device according to a sixth aspect of the present invention.

According to a ninth invention, a first i-GaAs layer as a buffer layer and an n-GaAs layer or n-InGaAs as an n-type channel layer are formed on a semi-insulating GaAs substrate.
Layer, barrier layer, i-AlGaAs layer or i-In
A GaP layer, a second i-GaAs layer as a separation layer, a p-GaAs layer or p-InGaAs as a p-type channel layer
Sequentially growing layers, removing the p-type channel layer and the second i-GaAs layer by selective etching while leaving a region where a p-type element is to be formed, and exposing the surface of the barrier layer; A complementary semiconductor device comprising: a step of forming an n ⁺ -GaAs layer by selective growth in a region where a source and a drain of an n-type element are to be formed; and a step of forming a gate electrode and an ohmic electrode in each element. It relates to a manufacturing method.

According to a tenth aspect of the present invention, the n-type channel
The present invention relates to a method for manufacturing a complementary semiconductor device according to a ninth aspect of the present invention, which includes a step of growing an n-AlGaAs layer or an n-InGaP layer as a -GaAs layer or an i-InGaAs layer and a barrier layer.

An eleventh invention is directed to a ninth invention having a step of growing a semiconductor layer having a smaller electron affinity than the channel layer and a semiconductor layer doped with a high concentration of p-type impurities on the p-type channel layer. And a method of manufacturing a complementary semiconductor device.

According to a twelfth invention, a first i-InGaAs or i-InAlAs layer as a buffer layer and a p-InG layer as a p-type channel layer are formed on a semi-insulating InP substrate.
aAs layer, i-InAlAs layer as barrier layer or i
An InP layer, a second i-InGaAs layer as a separation layer,
a step of sequentially growing an n-InGaAs layer as an n-type channel layer;
removing the nGaAs layer and the second i-InGaAs layer by selective etching to expose the surface of the barrier layer; and forming p ⁺ − − in the regions where the source and drain of the p-type element are to be formed.
The present invention relates to a method for manufacturing a complementary semiconductor device, comprising a step of forming an InGaAs layer by selective growth and a step of forming a gate electrode and an ohmic electrode for each element.

According to a thirteenth aspect, the p-type channel layer is made of i
The present invention relates to a method for manufacturing a complementary semiconductor device according to a twelfth aspect, comprising a step of growing a p-InAlAs layer or a p-InP layer as an InGaAs layer and a barrier layer.

According to a fourteenth aspect, a twelfth aspect includes a step of growing a semiconductor layer having a smaller electron affinity than the channel layer and a semiconductor layer doped with a high concentration of n-type impurities on the n-type channel layer. And a method of manufacturing a complementary semiconductor device.

According to a fifteenth aspect, a first i-InGaAs layer or i-InAlAs layer as a buffer layer and an n-InG layer as an n-type channel layer are formed on a semi-insulating InP substrate.
aAs layer, i-InAlAs layer as barrier layer or i
An InP layer, a second i-InGaAs layer as a separation layer,
a step of sequentially growing a p-InGaAs layer as a p-type channel layer;
removing the nGaAs layer and the second i-InGaAs layer by selective etching to expose the surface of the barrier layer; and forming n ⁺ -in the source and drain formation regions of the n-type element.
The present invention relates to a method for manufacturing a complementary semiconductor device, comprising a step of forming an InGaAs layer by selective growth and a step of forming a gate electrode and an ohmic electrode for each element.

According to a sixteenth aspect of the present invention, the n-type channel
The present invention relates to a method for manufacturing a complementary semiconductor device according to a fifteenth aspect, comprising a step of growing an n-InAlAs layer or an n-InP layer as an InGaAs layer and a barrier layer.

A seventeenth invention is directed to a fifteenth invention having a step of growing, on a p-type channel layer, a semiconductor layer having a smaller electron affinity than the channel layer and a semiconductor layer doped with a p-type impurity at a high concentration. And a method of manufacturing a complementary semiconductor device.

[0030]

DETAILED DESCRIPTION OF THE INVENTION In the present invention, an n-FET and a p-F
The ET is manufactured as a laminated structure on the same substrate, and the transistors located below are manufactured using a combination of materials such as an AlGaAs / GaAs system, which is easy to selectively etch, and are selectively manufactured by selectively etching these. Can be. In addition, by forming the source and drain regions with a low-resistance semiconductor layer by selective growth, it becomes easy to form an ohmic contact, and the source resistance can be reduced.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1) FIG. 1 is a sectional view showing the configuration of an embodiment of a complementary semiconductor device according to the present invention. In FIG. 1, 10 is a semi-insulating GaAs substrate, and 11 is i-Ga
An As buffer layer, 12 is a non-doped i-In _0.2 Ga _0.8 As channel layer serving as a p-FET channel layer, and 13 is p-Al _0.8 Ga doped with a p-type impurity such as Be or C at 2 × 10 ¹⁸ cm ^−3. _0.2 As barrier layer. This barrier layer also serves as a hole supply layer for generating a two-dimensional hole gas. Further, reference numeral 14 denotes a second i-GaAs buffer layer;
Is a non-doped i-In to be an n-PET channel layer
_0.2 Ga _0.8 As channel layer, 16 is 2 × 10 ¹⁸ c of Si
An n-Al _0.3 Ga _0.7 As electron supply layer doped with m ⁻³ , and 17 is an n ⁺ -GaAs cap layer. 30 is p
-A p ⁺ -GaAs contact layer selectively formed in the source and drain regions of the FET. 40 and 41 are WS
A gate electrode made of i, 50 is an ohmic electrode (AuGeNi) of an n-FET, and 51 is an ohmic electrode (AuZn) of a P-FET.

In addition to the present embodiment, as shown in FIG.
ET is formed of n-GaAs18, and MESFET (Me
tal Semiconductor FET) type, or Figure 3
The p-FET may be formed of a p-In _0.2 Ga _0.8 As layer channel layer 19 and an i-Al _0.8 Ga _0.2 As barrier layer 20 as shown in FIG. Similarly, the n-FET is replaced with n-In _0.2 G
It may be formed of an a _0.8 As channel layer 28 and an i-Al _0.3 Ga _0.7 As barrier layer 29. The channel layer is Ga
As may be used, and the barrier layer may be InGaP. In addition, the composition of all the materials is arbitrary as long as the object of the present invention can be achieved.

Next, an example of a method for manufacturing the complementary semiconductor device shown in FIG. 1 will be described. 4 and 5 show the manufacturing process.

First, as shown in FIG. 4A, a 500 nm-thick i-GaAs buffer layer 11 and a p-FET are formed on a semi-insulating GaAs substrate 10 using a molecular beam epitaxy apparatus (MBE). A non-doped i-In _0.2 Ga _0.8 As channel layer 12 having a thickness of 15 nm serving as a channel layer, and a 25 nm thick p-layer doped with Be at 2 × 10 ¹⁸ cm ^−3.
-Al _0.8 Ga _0.2 As barrier layer 13, 100 nm-thick second i-GaAs buffer layer 14, 15 nm-thick non-doped i-In _0.2 G serving as a channel layer of an n-FET
a _0.8 As channel layer 15; n-Al _0.3 Ga _0.7 As electron supply layer 16 with a thickness of 30 nm doped with 2 × 10 ¹⁸ cm ^{−3 of} Si; n with a thickness of 60 nm doped with 5 × 10 ¹⁸ cm ^{−3 of} Si ^{A +} -GaAs cap layer 17 is sequentially grown.

Next, as shown in FIG.
The portion is covered with a mask PR, and etching is performed to the i-In _0.2 Ga _0.8 As channel layer 15 by phosphoric acid-based wet etching. In this case, it is not necessary to stop the etching just at the i-In _0.2 Ga _0.8 As channel layer, and it may be applied to the second i-GaAs buffer layer 14.

Subsequently, as shown in FIG.
Using an etching apparatus, p-Al _0.8Ga_0.2As Bali
The etching is performed until the layer 13 is reached. At this time, etch
CCl_TwoF_TwoOr SF₆And BCl_ThreeBlend of
Selection of AlGaAs and GaAs by using combined gas
Selective etching, and etching is automatically performed with the AlGaAs layer.
Stop dynamically. In addition, selective etching of this system requires
There is a method using enic acid or the like.

In the same manner, the cap layer 1 of the n-FET
7 is etched to open a gate portion (FIG. 4).
(D)).

Next, as shown in FIG. 5E, gate electrodes 40 and 41 are formed of WSi, and a SiO ₂ film (mask) is formed.
Then, the source and drain regions of the p-FET are etched by phosphoric acid-based wet etching until they reach the channel layer 12.

Next, as shown in FIG. 5 (f), the source and drain regions are doped with Zn or C as a dopant by using metalorganic vapor phase epitaxy (MOVPE) or metalorganic molecular beam epitaxy (MOMBE). p ⁺ -Ga
An As contact layer 30 (thickness: 100 nm, dopant concentration: 5 × 10 ¹⁹ cm ⁻³ ) is selectively grown. At this time, there is no problem in contact formation even if the source and drain regions are not etched and only selective growth is performed as a cap layer.
The source resistance is slightly higher.

Finally, as shown in FIG.
eNi and AuZn are deposited to form ohmic electrodes 50 and 51, respectively, to complete the device.

Further, as shown in FIG. 6, when the source and drain regions of the n-FET are formed of, for example, an n ⁺ -GaAs contact layer (selective growth layer) 31, the n-FET
Can also be reduced.

In the structure shown in FIG.
When the device characteristics were evaluated as 5 μm, n-FE
Gm at T = 250 mS / mm, f _T = 50 GHz, f _max
= 60 GHz, gm = 80 mS / mm with p-FET, f
_T = 10 GHz, _fmax = 20 GHz, and good results were obtained.

The growth method, etching method, conditions, composition, materials, and the like described in the present manufacturing method are arbitrary and can be applied as long as the object of the present invention is achieved.

(Embodiment 2) FIG. 7 is a sectional view showing the configuration of an embodiment of the complementary semiconductor device of the present invention. 7, 10 is a semi-insulating GaAs substrate, 21 is i-Ga
An As buffer layer, 22 is a non-doped i-In _0.2 Ga _0.8 As channel layer serving as a channel layer of an n-FET, and 23 is an n-type doped with an n-type impurity such as Si at 2 × 10 ¹⁸ cm ^−3.
Al _0.3 Ga is _{0 .7} As electron supply layer. Further, 24 is a second i-GaAs buffer layer, 25 is a non-doped i-In _0.2 Ga _0.8 As channel layer serving as a channel layer of a p-FET, and 26 is a p-type impurity such as Be or C of 2 × 10 ¹⁸ cm.
^{A -3} doped p-Al _0.8 Ga _0.2 As hole supply layer, and 27 is a p ⁺ -GaAs cap layer. 31 is n
-N ⁺ -GaAs contact layer selectively formed in the source and drain regions of the FET. 40 and 41 are W
A gate electrode made of Si, 50 is an ohmic electrode (AuGeNi) of an n-FET, and 51 is an ohmic electrode (AuZn) of a p-FET.

In addition to the present embodiment, as shown in FIG.
-FET is connected to an n-In _0.2 Ga _0.8 As channel layer 28, i
-Al _0.3 Ga _0.7 As barrier layer 29 may be used.

Further, as shown in FIG.
-In_0.2Ga_0.8As layer channel layer 19, i-Al_0.8
Ga_0.2The As barrier layer 20 may be used. Note that
The channel layer may be GaAs, and the barrier layer may be In.
GaP may be used. And n ⁺-GaAs contact
Layer 31 is n⁺-InGaAs layer may be used. All materials
Is arbitrary within a range that achieves the present invention.
You.

Next, an example of a method for manufacturing the complementary semiconductor device shown in FIG. 7 will be described. The manufacturing process diagram is substantially the same as that of FIGS.

First, semi-insulating GaAs is formed by using the MBE method.
An i-GaAs buffer layer 21 having a thickness of 500 nm and a thickness of 15 nm serving as a channel layer of an n-FET are formed on an s substrate 10.
Non-doped i-In _0.2 Ga _0.8 As layer 22
30 nm thick ^nA doped with i at 2 × 10 ¹⁸ cm ⁻³
l _0.3 Ga _0.7 As electron supply layer 23, a second i-GaAs buffer layer 24 having a thickness of 100 nm, and a non-doped i-In _0.2 Ga having a thickness of 15 nm serving as a channel layer of a p-FET.
_0.8 As layer 25, 25 nm thick p-Al _0.8 Ga _0.2 As hole supply layer 26 doped with Be at 2 × 10 ¹⁸ cm ⁻³ , Be-doped p ⁺ -GaAs cap layer (thickness 60
nm, and a doping concentration of 1 × 10 ¹⁹ cm ⁻³ ) 27 are sequentially grown.

Next, the p-FET portion is covered with a mask and etched by phosphoric acid-based wet etching and selective dry etching until reaching the n-Al _0.3 Ga _0.7 As electron supply layer 23. The reason why the etching is automatically stopped in the AlGaAs layer is the same as in the first embodiment.

In the same manner, the cap layer 2 of the p-FET
7 is etched to open a gate portion.

Further, the gate electrodes 40 and 41 are formed of WSi, and are covered with a SiO ₂ film (mask) 42 to form an n-FET.
Is etched by phosphoric acid-based wet etching until the source and drain regions reach the channel layer 22.
Using the OVPE method or the MOMBE method, n ⁺ -GaAs
s layer 31 (thickness 100 nm, dopant concentration 5 × 10 ¹⁸
cm ⁻³ ) to grow selectively. At this time, if the source and drain regions are not etched and only selective growth is performed as a cap layer, there is no problem in contact formation, but the source resistance is slightly increased.

Finally, AuGeNi and AuZn are deposited to form ohmic electrodes 50 and 51, respectively, to complete the device.

Further, if the source and drain regions of the p-FET are formed of, for example, ap ⁺ -GaAs contact layer, the source resistance of the p-FET can be reduced.

The growth method, etching method, conditions, composition, materials, and the like described in the present manufacturing method are arbitrary and applicable as long as the objects of the present invention are achieved.

(Embodiment 3) FIG. 10 is a sectional view showing the configuration of an embodiment of a complementary semiconductor device according to the present invention. FIG.
At 0, 60 is a semi-insulating InP substrate and 61 is i-I
nAlAs buffer layer, 62 is a non-doped i-In _0.5 Ga _0.5 As layer serving as a p-FET channel layer, 63 is B
p-I doped with 2 × 10 ¹⁸ cm ^{−3 of} a p-type impurity such as e
This is an n _0.5 Al _0.5 As barrier layer. This barrier layer also serves as a hole supply layer for generating a two-dimensional hole gas. Further, 64 is an i-InGaAs buffer layer, and 65 is n-FE
Non-doped i-In _0.5 Ga _0.5 A to be a T channel layer
The s layer 66 is n doped with 2 × 10 ¹⁸ cm ⁻³ of Si.
-In _0.5 Al _0.5 As electron supply layer, 67 is n ⁺ -InG
This is an aAs cap layer. 68 is the source of the p-FET,
P ⁺ -InGaAs selectively formed in the drain region
It is a contact layer. 40 and 41 are gate electrodes made of WSi, and 52 and 53 are ohmic electrodes made of TiPtAu.

In addition to the present embodiment, as shown in FIG.
A structure in which the positions of the n-FET and the p-FET are reversed may be used. The barrier layer may be InP. The composition of all the materials is arbitrary within a range that achieves the object of the present invention.

Next, an example of a method for manufacturing the complementary semiconductor device shown in FIG. 10 will be described. The manufacturing process diagram is substantially the same as that of FIGS.

First, a semi-insulating InP is formed using the MBE method.
Substrate 60 On the substrate, i-InAlAs buffer layer 61,
Non-doped i-In to be the channel layer of p-FET_0.5
Ga_{0 .Five}The p-type impurity such as the As layer 62 and Be is¹⁸
cm^-3Doped p-In_0.5Al_0.5As hole supply layer
63, i-InGaAs buffer layer 64, n-FET
Non-doped i-In serving as a channel layer_0.5Ga_0.5As layer
65, 2 × 10 Si ¹⁸cm^-3Doped n-In
_0.5Al_0.5As electron supply layer 66, n⁺-InGaAs key
A cap layer 67 is sequentially grown.

Next, the n-FET portion is covered with a mask, and p-In
Etching is performed until reaching the _0.5 Al _0.5 As hole supply layer 63. At this time, citric acid or succinic acid which can be selectively etched with InGaAs and InAlAs can be used.

In the same manner, the cap layer 6 of the n-FET
7 is etched to open a gate portion.

Next, gate electrodes 40 and 41 are formed of WSi, covered with a SiO ₂ film (mask) 42, and the source and drain regions of the p-FET are etched by wet etching until reaching the channel layer 62.

Next, a p ⁺ -InGaAs contact layer 68 (having a thickness of 100 mm) was formed in the source and drain regions by using MOVPE or MOMBE with Zn as a dopant.
and a dopant concentration of 5 × 10 ¹⁹ cm ⁻³ ). At this time, the source and drain regions are not etched,
Although there is no problem in forming a contact even if it is selectively grown as a cap layer, the source resistance is slightly increased.

Lastly, ohmic electrodes 52 and 53 are formed by vapor deposition with TiPtAu to complete the device.

Further, if the source and drain regions of the n-FET are formed of, for example, an n ⁺ -InGaAs contact layer, the source resistance of the n-FET can be reduced.

The growth method, etching method, conditions, composition, materials and the like shown in the present manufacturing method are arbitrary and all applicable as long as the object of the present invention can be achieved.

[0067]

As described above, according to the present invention, n
-It is possible to easily manufacture a semiconductor device which has high performance in both FET and p-FET and can operate at high speed with low power consumption without using ion implantation.

[Brief description of the drawings]

FIG. 1 is a structural sectional view of a complementary semiconductor device of the present invention.

FIG. 2 is a structural sectional view of a complementary semiconductor device of the present invention.

FIG. 3 is a structural sectional view of a complementary semiconductor device of the present invention.

FIG. 4 is a process chart showing a method for manufacturing a complementary semiconductor device of the present invention.

FIG. 5 is a process chart showing a method for manufacturing a complementary semiconductor device of the present invention.

FIG. 6 is a structural sectional view of a complementary semiconductor device of the present invention.

FIG. 7 is a structural sectional view of a complementary semiconductor device of the present invention.

FIG. 8 is a structural sectional view of a complementary semiconductor device of the present invention.

FIG. 9 is a structural sectional view of a complementary semiconductor device of the present invention.

FIG. 10 is a structural sectional view of a complementary semiconductor device of the present invention.

FIG. 11 is a structural sectional view of a complementary semiconductor device of the present invention.

FIG. 12 is a structural sectional view of a conventional complementary semiconductor device.

FIG. 13 is a structural sectional view of a conventional complementary semiconductor device.

[Explanation of symbols]

Reference Signs List 10 insulating GaAs substrate 11 i-GaAs buffer layer 12 i-In _0.2 Ga _0.8 As channel layer 13 p-Al _0.8 Ga _0.2 As barrier layer 14 second i-GaAs buffer layer 15 i-In _0.2 Ga _0.8 As channel layer 16 n-Al _0.3 Ga _0.7 As electron supply layer 17 n ⁺ -GaAs cap layer 18 n-GaAs layer 19 p-In _0.2 Ga _0.8 As layer channel layer 20 i-Al _0.8 Ga _0.2 As barrier layer 21 i-GaAs buffer layer 22 i-In _0.2 Ga _0.8 As channel layer 23 n-Al _0.3 Ga _0.7 As electron supply layer 24 second i-GaAs buffer layer 25 i-In _0.2 Ga _0.8 As channel layer 26 p-Al _0.8 Ga _0.2 As hole supply layer 27 p ⁺ -GaAs cap layer 28 n-In _0.2 Ga _0.8 As channel layer 29 i-Al _0.3 Ga _0.7 A Barrier layer 30 p ⁺ -GaAs contact layer 31 n ⁺ -GaAs contact layer 40 and 41 gate one gate electrode (WSi) 42 SiO ₂ film 50 ohmic electrode (AuGeNi) 51 ohmic electrode (AuZn) 52 and 53 ohmic electrode (TiPtAu) Reference Signs List 60 semi-insulating InP substrate 61 i-InAlAs buffer layer 62 i-In _0.5 Ga _0.5 As layer 63 p-In _0.5 Al _0.5 As barrier layer 64 i-InGaAs buffer layer 65 i-In _0.5 Ga _0.5 As layer 66 n-In _0.5 Al _0.5 As electron supply layer 67 n ⁺ -InGaAs cap layer 68 p ⁺ -InGaAs contact layer 69 n ⁺ -InGaAs contact layer 70 p ⁺ -InGaAs cap layer PR mask 121 GaAs substrate 122 i-GaAs layer 123 i-AlGaAs layer 12 The gate electrode 125 P ⁺ ion implantation region 126 N ⁺ ion implantation region 131 GaAs substrate 132,134 i-GaAs 133 p-AlGaAs layer 135 n-AlGaAs layer 136 n ⁺ -GaAs layer 137 ohmic electrode 138 gate electrode

Claims (17)

[Claims] In a complementary semiconductor device using a group III-V compound semiconductor in which an n-type channel field effect transistor and a p-type channel field effect transistor are formed on the same substrate, a semiconductor layer for a p-type channel is formed. It has a structure in which semiconductor layers for an n-type channel are stacked, has a structure in which the surfaces of both of these semiconductor layers are exposed in a step shape, and a source, a drain, and a gate electrode are provided for each,
And a source / drain region of a field effect transistor located below has a structure formed of a low-resistance semiconductor layer to which an impurity is added at a high concentration. 2. A p-channel field effect transistor, comprising:
A semiconductor layer provided at the lower side of the step-like stacked structure and formed of at least two kinds of semiconductor layers having different electron affinities, and a semiconductor layer having a high electron affinity and serving as a channel layer is doped with a p-type impurity and has a small electron affinity. Has a structure provided immediately below a gate as a barrier layer.
The complementary semiconductor device as described in the above. 3. The p-channel field effect transistor according to claim 1,
The semiconductor layer having a lower electron affinity is provided as a non-doped channel layer, and the semiconductor layer having a lower electron affinity is formed of at least two types of semiconductor layers having different electron affinities. 2. The complementary semiconductor device according to claim 1, wherein the barrier layer is formed by adding a compound to the substrate to have a structure for generating a two-dimensional hole gas. 4. An n-type channel field effect transistor,
A semiconductor layer provided below the stepped laminated structure and formed of at least two types of semiconductor layers having different electron affinities, and having a high electron affinity as a channel layer is a semiconductor layer to which an n-type impurity is added and which has a low electron affinity. Has a structure provided immediately below a gate as a barrier layer.
The complementary semiconductor device as described in the above. 5. An n-type channel field effect transistor, comprising:
The semiconductor layer having a lower electron affinity is provided as a non-doped channel layer, and the semiconductor layer having a lower electron affinity is formed of at least two types of semiconductor layers having different electron affinities. 2. The complementary semiconductor device according to claim 1, wherein said semiconductor device has a structure in which a two-dimensional electron gas is generated by adding a barrier layer. 6. A first i-GaAs layer as a buffer layer and a p-type channel layer on a semi-insulating GaAs substrate.
-GaAs layer or p-InGaAs layer, i-AlGaAs layer or i-InGaP layer as a barrier layer, second i-GaAs layer as a separation layer, n as an n-type channel layer
A step of sequentially growing a -GaAs layer or an n-InGaAs layer; and removing the n-type channel layer and the second i-GaAs layer by selective etching while leaving a region where an n-type element is to be formed. A step of exposing a surface, a step of forming ap ⁺ -GaAs layer by selective growth in a region where a source and a drain of a p-type element are to be formed, and a step of forming a gate electrode and an ohmic electrode in each element. Of manufacturing a complementary semiconductor device. 7. An i-GaAs layer or an i-InGaAs layer as a p-type channel layer, and p-AlGa as a barrier layer
7. The method of manufacturing a complementary semiconductor device according to claim 6, further comprising the step of growing an As layer or a p-InGaP layer. 8. The method according to claim 6, further comprising the step of growing, on the n-type channel layer, a semiconductor layer having a smaller electron affinity than the channel layer and a semiconductor layer to which a high concentration of n-type impurities is added. A method for manufacturing the complementary semiconductor device according to the above. 9. A first i-GaAs layer as a buffer layer and n as an n-type channel layer on a semi-insulating GaAs substrate.
A GaAs layer or an n-InGaAs layer, an i-AlGaAs layer or an i-InGaP layer as a barrier layer, a second i-GaAs layer as a separation layer, and p as a p-type channel layer.
-A step of sequentially growing a GaAs layer or a p-InGaAs layer; and removing the p-type channel layer and the second i-GaAs layer by selective etching while leaving a region where a p-type element is to be formed. A step of exposing a surface, a step of forming an n ⁺ -GaAs layer by selective growth in a region where a source and a drain of an n-type element are to be formed, and a step of forming a gate electrode and an ohmic electrode for each element. Of manufacturing a complementary semiconductor device. 10. An i-GaAs layer or an i-InGaAs layer as an n-type channel layer and n-AlG as a barrier layer
The method of manufacturing a complementary semiconductor device according to claim 9, further comprising a step of growing an aAs layer or an n-InGaP layer. 11. The method according to claim 9, further comprising the step of growing, on the p-type channel layer, a semiconductor layer having a smaller electron affinity than the channel layer and a semiconductor layer to which a p-type impurity is added at a high concentration.
A method for manufacturing the complementary semiconductor device according to the above. 12. A first i-InGaAs layer or i-InAlA as a buffer layer on a semi-insulating InP substrate.
An s layer, a p-InGaAs layer as a p-type channel layer, an i-InAlAs layer or i-InP layer as a barrier layer, a second i-InGaAs layer as a separation layer, and an n-InGaAs layer as an n-type channel layer are sequentially grown. A step of removing the n-InGaAs layer and the second i-InGaAs layer by selective etching while leaving a region where an n-type element is to be formed, exposing the surface of the barrier layer; Forming a p ⁺ -InGaAs layer in a region where a drain is to be formed by selective growth, and forming a gate electrode and an ohmic electrode for each element. 13. i-InGaAs as a p-type channel layer
s layer, p-InAlAs layer or p-I as a barrier layer
13. The method of manufacturing a complementary semiconductor device according to claim 12, further comprising a step of growing an nP layer. 14. The method according to claim 1, further comprising the step of growing a semiconductor layer having a smaller electron affinity than the channel layer and a semiconductor layer doped with a high concentration of n-type impurities on the n-type channel layer.
3. The method for manufacturing a complementary semiconductor device according to item 2. 15. A first i-InGaAs layer or i-InAlA as a buffer layer on a semi-insulating InP substrate.
An s layer, an n-InGaAs layer as an n-type channel layer, an i-InAlAs layer or i-InP layer as a barrier layer, a second i-InGaAs layer as a separation layer, and a p-InGaAs layer as a p-type channel layer are sequentially grown. A step of removing the p-InGaAs layer and the second i-InGaAs layer by selective etching while leaving a region where a p-type element is to be formed, exposing the surface of the barrier layer; A method of forming an n ⁺ -InGaAs layer by selective growth in a region where a drain is to be formed, and a step of forming a gate electrode and an ohmic electrode for each element. 16. i-InGaAs as an n-type channel layer
s layer, n-InAlAs layer or nI as a barrier layer
The method for manufacturing a complementary semiconductor device according to claim 15, further comprising a step of growing an nP layer. 17. The method according to claim 1, further comprising the step of growing a semiconductor layer having a lower electron affinity than the channel layer and a semiconductor layer doped with a high concentration of p-type impurities on the p-type channel layer.
6. The method for manufacturing a complementary semiconductor device according to claim 5.