JPH10313075A - Board for chip mounting use and manufacture thereof - Google Patents
Board for chip mounting use and manufacture thereofInfo
- Publication number
- JPH10313075A JPH10313075A JP15728497A JP15728497A JPH10313075A JP H10313075 A JPH10313075 A JP H10313075A JP 15728497 A JP15728497 A JP 15728497A JP 15728497 A JP15728497 A JP 15728497A JP H10313075 A JPH10313075 A JP H10313075A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- hole
- mounting
- substrate material
- laminated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【0001】[0001]
【産業上の利用分野】この発明は、チップ搭載用基板及
びその製造法に関し、更に詳しくは材料の厚みのあるモ
ールド品に対して数100ミクロンの厚みで直接接合出
来、ソケットが不要なチップ搭載用基板及びその製造法
に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip mounting substrate and a method of manufacturing the same, and more particularly, to a chip mounting that can be directly joined to a molded product having a thick material with a thickness of several hundred microns and does not require a socket. The present invention relates to a substrate for use and a method for manufacturing the same.
【0002】[0002]
【従来の技術】従来座ぐり等の機械加工により1個づつ
チップを装着する箇所の凹部を基板に露出形成してい
た。この方法は、数ミクロン単位で、Z軸(縦軸)方向
の調整の外に、X、Y軸方向の調整をも必要とした。2. Description of the Related Art Conventionally, recesses at locations where chips are mounted one by one have been formed on a substrate by machining such as spot facing. This method required adjustment in X and Y axis directions in addition to adjustment in the Z axis (vertical axis) direction in units of several microns.
【0003】[0003]
(1)機械加工は、正確に実施する必要があり、相当の
技術と時間とを必要とした。 (2)又印刷法により所要高さの壁(通称ダム)を形成
する方法も提案されているが、厚みが制限され、該壁に
使用される接着剤が流出するので数10ミクロン以下の
ものしか加工不可能であった。 (3)中間層に必要で確実な回路とボンディング・パッ
ドを形成する事は、数10ミクロンの厚さの回路と、中
間層が数100ミクロンの厚さであるから調整が困難で
あった。(1) Machining must be performed accurately and requires considerable skill and time. (2) A method of forming a wall (commonly called a dam) having a required height by a printing method has also been proposed, but the thickness is limited, and the adhesive used for the wall flows out, so that the wall is several tens of microns or less. Only processing was possible. (3) It is difficult to form a necessary and reliable circuit and bonding pad on the intermediate layer because the circuit has a thickness of several tens of microns and the intermediate layer has a thickness of several hundreds of microns.
【0004】[0004]
【課題を解決しようとする手段】この発明の一方の要旨
は、前述のチップ搭載用基板及びその製造法に於て、夫
々所要広さと厚みとを有する銅箔、絶縁層及び積層材と
から成る第1基板材の所要箇所に、所要大きさの部品搭
載用貫通孔を形成する工程、夫々所要広さと厚みとを有
する銅箔、絶縁層及び銅箔とから成る第2基板材で、該
第1基板材の該部品封止及び搭載用貫通孔の対応箇所
に、所要大きさの部品搭載用貫通孔を形成する工程と、
該第2基板材の該銅箔に、パターン形成後エッチングを
施して露出回路と端子とを形成し、チップ取付用パッド
を設ける工程と、該第1基板材の積層面にノン・フロー
・タイプの接着剤を施す工程と、該第2基板材の該回路
に金属メッキ・レジストを施す工程と、該第1基板材と
該第2基板材とを、高温、高圧で所要時間加圧、積層し
て積層基板とする工程と、該積層基板の周囲にスルー・
ホールを形成し、該スルー・ホールと該部品封止及び搭
載用貫通孔とに、スルー・ホール・メッキ層を施して回
路を形成し、エッチング加工する工程とから成るチップ
搭載用基板の製造法である。According to one aspect of the present invention, there is provided a chip mounting board and a method of manufacturing the same, comprising a copper foil, an insulating layer, and a laminated material each having a required width and thickness. Forming a through hole for mounting a component of a required size in a required portion of the first substrate material; a second substrate material comprising a copper foil, an insulating layer, and a copper foil each having a required width and thickness; Forming a component mounting through hole of a required size at a position corresponding to the component sealing and mounting through hole of one substrate material;
A step of forming an exposed circuit and a terminal on the copper foil of the second substrate material after pattern formation to form an exposed circuit and a terminal, and providing a chip mounting pad; and a step of forming a non-flow type on the laminated surface of the first substrate material. Applying an adhesive, applying a metal plating resist to the circuit of the second substrate material, and pressing and laminating the first substrate material and the second substrate material at a high temperature and a high pressure for a required time. And forming a through board around the laminated board.
Forming a hole, forming a circuit by applying a plated-through-hole layer to the through-hole and the through-hole for sealing and mounting the component, and performing an etching process. It is.
【0005】この発明の他方の要旨は、所要大きさの部
品封止及び搭載用貫通孔を形成した夫々所要広さと厚み
とを有する銅箔、絶縁層及び積層材とを有する第1基板
材と、該部品封止及び搭載用貫通孔に対応する箇所に所
要大きさの部品封止及び搭載用貫通孔を形成し、所要広
さとエッチングを施して露出回路と端子とを形成し、チ
ップ取付用パッドを設け、該第1基板材の積層面にノン
・フロー・タイプの接着剤を施し、該回路にメッキによ
り金属メッキ・レジストを施した第2基板材と合わせ、
高温、高圧で所要時間加圧した積層基板と、該積層基板
の周囲と該部品封止及び搭載用貫通孔とにエッチングを
施してパターンを形成後、該積層基板の周囲に形成した
後エッチングを施して露出回路と端子とを形成し、チッ
プ取付用パッドを設け、該第1基板材の積層面にノン・
フロー・タイプの接着剤を施し、該回路に金属メッキ・
レジストを施した第2基板材と合わせ、高温、高圧で所
要時間加圧した積層基板と、該積層基板に孔加工してス
ルー・ホール・メッキを施し、該封止及び部品搭載用貫
通孔とにエッチングを施してパターンを形成を施した露
出回路に各種メッキを施して成るチップ搭載用基板であ
る。[0005] The other gist of the present invention is to provide a first substrate material having a required size and thickness for forming a through hole for encapsulating and mounting components, a copper foil having a required width and thickness, an insulating layer and a laminated material, respectively. Forming a through hole for sealing and mounting of a required size at a position corresponding to the through hole for sealing and mounting the component, performing a required width and etching to form an exposed circuit and a terminal, and mounting the chip; A pad is provided, a non-flow type adhesive is applied to the lamination surface of the first substrate material, and the circuit is combined with a second substrate material obtained by applying a metal plating resist by plating,
After forming a pattern by forming a pattern on the periphery of the laminated substrate and the through hole for component sealing and mounting by pressing the laminated substrate for a required time at a high temperature and a high pressure, and forming the pattern around the laminated substrate, etching is performed. To form an exposed circuit and terminals, provide chip mounting pads, and attach a non-
Apply a flow type adhesive and apply metal plating to the circuit.
A laminated substrate pressed with high temperature and high pressure for a required time together with the second substrate material subjected to the resist, and a hole is formed in the laminated substrate, through-hole plating is performed, and the sealing and through holes for mounting components are formed. This is a chip mounting substrate obtained by applying various platings to an exposed circuit in which a pattern is formed by etching a substrate.
【0006】[0006]
【実施例】請求項1、3記載のチップ搭載用基板の製造
法を添付図面に示す実施例について説明する。請求項1
記載のチップ搭載用基板の製造法の実施例を示す図1に
於て、夫々所要広さと厚みとを有する第1基板材10
は、銅箔12、ガラス繊維エポキシ樹脂製絶縁層14及
び半硬化性樹脂製ボンディング・シート16とから成
り、該第1基板材10の所要箇所に孔加工により所要大
きさの貫通孔12a、14a及び16aとを穿設する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for manufacturing a chip mounting board according to the first and third aspects will be described with reference to the accompanying drawings. Claim 1
In FIG. 1 showing an embodiment of the method for manufacturing a chip mounting substrate described above, first substrate members 10 each having a required width and thickness are shown.
Comprises a copper foil 12, an insulating layer 14 made of glass fiber epoxy resin, and a bonding sheet 16 made of a semi-curable resin, and through holes 12a, 14a of a required size are formed in required portions of the first substrate material 10 by drilling. And 16a.
【0007】図2於て、第2基板材20は、夫々所要広
さと厚みとを有する銅箔22、絶縁層24及び銅箔26
とから成り、該第2基板材20で、該第1基板材10の
該部品搭載用貫通孔12a、14a及び16aの対応箇
所に、孔加工により所要大きさの部品搭載用貫通孔22
a、24a及び26aとを夫々穿設して形成する。In FIG. 2, a second substrate material 20 comprises a copper foil 22, an insulating layer 24, and a copper foil 26 each having a required width and thickness.
In the second substrate 20, component mounting through holes 22 of a required size are formed in the corresponding positions of the component mounting through holes 12 a, 14 a and 16 a of the first substrate 10 by drilling.
a, 24a and 26a are respectively formed by drilling.
【0008】図2〜3於て、該第2基板材20の上面の
該銅箔22に、感光剤をラミーネートし、露光、現像し
て所要パターンを形成後、エッチングを施して露出回路
22bを形成する。Referring to FIGS. 2 and 3, a photosensitive agent is laminated on the copper foil 22 on the upper surface of the second substrate member 20, exposed and developed to form a required pattern, and then etched to form an exposed circuit 22b. Form.
【0009】次に該露出回路22bに、チップ取付用ワ
イヤ・ボンディング端子28を形成する。Next, chip bonding wire bonding terminals 28 are formed on the exposed circuit 22b.
【0010】図1〜3於て、該第2基板材20の該第1
基板材10との接合面にある該露出回路22bに金属メ
ッキ・レジストを施す。Referring to FIGS. 1-3, the first substrate material 20 has a first
A metal plating resist is applied to the exposed circuit 22b on the joint surface with the substrate material 10.
【0011】該第1基板材10と該第2基板材20と
を、高温100〜200℃、高圧5〜70kg/cm2
で所要時間加圧し、一体に積層して積層基板40とす
る。The first substrate material 10 and the second substrate material 20 are heated at a high temperature of 100 to 200 ° C. and a high pressure of 5 to 70 kg / cm 2.
, And pressurized for a required time to form a laminated substrate 40.
【0012】図5、6於て、該積層基板40の周囲に一
定間隔で直径0.1φ以上のスルー・ホール42を形成
し、該スルー・ホール42内にスルー・ホール・メッキ
を施した後、エッチング加工して回路を形成し、スルー
・ホールをダイシングし、又は水に研磨材を混合して高
圧で切断し、他の方法或いは金型加工により回路44を
形成する。In FIGS. 5 and 6, through holes 42 having a diameter of 0.1.phi. Or more are formed at regular intervals around the laminated substrate 40, and through holes 42 are plated in the through holes 42. Then, a circuit is formed by etching, a through hole is diced, or an abrasive is mixed with water and cut at a high pressure, and the circuit 44 is formed by another method or die processing.
【0013】該積層基板40の部品封止及び搭載用貫通
孔内(チップ取付用端子28)に、ICチップ34を設
け、金属板又は樹脂板等46を接着又は積層して一体と
する。An IC chip 34 is provided in the through hole for component sealing and mounting (chip mounting terminal 28) of the laminated substrate 40, and a metal plate or a resin plate 46 or the like is bonded or laminated to be integrated.
【0014】請求項2記載の発明の実施例の製造法に於
いては、請求項1記載の発明の実施例と相違し、該第2
基板材20は、該第1基板材10の該貫通孔12a、1
4a及び16aに対応する部品搭載用貫通孔を穿設しな
いものとする。The manufacturing method of the embodiment of the second aspect of the present invention differs from the embodiment of the first aspect of the present invention in that
The substrate material 20 is formed in the through holes 12a, 1
It is assumed that no component mounting through holes corresponding to 4a and 16a are formed.
【0015】請求項4記載の発明の実施例に於ては、該
積層基板40の裏側に放熱用金属製基板を設けないこと
を特徴とするものである。In an embodiment of the present invention, a metal substrate for heat radiation is not provided on the back side of the laminated substrate 40.
【0016】請求項6記載の発明の実施例に於ては、金
属メッキ・レジストの代わりに合成樹脂を封止(充填)
したものである。In an embodiment of the present invention, the synthetic resin is sealed (filled) instead of the metal plating resist.
It was done.
【0017】請求項7記載の発明の実施例に於ては、銅
箔、絶縁層及び積層材とから成る第1基板材10に於
て、銅箔12、ガラス繊維エポキシ樹脂製絶縁層14及
び半硬化性樹脂製ボンディング・シート16とするもの
である。According to an embodiment of the present invention, in a first substrate material 10 comprising a copper foil, an insulating layer and a laminated material, a copper foil 12, a glass fiber epoxy resin insulating layer 14, The bonding sheet 16 is made of a semi-curable resin.
【0018】請求項8記載の発明の実施例に於ては、絶
縁層14をガラス繊維エポキシ樹脂とし、且つ積層材2
4上の回路22bに、金属メッキを施して金属レジスト
とするものである。In an embodiment of the present invention, the insulating layer 14 is made of glass fiber epoxy resin and
The circuit 22b on No. 4 is subjected to metal plating to form a metal resist.
【0019】前述の通り、請求項10記載の発明の実施
例のチップ搭載用基板は、該第2基板材20の積層面
に、ノン・フロー・タイプの接着剤を施して該第1基板
材10を合わせ、高温、高圧で一体に積層して積層基板
40としたものである。As described above, in the chip mounting board according to the embodiment of the present invention, the non-flow type adhesive is applied to the lamination surface of the second board member 20 so that the first board member is provided. 10 are laminated together at a high temperature and a high pressure to form a laminated substrate 40.
【0020】[0020]
【発明の効果】前述の通り、この発明に係るチップ搭載
用基板の製造法によれば、 (1)従来の座ぐり加工による1個づつの機械加工に比
較して、この発明に係る製造法は、封止及び部品搭載用
貫通孔の孔加工を除きパターン形成とエッチングによる
ものであるから、工程が著しく短縮可能となる。As described above, according to the method for manufacturing a chip mounting board according to the present invention, (1) the manufacturing method according to the present invention can be compared with the conventional one-by-one machining by spot facing. Is based on pattern formation and etching except for hole processing of the through hole for sealing and component mounting, so that the process can be significantly shortened.
【0021】(2)公知の方法では、印刷法により所要
高さの壁(通称ダム)を形成する方法であったので、厚
みが制限され、該壁に使用される接着剤が流出するから
数〜10ミクロン以下のものしか加工不安定であった。
しかし、該第1基板材10の積層面に、ノン・フロー・
タイプの接着剤を施すので、この欠陥を完全に除去する
事が可能となる。(2) In a known method, a wall (commonly called a dam) having a required height is formed by a printing method, so that the thickness is limited and an adhesive used for the wall flows out. Only those having a size of 10 μm or less were unstable.
However, the non-flow flow
By applying a type of adhesive, this defect can be completely removed.
【図1】この発明に係るチップ搭載用基板の製造法の実
施例に於て、部品封止及び搭載孔を形成した第1基板材
の部分拡大縦断斜視図である。FIG. 1 is a partially enlarged longitudinal perspective view of a first substrate material in which a component sealing and a mounting hole are formed in an embodiment of a method of manufacturing a chip mounting substrate according to the present invention.
【図2】図1と同様に部品封止及び搭載孔を形成した第
2基板材の部分拡大縦断斜視図である。FIG. 2 is a partially enlarged longitudinal perspective view of a second substrate material in which component sealing and mounting holes are formed as in FIG.
【図3】図2に示す第2基板材の両面の銅箔に、パター
ン形成とエッチングとにより回路を形成した部分拡大縦
断面側面略図である。FIG. 3 is a partially enlarged longitudinal sectional side view schematically showing a circuit formed by pattern formation and etching on copper foil on both surfaces of a second substrate material shown in FIG. 2;
【図4】図3の実施例を別の部分で切断したものを示す
部分拡大縦断斜視図である。FIG. 4 is a partially enlarged longitudinal perspective view showing the embodiment of FIG. 3 cut at another portion.
【図5】この発明に係るチップ搭載用基板の製造法によ
り製造したチップ搭載用基板の正面図である。FIG. 5 is a front view of the chip mounting substrate manufactured by the method of manufacturing a chip mounting substrate according to the present invention.
【図6】図5のVI−VI線切断拡大略斜視図である。FIG. 6 is an enlarged schematic perspective view cut along the line VI-VI of FIG. 5;
【図7】図6の側面図である。FIG. 7 is a side view of FIG. 6;
【図8】積層基板に形成されたスルー・ホールを示す部
分側面略図である。FIG. 8 is a partial side schematic view showing through holes formed in a laminated substrate.
10・・・第1基板材; 12・・・銅箔; 12a・・・貫通孔; 14・・・絶縁層; 16・・・積層材; 16a・・・封止用貫通孔; 20・・・第2基板材; 22a・・・部品封止及び搭載用貫通孔; 22b・・・回路; 24・・・絶縁層; 24a・・・部品搭載用貫通孔; 26・・・銅箔; 26a・・・部品封止及び搭載用貫通孔; 26b・・・露出回路形成用銅箔; 22b・・・回路; 28・・・チップ取付用端子; 30・・・ICチップ搭載箇所; 40・・・積層基板; 42・・・スルー・ホール; 44・・・回路; 46・・・放熱用金属製基板又は多目的合成樹脂板。 Reference numeral 10: first substrate material; 12: copper foil; 12a: through hole; 14: insulating layer; 16: laminated material; 16a: sealing through hole; · 2nd substrate material; 22a · · · through-hole for component sealing and mounting · 22 b · · · circuit; 24 · · · insulating layer; 24 a · · · through-hole for mounting components; ··· Through-holes for component sealing and mounting; 26b ··· Copper foil for forming an exposed circuit; 22b ··· circuit; 28 ··· terminal for chip mounting; · Laminated substrate; 42 · Through hole; 44 · Circuit; 46 · Metal substrate for heat dissipation or multipurpose synthetic resin plate.
Claims (8)
層及び積層材とから成る第1基板材の所要箇所に、所要
大きさの部品封止及び搭載用貫通孔を形成する工程と;
夫々所要広さと厚みとを有する銅箔、絶縁層及び銅箔と
から成る第2基板材で、該第1基板材の該部品封止及び
搭載用貫通孔の対応箇所に、所要大きさの部品封止及び
搭載用貫通孔を形成する工程と;該第2基板材の該銅箔
に、パターン形成後エッチングを施して露出回路と端子
とを形成し、チップ取付用パッドを設ける工程と;該第
1基板材の積層面に、ノン・フロー・タイプの接着剤を
施す工程と;該第2基板材の該回路に、金属メッキ・レ
ジストを施す工程と;該第1基板材と該第2基板材と
を、高温、高圧で所要時間加圧、積層して積層基板とす
る工程と;該積層基板の周囲に、スルー・ホールと、該
部品封止及び搭載用貫通孔とに、スルー・ホール・メッ
キを施して回路を形成し、エッチング加工する工程と;
から成るチップ搭載用基板の製造法。Forming a through hole for sealing and mounting a required size of a component in a required portion of a first substrate material comprising a copper foil, an insulating layer, and a laminated material having a required width and thickness, respectively; ;
A second board member made of a copper foil, an insulating layer, and a copper foil each having a required width and thickness, and a component of a required size is provided at a position corresponding to the component sealing and mounting through hole of the first board material. Forming a through hole for sealing and mounting; and performing etching after forming a pattern on the copper foil of the second substrate material to form an exposed circuit and a terminal, and providing a chip mounting pad; Applying a non-flow type adhesive to the laminated surface of the first substrate material; applying a metal plating resist to the circuit of the second substrate material; and applying the first substrate material and the second Pressurizing and laminating a substrate material at a high temperature and a high pressure for a required time to form a laminated substrate; and forming a through-hole around the laminated substrate and a through-hole for sealing and mounting the component. Forming a circuit by hole plating and etching;
A method for manufacturing a chip mounting substrate comprising:
層及び積層材とから成る第1基板材の所要箇所に、所要
大きさの部品封止及び搭載用貫通孔を形成する工程と;
該第2基板材の該銅箔に、所要箇所に、所要大きさの部
品封止及び搭載用貫通孔を形成し、パターン形成後エッ
チングを施して露出回路と端子とを形成し、チップ取付
用パッドを設ける工程と;該第1基板材の積層面に、ノ
ン・フロー・タイプの接着剤を施す工程と;該第2基板
材の該回路に、金属メッキ・レジストを施す工程と;該
第1基板材と該第2基板材とを、高温、高圧で所要時間
加圧、積層して積層基板とする工程と;該第1基板材と
該第2基板材とに同じく所要枚数の基板材とを積層する
工程と;該積層基板の周囲に、スルー・ホールと、該部
品封止及び搭載用貫通孔に、スルー・ホール・メッキを
施して回路を形成し、エッチング加工する工程と;から
成る請求項1記載のチップ搭載用基板の製造法。2. A step of forming through holes for sealing and mounting parts of a required size at required positions of a first substrate material comprising a copper foil, an insulating layer and a laminated material each having a required width and thickness. ;
In the copper foil of the second substrate material, through holes for sealing and mounting parts of a required size are formed at required places, and after pattern formation, etching is performed to form exposed circuits and terminals, and chip mounting is performed. Providing a pad; applying a non-flow type adhesive to the lamination surface of the first substrate material; applying a metal plating resist to the circuit of the second substrate material; Pressing and laminating one substrate material and the second substrate material at a high temperature and a high pressure for a required time to form a laminated substrate; a required number of the same substrate materials as the first substrate material and the second substrate material And a step of forming a circuit by plating a through hole around the laminated substrate and a through hole for sealing and mounting the component to form a circuit, and performing an etching process. The method for manufacturing a chip mounting substrate according to claim 1.
イシド、変性エポキシ樹脂、ガラス繊維樹脂製絶縁層及
び半硬化性樹脂ボンディング・シートとを有する第1基
板材の所要箇所に、所要大きさの部品封止及び搭載用貫
通孔を形成する工程と;夫々所要広さと厚みとを有する
銅箔、ガラス繊維エポキシ樹脂製絶縁層及び銅箔とから
成る第2基板材で、該第1基板材の該部品封止及び搭載
用貫通孔の対応箇所に、所要大きさの部品封止及び搭載
用貫通孔を形成する工程と;該第2基板材の該銅箔に、
パターン形成後エッチングを施して露出回路と端子とを
形成し、チップ取付用パッドを設ける工程と;該第1基
板材の積層面にノン・フロー・タイプの接着剤を施す工
程と;該第2基板材の該回路に金属メッキ・レジストを
施す工程と;該第1基板材と該第2基板材とを、高温、
高圧で所要時間加圧、積層して積層基板とする工程と;
該積層基板の周囲に、スルー・ホールと、該部品封止及
び搭載用貫通孔とに、スルー・ホール・メッキを施して
回路を形成し、エッチング加工する工程と;から成る請
求項1記載のチップ搭載用基板の製造法。3. A required size is provided at a required portion of a first substrate material having a copper foil, a polyimide, a modified epoxy resin, a glass fiber resin insulating layer and a semi-curable resin bonding sheet each having a required width and thickness. Forming a through hole for component sealing and mounting; a second substrate material comprising a copper foil, a glass fiber epoxy resin insulating layer, and a copper foil each having a required width and thickness; Forming a component sealing and mounting through-hole of a required size at a position corresponding to the component sealing and mounting through-hole of a plate material;
Etching after forming the pattern to form an exposed circuit and a terminal to provide a chip mounting pad; applying a non-flow type adhesive to the lamination surface of the first substrate material; Applying a metal plating resist to the circuit of the substrate material; and applying the first substrate material and the second substrate material to a high temperature,
Pressing at a high pressure for a required time and laminating to form a laminated substrate;
2. The process according to claim 1, further comprising the steps of: forming a circuit by applying through-hole plating to the through-hole and the through-hole for sealing and mounting the component around the laminated substrate to form a circuit; Manufacturing method for chip mounting substrate.
けないことを特徴とする請求項1−3記載のチップ搭載
用基板の製造法。4. The method for manufacturing a chip mounting substrate according to claim 1, wherein no metal substrate for heat radiation is provided on the back side of said laminated substrate.
脂を封止(充填)して成る請求項1−4項記載のチップ
搭載用基板の製造法。5. The method for manufacturing a chip mounting substrate according to claim 1, wherein a synthetic resin is sealed (filled) in place of said metal plating resist.
板材に於て;該絶縁層をガラス繊維エポキシ樹脂とし、
且つ該積層材を半硬化性樹脂ボンディング・シートして
成る請求項1−5記載のチップ搭載用基板の製造法。6. A first substrate material having a copper foil, an insulating layer and a laminated material; said insulating layer is made of glass fiber epoxy resin;
6. The method for manufacturing a chip mounting board according to claim 1, wherein said laminated material is a semi-curable resin bonding sheet.
板材に於て;該絶縁層をガラス繊維エポキシ樹脂とし、
且つ該積層材上の回路に金属メッキ・レジストを施す請
求項1〜6記載のチップ搭載用基板の製造法。7. A first substrate material having a copper foil, an insulating layer and a laminated material; said insulating layer is made of glass fiber epoxy resin;
7. The method for manufacturing a chip mounting board according to claim 1, wherein a metal plating resist is applied to the circuit on the laminated material.
形成した夫々所要広さと厚みとを有する銅箔、絶縁層及
び積層材とを有する第1基板材と;該部品搭載用貫通孔
に対応する箇所に所要大きさの部品搭載用貫通孔を形成
し、所要広さと厚みとを有する銅箔、絶縁層及び銅箔と
を有し、該銅箔にパターン形成後エッチングを施して露
出回路と端子とを形成し、チップ取付用パッドを設け、
該第1基板材の積層面にノン・フロー・タイプの接着剤
を施し、該回路に金属レジストを施した第2基板材と合
わせ、高温、高圧で所要時間加圧した積層基板と;該積
層基板の周囲と該部品封止及び搭載用貫通孔とにエッチ
ングを施してパターンを形成後、回路に金属メッキ・レ
ジストを施し、該積層基板の周囲に形成したスルー・ホ
ールと該部品封止及び搭載用貫通孔とにスルー・ホール
・メッキを施した後エッチングを施して形成した露出回
路とから成るチップ搭載用基板。8. A first substrate material having a required size and thickness of a copper foil, an insulating layer, and a laminated material, each having a required size of a component sealing and mounting through hole; Forming a through hole for mounting a component of a required size at a position corresponding to the hole, having a copper foil having a required width and thickness, an insulating layer and a copper foil, and performing etching after pattern formation on the copper foil. Form an exposed circuit and terminals, provide chip mounting pads,
A laminated substrate which is provided with a non-flow type adhesive on the laminating surface of the first substrate material, is combined with a second substrate material having a metal resist applied to the circuit, and is pressed at a high temperature and a high pressure for a required time; After forming a pattern by etching the periphery of the substrate and the through hole for component sealing and mounting, a metal plating resist is applied to the circuit, and the through hole formed around the laminated substrate, the component sealing and A chip mounting substrate comprising a mounting through-hole and an exposed circuit formed by performing through-hole plating and then etching.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15728497A JPH10313075A (en) | 1997-05-13 | 1997-05-13 | Board for chip mounting use and manufacture thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15728497A JPH10313075A (en) | 1997-05-13 | 1997-05-13 | Board for chip mounting use and manufacture thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH10313075A true JPH10313075A (en) | 1998-11-24 |
Family
ID=15646308
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15728497A Pending JPH10313075A (en) | 1997-05-13 | 1997-05-13 | Board for chip mounting use and manufacture thereof |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH10313075A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008263550A (en) * | 2007-04-13 | 2008-10-30 | Matsushita Electric Ind Co Ltd | Solid-state imaging device and manufacturing method therefor |
-
1997
- 1997-05-13 JP JP15728497A patent/JPH10313075A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008263550A (en) * | 2007-04-13 | 2008-10-30 | Matsushita Electric Ind Co Ltd | Solid-state imaging device and manufacturing method therefor |
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