JPH10312279A - Bit retrieval circuit and method processor having the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a bit retrieval circuit capable of detecting bit retrieval and the termination without the need of a circuit such as an offset circuit, a counter circuit or a subtraction circuit. SOLUTION: This bit retrieval circuit 8 is provided with a register list holding circuit 11 holding a register list, a bit position detection circuit 12 detecting the bit position of first '1' from the register list which the register list holding circuit 11 holds and a bit rejecting circuit 13 rewriting the bit of the detected position into '0' and making the register list holding circuit 11 hold it. The bit position detection circuit 12 is provided with a terminal part (IQ- NULL) outputting a signal '1' showing that all bits in the register list which the register list holding circuit 11 holds become '0'.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bit retrieval circuit for retrieving a predetermined bit from a bit string to be retrieved, and a microprocessor having the bit retrieval circuit and performing an instruction processing requiring a bit retrieval by a microprogram. About.

[0002]

2. Description of the Related Art In a high-level language such as C or C ++, data is saved when calling another function during execution of a program, or data is loaded to restore the original function from processing of the called function. When performing the processing, the microprocessor performs processing such as storing the values of the plurality of registers in the memory, and conversely, loading the values from the memory into the plurality of registers. An instruction set for handling such a plurality of registers is often provided in a microprocessor. In addition, since such processing is frequently performed in a program in a high-level language, it is desired that an instruction that handles a plurality of registers provided in the microprocessor has a small number of machine cycles.

[0003] Instruction sets handling a plurality of registers include, for example, LDM, STM, EXTD, and ENTER. The LDM is an instruction to load a plurality of data continuously arranged in a memory into a plurality of registers. The STM is, on the contrary, an instruction for successively storing data of a plurality of registers on a memory. ENTER
R is an instruction for securing an automatic variable area and saving data of a plurality of registers in a memory. EXTD is ENTER
This is an instruction to load the data of the register saved by the above into the register, release the automatic variable area, and return to the address after the JSR (subroutine jump instruction) executed before the ENTER is executed.

[0004] In such an instruction handling a plurality of registers, a description such as a register list is used. Here, for example, if there is a microprocessor having 16 general-purpose registers, the register list is given as data consisting of a total of 16 bits corresponding to each of the registers r0 to r15, as shown in FIG. . That is, by setting a bit corresponding to a target register to “1”, the register can be designated. For example,
When specifying in the immediate mode, if the registers r0 to r7 are specified, "11111111100000"
000b "(in the case of binary description) or FF00h (16
R0, r2, r4, r6,
In order to specify the eight registers r8, r10, r12, and r14, 1010101010101010b (in the case of binary description) or A0A0h (in the case of hexadecimal description) is described.

Conventionally, when processing an instruction having such a register list by microprogramming, "1" described in the register list is searched from either the upper or lower register list, and "1" is detected. The register corresponding to the specified bit is specified. Search is
A bit position detection circuit composed of a circuit called a priority encoder is used. The bit number next to the bit number detected at this time is held on the circuit and used as an offset for the next search. That is, the search for the next bit is started from the bit having the number indicated by the offset value. When the search is performed for all the bits, the process ends.

[0006]

However, as described above, if all bits are searched, the processing time becomes long. That is, for example, even if the seventh bit is the last "1", there is a disadvantage that the processing speed is long because the search is continued for the eighth and subsequent bits.

[0007] In order to detect the end of a search, Japanese Patent Laid-Open Publication No. Hei 4-260926 discloses an offset value designating circuit indicating a search start bit in a search bit field and a position of the searched bit. A bit position detection circuit for detecting, a bit number counting circuit for counting the total number of bits to be searched in the bit field,
A bit search circuit comprising a search end circuit for detecting a search end by subtracting from a count result when a target bit is detected when the bit position detection circuit searches a plurality of times is disclosed. I have. However, such a circuit requires a circuit for designating an offset value, a counter circuit for counting the number of bits, and a subtraction circuit.

Japanese Patent Application Laid-Open No. Hei 5-134864 discloses a register list process of an instruction for handling a plurality of registers, in which register list data is held in a register indirect register and the register indirect register is shifted. Discloses a micro-instruction control device in which a target bit is searched. The end of the bit search in this device is determined by holding the number of registers to be searched in the count counter, decrementing the count counter each time the search is performed, and setting the count to “0”. Such a device also requires a counter and a subtraction circuit.

[0009] Japanese Patent Application Laid-Open No. 6-59885 discloses that
A bit search circuit is disclosed that performs a search in a circuit without using microprogramming control to perform a search for multiple bits rather than a single bit in a search bit field.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a bit search circuit capable of detecting a bit and detecting the end thereof without requiring a circuit such as an offset circuit, a counter circuit, or a subtraction circuit. It is another object of the present invention to provide a microprocessor that suitably controls a machine cycle of an instruction processing requiring a bit search by performing microprogramming control of the bit search circuit.

[0011]

In order to solve the above problems, a bit search circuit according to the present invention has a bit string holding circuit for holding a bit string to be searched and a first bit string from a bit string to be searched held by the bit string holding circuit. A bit position detection circuit for detecting a bit position of “0” or “1”;
A bit reject circuit for rewriting the bit at the detected position and holding the bit string in the bit string holding circuit.

With the above arrangement, when the first bit position of "0" or "1" is detected from the bit string to be searched by the bit position detection circuit, the bit at the detected position is determined by the bit rejection circuit. It is rewritten and bit searched again. For example, for the search target bit string “1100b”, the first bit position of “1” is 0
At the same time as detecting the bit, the bit string to be searched becomes “0100b” by rewriting of the bit reject circuit, and it is detected that the first bit position of “1” is the first bit in the second bit search. Is done. Then, the bit string to be searched becomes “0000b” by rewriting of the bit reject circuit. Since rewriting is performed by the bit reject circuit in this way,
The bit at the same position is not searched by the bit search again. As described above, the target bit position can be sequentially searched by the bit position detection circuit without performing the offset processing.

An output unit may be provided which outputs a signal indicating that all bits in the search target bit string held by the bit string holding circuit have become "0" or "1". For example, in the above case, the bit string to be searched becomes “00” by rewriting the bit reject circuit.
00b "is output from the output unit, so that the end of the bit search can be detected and the number of machine cycles can be reduced.

Further, a microprocessor according to the present invention comprises:
The execution unit includes any one of the above-described bit search circuits and a register designating circuit that designates a register based on the position of the detected bit. It is characterized by being comprised so that. By microprogramming control of the bit search circuit and the register designating circuit, it is possible to appropriately control a machine cycle of an instruction processing that handles a plurality of arbitrary registers.

[0015]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a microprocessor according to this embodiment. The program code stored in the first memory 1 is stored in a temporary holding circuit (QUE: called a prefetch queue;
The instruction is prefetched, and is configured by a FIFO). The stored program code is divided by the predecoder 3 into an instruction part, an operand part, and operand data. The code of the instruction portion is sent to a PLA (programmable logic array) 4. The PLA 4 sends a control signal to the execution unit 5 every machine cycle. The execution unit 5 includes the general-purpose register 7 and the second
The storage processing and the loading processing of data with the memory 6 are executed. Note that operand data (immediate data,
The register list data) is not directly involved in the identification of the instruction, and thus is sent directly from the temporary holding circuit (QUE) 2 to the execution unit 5 (or the bit search circuit 8 provided in the execution unit 5) by the control signal of the PLA 4. .

FIG. 2 shows the configuration of the bit search circuit 8 provided in the execution unit 5 and the register designating circuit 1 of the execution unit 5.
FIG. 4 is a block diagram showing a relationship with the fourth embodiment. The bit search circuit 8 includes a register list holding circuit (bit string holding circuit) 11 for holding a register list as a search target bit string (a bit string for specifying a register of an arbitrary number of the general-purpose register 7). A bit position detecting circuit 12 for detecting the first bit position of “0” or “1” (in this embodiment, a bit position of “1”) from the register list held by the register list holding circuit 11; And a bit reject circuit 13 for rewriting the bits in the register list holding circuit 11. Further, the register designating circuit 14 designates each register in the general-purpose register 7 by the register number detected by the bit position detecting circuit 12.

FIG. 3 is a circuit diagram showing a specific configuration of the bit search circuit 8. As shown in FIG. Q0 to Q7 in the figure indicate register lists (sent from QUE2). In addition,
The number of bits of the register list data is set to eight because the general-purpose register 7 has eight or less registers (r0 to r).
7: half the configuration of the register in FIG. 5), the number of bits becomes 16 if the number of general-purpose registers 7 is 9 to 16, and 19 to 32 When extended to books, etc., the number of bits is 3
Needless to say, there will be two. Q0 to Q7 are input to the register list holding circuit 11 via the second circuit section 13b of the bit reject circuit 13. The register list holding circuit 11 is composed of a total of eight flip-flops FF0 to FF7, and holds an input in each FF when an IQ_LT signal serving as a latch signal rises, and outputs it as SB0 to SB7.

The bit position detecting circuit 12 comprises a first circuit section 12a and a second circuit section 12b. First circuit unit 1
2a has seven logic circuits. The logic circuit of the first stage (the uppermost stage in the drawing) inverts SB0 and SB1 respectively and outputs the AND as N0. The logic circuit of the second stage inverts the input of SB2, inputs the output of the logic circuit of the first stage, and outputs its AND as N1.
Hereinafter, similarly, each logic circuit inverts each output of SB3 to SB7, inputs the output of the logic circuit of each upper stage, and outputs its AND to N2 to N5 and IQ_NUL.
L is output. Here, SB0
When all of SB7 are “0” (register list is N
In the case of ULL), N0 = N1 = N2 = N3 = N4 =
N5 = IQ_NULL = "1". Second circuit unit 12
b is composed of a plurality of various logic circuits;
0 to N5, SB0, SB3, SB5, and SB7 are input, and three signals R0, R1, and R2 are output. R
2 to R0 are signals indicating register numbers. For example, if “R2R1R0” = “001b”, it indicates the first register r1, and “R2R1R0” = “101
If "b", it indicates the fifth register r5.

The bit reject circuit 13 comprises a first circuit section 13a and a second circuit section 13b. First circuit unit 13
"a" is composed of eight NAND logic circuits. N0 to N5 and SB0 to SB7 are appropriately input to each input terminal unit, and a SCAN signal is input to one of the input units and T0 to T7 is output. Have been. The SCAN signal is
It is controlled by the PLA 4 by a microprogram. T0 to T7 are signals indicating rewriting of the bit at the detected position. If the detected bit is the 0th bit, T0 becomes "0". The second circuit section 13b is composed of eight 2-input AND logic circuits, and one input section of each of the logic circuits has the T0 to T
7 and Q0 to Q7 are input to the other input terminal section. Therefore, for example, when T0 is set to “0”, even if Q0 is “1”, it is rewritten and SB0 is set to “0”.

FIG. 4 shows that, in the 8-bit register list data (Q0 to Q7), a bit is detected and the bit at the detected position is further rewritten to SB0 to SB7.
FIG. 7 is an explanatory diagram showing a state of being output as 7; As shown in FIG. 11A, the register list data is "010".
01100b ". Here, for the bit numbers" 0, 1, 2, ..., 7 "of the register list data,
If the register numbers correspond to “r0, r1, r2,..., R7”, the register list data in FIG. 9A specifies three general-purpose registers r1, r4, and r5. (This case is defined as normal rotation, and the case of normal rotation will be described below as an example). On the other hand, if the bit number of the register list data corresponds to “0, 1, 2,..., 7”, the register number corresponds to “r7, r6, r5,. Register list data designates three general-purpose registers r6, r3, and r2 (this case is assumed to be the reverse).

Hereinafter, the bit search process and the rewriting process of the bit at the detected position will be described with reference to FIG. 4 as an example. Initially, register list data (Q0 to Q7) =
SB0 to SB7 = "01001100b" (r
When these data are inputted, N0 to N5 = "000000". In this case, since N0 = “0” and SB0 = “0”, R0 = “1”, and since N0 = “0”, R1
= "0" and N2 = "0", so R2 = "0"
Becomes Therefore, “R2R1R0” = “001”, and the first bit (that is, the designation of the register r1) is detected (see FIG. 13B). Then, to the logic circuit that outputs T1 as a rewrite signal for the first bit, “1” which is an inverted signal of SB0 = “0”, SB1 = “1”, and SCAN = “1” Since it is input, T1 = "0". As a result, Q1
Is masked, SB1 = "0", and SB0 to SB7
= “00001100b” (see FIG. 3C).

After the above rewriting, IQ_NULL = "1"
It is determined whether or not SB0 to SB7 = “00001”.
In the state of "100b", IQ_NULL = "0", so that the bit search is continued. By the input of the rewritten signal, N0 to N5 = "111000".
Becomes Since N2 = “1”, R2 = “1” and N4
= "0", R1 = "0", and R0 =
Since it becomes "0", "R2R1R0" = "100", and the fourth bit (that is, the designation of the register r4) is detected (see FIG. 4D). Then, to the logic circuit that outputs T4 as a rewrite signal for the fourth bit, SB4 = “1”, N2 = “1”,
Since SCAN = "1" is input, T4 = "0". As a result, Q4 is masked and SB4 = "0"
And rewriting is performed as SB0 to SB7 = “00000100b” (see FIG. 9E).

After the above rewriting, IQ_NULL = "1"
It is determined whether or not SB0 to SB7 = “00000”.
In the state of "100b", IQ_NULL = "0", so that the bit search is continued. By the input of the rewritten signal, N0 to N5 = "111100".
Becomes Since N2 = “1”, R2 = “1” and N4
= "0", R1 = "0", and N3 =
Since it is “1” and SB5 = “1”, R0 = “1”. Therefore, “R2R1R0” = “101”, and the fifth bit (that is, the designation of the register r5) is detected (see FIG. 11F). Then, to the logic circuit that outputs T5 as a rewrite signal for the fifth bit, SB5 = “1”, N3 = “1”, and SCA
Since N = “1” is input, T5 = “0”.
As a result, Q5 is masked, SB5 = "0", and rewriting is performed as SB0-SB7 = "00000000b" (see FIG. 11E).

Then, as described above, SB0-SB7 =
When “00000000b” is reached, IQ_NULL =
Since it becomes "1", the end of the bit search is detected.

Next, the microprogramming control for performing the above-described bit search processing in an instruction set that handles a plurality of registers will be described using an instruction called LDM as an example. First, the LDM microcode is transferred from the first memory 1 to the temporary holding circuit (QUE) 2 and the predecoder 3
To be divided into an instruction part and an operand part. The register list is stored in QUE2. Then, a control signal is provided from the PLA 4 to the execution unit 5 every machine cycle. give. Further, the LDM transfers data from the second memory 6 to the general-purpose register 7, so that address information of the second memory 6 is required. Since this address information exists in the operand portion, another address is simultaneously provided in the first machine cycle. The address information is transferred to the execution unit 5 via the bus.

In the latter half of one machine cycle, PLA4
A control signal for making a NULL determination in the register list is output to the execution unit 5. Since the judgment result appears in the next second machine cycle, if NULL, it means that there is no register to be transferred in the register list.
A control signal for terminating LDM is output in the machine cycle. If it is other than NULL, there are registers to be transferred, so that the register list is processed after three machine cycles.

The processing of the register list is performed for one register in three machine cycles.

(First Machine Cycle) The bit position detection circuit 12 detects a bit having "1" in the register list. At the same time, the execution unit 5 transfers the above-mentioned address information to ADD (a register that holds a memory address when inputting / outputting to / from a memory). When the execution unit 5 exchanges data with the second memory 6, the ADD is referred to as an address. In addition, the bit reject circuit 13 rewrites bits in the register list of the register list holding circuit 11 (bit “1” at the detected position →
“0”). Also, it outputs a control signal for performing NULL determination (performed in the next cycle) of the register list.

(Second machine cycle) The number (ie, register number) indicating the position of the searched bit is transferred to the register specifying circuit 14. Further, it is determined whether or not the rewritten register list has become NULL.

(Third Machine Cycle) If the register list becomes NULL, the instruction processing is completed in the third machine cycle. On the other hand, if the register list is NU
If it is not LL, the same processing as the processing in the first machine cycle described above is executed, and the processing is continued until the register list becomes NULL.

In the above embodiment, the first bit position of "1" is detected from the bit string to be searched, but the first bit position of "0" is detected and rewritten to "1". Alternatively, the configuration may be such that a signal indicating that the register list is NULL is output when all bits in the search target bit string become “1”.

When the bit number of the register list data is "0, 1, 2, ..., 7", the register number is "r".
7, r6, r5,..., R0 ", an output signal is inverted by connecting an XOR circuit to the output terminal R2R1R0 as shown in FIG. 5 and controlling the input terminal REG_REV. For example, if the register list data is “00100000”, the expected transfer register is r5, and “R2R1R0” = “010” at that time.
By setting _REV to “1”, each bit is inverted and “RR”
2RR1RR0 "=" 101 ", and the expected register number is obtained.

[0034]

As described above, according to the present invention, a bit search and its end can be detected without the need for a circuit such as an offset circuit, a counter circuit, or a subtraction circuit. In addition, a microprocessor that microprograms and controls a bit search circuit and a register designating circuit has an effect that a machine cycle of instruction processing that handles a plurality of arbitrary registers can be suitably controlled.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a microprocessor according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a bit detection device according to an embodiment of the present invention.

FIG. 3 is a circuit diagram showing details of a bit detection device of FIG. 2;

FIG. 4 is an explanatory diagram showing a state in which a bit at a detected position is rewritten and output in a register list of the present invention.

FIG. 5 is a diagram illustrating an example of a register instruction circuit.

FIG. 6 is an explanatory diagram of a register list.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 1st memory 2 Temporary holding circuit (QUE) 3 Predecoder 4 PLA 5 Execution part 6 2nd memory 7 General-purpose register 8 Bit search circuit 11 Register list holding circuit 12 Bit position detection circuit 13 Bit reject circuit 14 Register specification circuit

Claims (3)

[Claims] A bit string holding circuit for holding a bit string to be searched, a bit position detecting circuit for detecting the first bit position of "0" or "1" from the bit string to be searched held by the bit string holding circuit, And a bit reject circuit for rewriting the bit at the set position and holding the bit string in the bit string holding circuit. 2. An output unit for outputting a signal indicating that all bits in a search target bit string held by the bit string holding circuit have become “0” or “1”. 2. The bit search circuit according to claim 1, wherein: 3. An execution unit comprising: a bit search circuit according to claim 1; and a register designating circuit for designating a register based on a detected bit position. Is configured to be controlled by a control signal based on microprogramming.