JPH10311985A - Manufacture of thin film transistor and manufacture of active matrix substrate for liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the manufacture of a TFT substrate which reduces the manufacture cost and variance in LDD(low-density source-drain area) length among TFTs (thin film transistor) and prevents damage due to a charge-up at the time of implantation of impurity ions. SOLUTION: When a TFT is manufactured, gate electrodes 15, 25, and 35 are formed and then a coating ITO(indium thin oxide) film 41 is formed on the surface sides to obtain the same state with the formation of a side wall. In this state, impurity ions of high density are implanted and then the implantation amount of impurity ions is small in a source-drain area facing end parts of the gate electrodes, so an LDD area (low-density source-drain area) is automatically formed, eliminating the need for a resist mask covering the gate electrodes a little wider. The coating ITO film 41 is conductive, so the charge-up at the time of the implantation of impurity ions can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a thin film transistor (hereinafter, referred to as TFT) and a method of manufacturing an active matrix substrate for a liquid crystal display device using the same. More specifically, the present invention relates to a technology for manufacturing a TFT having an LDD structure or an offset gate structure.

[0002]

2. Description of the Related Art In an active matrix substrate with a built-in drive circuit used for a liquid crystal display device, a drive circuit is formed using complementary TFTs, and a pixel switching TFT is formed in a pixel region. Where TF
When T has a self-aligned structure, there is a problem that the transfer characteristics of the self-aligned N-type TFT and the P-type TFT are large as shown in solid lines L1 and L2 in FIG. 9, respectively. As described above, when a TFT having a large off-leak current is used for pixel switching, it causes a reduction in contrast, uneven display, flicker, and the like. In addition, when a driving circuit is formed by a TFT having a large off-leakage current, a malfunction may be caused.

Therefore, as a TFT used for an active matrix substrate, a TFT having an LDD structure or an offset gate structure tends to be used. In this type of TFT, since the electric field intensity at the drain end is reduced, FIG. 10 shows an N-type TFT and a P-type TFT having an LDD structure.
As shown by the solid lines L3 and L4, respectively, the transfer characteristics of the FT can reduce the off-leakage current. Therefore, when a TFT having an LDD structure is used for pixel switching, a decrease in contrast and the like can be prevented. In addition, when the driving circuit is configured by the TFT having the LDD structure, malfunction can be prevented, and
Since the channel length can be shortened by the higher withstand voltage, operation speed and reliability can be improved.

In manufacturing an active matrix substrate having such a structure, as briefly described with reference to FIG. 11, an impurity introduction step is performed four times to form a source / drain region having an LDD structure. Here, N-type pixel TFTs and N-type TFTs are arranged on the surface side of the insulating substrate 2 which is the base of the active matrix substrate from left to right.
The description will be made assuming that a TFT for a driving circuit of a type and a TFT for a driving circuit of a P type are formed.

[0005] First, as shown in FIG.
After the gate insulating films 14, 24, 34 and the gate electrodes 15, 25, 35 are sequentially formed on each of the island-shaped polysilicon thin films for forming the active layer of The area where the TFT is to be formed is formed with a resist mask 5
3, a low concentration donor-type impurity is ion-implanted into a region where the pixel TFT and the N-type drive circuit TFT are to be formed, and self-aligned with the gate electrodes 15 and 25. The lightly doped source regions 11b and 21b and the lightly doped drain regions 12b and 22b are formed. The portion where the impurity is not introduced is the channel forming region 13,
23. Thereafter, the resist mask 53 is removed.

Next, as shown in FIG. 11B, in addition to a region where a P-type driving circuit TFT is to be formed, a pixel TF is formed.
Gate electrodes 15, 2 of T and N type drive circuit TFTs
After the formation of the resist mask 54 that widely covers the region 5, a high-concentration donor-type impurity is ion-implanted. as a result,
The low-concentration source regions 11b and 21b and the low-concentration drain regions 12b and 22b have a high-concentration source region 11b.
2, 212, and high concentration drain regions 122, 222
Is formed. On the other hand, of the low-concentration source region 11 and the low-concentration drain region 12, the portion covered with the resist mask 54 is left as it is.
1, 211, and low concentration drain regions 121, 221
Becomes In this manner, the pixel TFT 1 having the LDD structure is formed.
The 0 and N type drive circuit TFTs 20 are formed. Thereafter, the resist mask 54 is removed.

Next, as shown in FIG. 11C, the P-type driving circuit TFT is covered with the pixel TFT 10 and the N-type driving circuit TFT 20 covered with the resist mask 55.
A low concentration acceptor-type impurity is ion-implanted into the region to be formed to form a low concentration source region 31b and a low concentration drain region 32b in self-alignment with the gate electrode 35. Note that the portion where the impurity is not introduced becomes the channel formation region 33. Thereafter, the resist mask 55 is removed.

Next, as shown in FIG. 11D, in addition to the pixel TFT 10 and the N-type drive circuit TFT 20, a resist mask 56 that widely covers the gate electrode 35 of the P-type drive circuit TFT 30 is also provided. Is formed, high-concentration acceptor-type impurities are ion-implanted. as a result,
A high-concentration source region 312 and a high-concentration drain region 322 are formed in the low-concentration source region 31b and the low-concentration drain region 32b. On the other hand, the portions of the low-concentration source region 31 and the drain region 32 that are covered with the resist mask 56 are left as they are.
11 and a lightly doped drain region 321. Thus, the P-type drive circuit TFT 30 having the LDD structure is formed. Thereafter, the resist mask 56 is removed.

By omitting the low-concentration impurity introduction step shown in FIGS. 11A and 11C, a TFT having an offset gate structure can be formed instead of a TFT having an LDD structure.

In such a method of manufacturing a TFT, when ion implantation is performed, an island-shaped conductive region (a gate electrode, a gate wiring, a semiconductor region into which impurities are introduced, etc.) is formed on the insulating film. When high-concentration ions are implanted in this state, charges are accumulated on the island-shaped conductive region and the insulating film.
However, since the shape and size of each island-shaped conductive region or the distance between the regions are different, the amount of accumulated charge differs for each region. As a result of such non-uniform charge-up, a discharge occurs between the conductive regions, between the gate electrode and the semiconductor layer to be the source / drain region, between the substrate holding member of the ion implantation apparatus and each pattern, and the like. TFT
Degradation of characteristics (increase in off-leak current, decrease in on-current,
(E.g., a shift in threshold voltage), a reduction in gate withstand voltage, and damage to the pattern itself. As a method for preventing such damage from occurring, there is a method in which annealing is performed after ion implantation. However, since damage may not be completely recovered, there is a particular problem when manufacturing a TFT by a low-temperature process. Become. There is also a method of forming a thin metal film on the entire surface before ion implantation to prevent the occurrence of damage due to charge-up. However, this method requires removing the metal film later, so However, there are problems such as an increase in the number and an effect on the gate electrode formed of metal when the metal thin film is removed.

[0011]

The manufacturing cost of an active matrix substrate greatly varies depending on the number of times a resist mask is formed.
To manufacture FT, N-type and P-type
In the method of introducing the active matrix substrate one by one, the manufacturing cost of the active matrix substrate is high. Moreover, regardless of whether the TFT having the LDD structure or the TFT having the offset gate structure is manufactured, the resist mask 5 for introducing the high concentration impurity is used.
When the formation positions of the gate electrodes 4 and 56 are shifted with respect to the gate electrodes 15, 25 and 35, the shift directly causes variations in the LDD length and the offset length. In particular, when manufacturing a large number of TFTs on a large substrate such as an active matrix substrate of a liquid crystal display device, the resist mask 54,
It is difficult to perform high-precision mask alignment for forming 56. Therefore, in the conventional method of manufacturing an active matrix substrate, not only is it difficult to reduce the manufacturing cost, but also there is a problem that variations in the LDD length and the offset length between the TFTs cannot be further reduced.

In view of the above problems, an object of the present invention is to
A TFT manufacturing method capable of reducing the manufacturing cost and the variation in LDD length between each TFT, and preventing the occurrence of damage due to charge-up when introducing impurity ions. And a method for manufacturing an active matrix substrate for a liquid crystal display device.

[0013]

In order to solve the above-mentioned problems, in a method for manufacturing a TFT according to the present invention, a semiconductor film is formed on a substrate, and a gate insulating film and a gate insulating film are formed on the surface of the semiconductor film.
Forming a conductive coating film on the surface side of the gate electrode after forming the gate electrode and the gate electrode sequentially; and forming an impurity ion on the semiconductor film via the conductive coating film and the gate insulating film. An impurity introducing step of forming a source / drain region by introducing a conductive coating film, a conductive coating film removing step of removing the conductive coating film, and an interlayer on a surface side of the gate electrode after removing the conductive coating film. And forming an interlayer insulating film for forming an insulating film.

In the present invention, in the conductive coating film forming step, a liquid coating material containing a precursor of the conductive coating film is applied to the entire surface of the substrate by a spin coating method.
The precursor is made conductive by heat treatment.

Here, as the conductive coating film, for example, a coating ITO film (Indium Tin Oxid) is used.
e) can be used.

In the present invention, if a conductive coating film is formed on the surface side after the gate electrode is formed, the thickness of the conductive coating film at the end of the gate electrode is increased by an amount corresponding to the thickness of the gate electrode. It is formed. That is, the state is the same as that of forming the sidewall at the end of the gate electrode only by forming the conductive coating film on the surface side of the gate electrode. Therefore, just by introducing impurity ions in this state,
The portion of the source / drain region facing the end of the gate electrode is thicker than the conductive coating film formed thereon.
The amount of impurity ions introduced is considerably smaller than in other regions. Therefore, an LDD region is automatically formed in the source / drain region. Therefore, unlike the method of preventing a high concentration of impurity ions from being introduced into the LDD region by a resist mask that covers the gate electrode a little wider, the number of steps for forming the resist mask is reduced and the size of the substrate is increased. Also, the LDD length does not vary due to the mask alignment accuracy. In the conventional manufacturing method,
Non-uniform charge-up occurs when introducing impurity ions, and the discharge causes damage to the TFT. However, according to the present invention, when implanting impurity ions, the surface is covered with a conductive coating film. This uneven charging does not occur. Therefore, it is possible to prevent the gate insulating film and the like from being damaged when the impurity ions are introduced.

Here, it has been described that the LDD region is formed in the source / drain region. However, when the amount of impurities introduced into the LDD region is extremely small, it can be considered that an offset region is formed. That is, according to the present invention,
A TFT having an offset gate structure can also be manufactured.

In the present invention, it is preferable that a conductive film having a sheet resistance of 10 ⁷ Ω / □ or less is formed as the conductive coating film so as to reliably prevent charge-up when introducing impurity ions.

The conductive coating film may have a thickness of 1000
When a conductive film having a thickness of about Å is formed, an LDD length sufficient to function as a TFT having an LDD structure can be secured.

In the present invention, after the gate insulating film and the gate electrode are sequentially formed, and before performing the conductive coating film forming step, the gate insulating film is etched using the gate electrode as a mask. Preferably, an etching step is performed. At the time of introducing the impurity, even if an attempt is made to make a predetermined difference in the thickness of the film which should be a barrier for introducing the impurity into the semiconductor film at a position apart from and around the gate electrode, if there is a gate insulating film there, Since the film thickness is constant irrespective of location, the above-mentioned barrier film has to be formed as a whole thicker. However, in the present invention, the gate insulating film does not exist in a portion of the surface of the semiconductor film other than immediately below the gate electrode. Therefore, at the time of introducing the impurity, when an attempt is made to make a predetermined difference in the thickness of the film which is to be a barrier to the introduction of the impurity into the semiconductor film at a position distant from the periphery of the gate electrode, The difference can be defined only by the conductive coating film. Therefore, at a position distant from the gate electrode, the film thickness can be reduced, so that energy for introducing impurities can be reduced.

In this case, after the gate insulating film etching step is performed and before the conductive coating film forming step is performed, an insulating coating film forming step of forming an insulating coating film on the surface side of the gate electrode is performed. Preferably, a step is performed. That is, since the coating film (insulating coating film) is located just below the conductive coating film, as described above, the amount of impurities introduced into this portion by utilizing the thick coating film around the gate electrode is utilized. Can be suppressed. Further, even when the gate insulating film immediately below the gate electrode is over-etched when the gate insulating film is etched, an overhang structure can be prevented by the insulating coating film. Even in this case, the portion of the surface of the semiconductor film other than immediately below the gate electrode does not have the gate insulating film, and the portion far from the gate electrode can be made thinner, so that energy for introducing impurities is small. I can do it.

In the present invention, after the gate insulating film and the gate electrode are sequentially formed, before performing the step of forming the conductive coating film, a mask for widely covering the gate electrode is formed. It is preferable to perform a gate insulating film etching step of etching the gate insulating film. With this configuration, the amount of impurities introduced into this portion can be suppressed by utilizing the gate insulating film remaining around the gate electrode and the conductive coating film formed thick around the gate electrode.

In the present invention, in the impurity introducing step, it is preferable to introduce impurity ions while keeping the conductive coating film at a ground potential. For example,
It is preferable that the conductive coating film is held at the ground potential in the impurity introduction step by holding the substrate in a state where the substrate holder set to the ground potential is electrically connected to the conductive coating film. With this configuration, it is possible to more reliably prevent charge-up when introducing impurity ions.

According to the method of manufacturing a thin film transistor having the above-described configuration, a large number of TFTs having no variation in LDD length can be formed on a large-sized substrate. It is suitable for forming a thin film transistor for a driving circuit for forming a driving circuit on the substrate of the above, and for forming a thin film transistor for pixel switching in a pixel region.

[0025]

Embodiments of the present invention will be described with reference to the drawings.

Embodiment 1 (Configuration of Active Matrix Substrate) FIG. 1 is a cross-sectional view schematically showing an active matrix substrate with a built-in driving circuit of a liquid crystal display device according to the present embodiment. In FIG. 1, contact holes in the interlayer insulating film and electrodes electrically connected to the source / drain regions via the contact holes are omitted.

In FIG. 1, three types of T-type are provided on the surface side of an insulating substrate 2 which is a base of an active matrix substrate 1.
An FT is formed, of which the one on the left is
The N-type pixel TFT 10 is shown. A TFT 20 for the N-type driving circuit is shown in the center, and a TFT 30 for the P-type driving circuit is shown on the right side. Among these TFTs, the N-type drive circuit TFT 20 and the P-type drive circuit TFT 30 constitute a CMOS circuit such as an inverter of the drive circuit.

That is, as shown in FIG. 2A, the liquid crystal display device has, on its active matrix substrate, a pixel area defined by data lines 90 and scanning lines 91. There is a liquid crystal capacitor 94 of a liquid crystal cell to which an image signal is input via the TFT 10 for use. For a data line 90, a data driver unit 82 including a shift register 84, a level shifter 85, a video line 87, and an analog switch 86 is formed on an active matrix substrate. For a scanning line 91, a scanning driver unit 83 including a shift register 88 and a level shifter 89 is formed on an active matrix substrate. In the pixel region, a storage capacitor 93 is also formed between the pixel region and the preceding scanning line. In the shift registers 84 and 88, as shown in FIG. 2B, two-stage inverters, N-type TFTs 20 and P-type TFTs 30 form CMOS circuits, respectively.

Referring again to FIG. 1, an N-type pixel TFT
10, the N-type drive circuit TFT 20 and the P-type drive circuit TFT 30 all have the same basic structure.
Channel forming regions 13, 23, 33 in which channels can be formed between drain regions 1, 31 and drain regions 12, 22, 32.
And gate electrodes 15, 25, and 35 that face each other via the gate insulating films 14, 24, and 34 on the surface side of these channel formation regions.

In the active matrix substrate 1, the source regions 11, 21, 31 and the drain region 12,
22 and 32, low-concentration source regions 111, 211 and 311 and low-concentration drain regions 121 are provided at portions facing the ends of the gate electrodes 15, 25 and 35 via the gate insulating films 14, 24 and 34, respectively. , 221 and 321 are formed, and each TFT has an LDD structure.

The source region 11, 21 and the drain region 12, 22 of the pixel TFT 10 and the N-type driving circuit TFT 20 have a low concentration source region 111,
Regions other than 211 and the low-concentration drain regions 121 and 221 are high-concentration source regions 112 and 212 and high-concentration drain regions 122 and 222 having an impurity concentration of about 1.0 × 10 ²⁰ cm ⁻³ or more. Concentration source region 1
11, 211 and low-concentration drain regions 121, 22
The impurity concentration of No. 1 is about 0.5 × 10 ²⁰ cm ⁻³ or less. Further, the source region 3 of the P-type driving circuit TFT 30 is formed.
1 and the drain region 32, the low-concentration source region 3
11 and the low-concentration drain region 321 are a high-concentration source region 312 and a high-concentration drain region 322 having an impurity concentration of about 1.0 × 10 ²⁰ cm ⁻³ or more. The impurity concentration of the region 321 is about 0.5 × 10 ²⁰ cm ⁻³ or less. Electrodes (not shown) such as data lines and pixel electrodes for each TFT are electrically connected to these high-concentration regions via contact holes in the interlayer insulating film 4.

Thus, in any TFT,
Source regions 11, 21, 31 and drain region 1
Of the regions 2, 22, and 32, the portions facing the ends of the gate electrodes 15, 25, and 35 are the low-concentration source regions 111, 21.
1, 311 and lightly doped drain regions 121, 22
Since they are 1, 321, the electric field strength at the drain end is reduced. Therefore, the driving circuit TFT 20
In the TFT 30 for the driving circuit, since the off-leakage current is small, a malfunction due to the off-leakage current does not occur, and the current flowing between the power supply terminals of the CMOS circuit is small. In addition, when the driving circuit is formed by the TFTs 20 and 30 having the LDD structure, the channel length can be shortened by the higher withstand voltage, so that the operation speed and the reliability can be improved. In addition, since the off-leak current is small even in the pixel TFT 10, display unevenness and flicker do not occur.
Also, when the off-state current is small, the holding characteristics are improved,
There are also advantages such as improvement in contrast.

(Method of Manufacturing Thin Film Transistor) Each TFT having such an LDD structure can be manufactured by the following method.

First, as shown in FIG. 3A, a polysilicon thin film 3 is formed on the surface of an insulating substrate 2 such as a glass substrate by using an LPCVD method or a plasma CVD method. There is also a method of forming a polysilicon thin film by performing laser annealing or lamp annealing after forming an amorphous silicon thin film.

Next, as shown in FIG. 3B, the polysilicon thin film 3 is patterned by a photolithography method, and is patterned into island-like silicon thin films 11a, 21a, 3a.
1a.

Next, as shown in FIG. 3C, the island-shaped silicon thin films 11a, 21a and 31a are formed to a thickness of about 1200 angstroms by thermal oxidation, LPCVD, plasma CVD or the like. The gate insulating films 14, 24, 34 made of a silicon oxide film are formed (gate insulating film forming step).

Next, as shown in FIG. 3D, gate electrodes 15, 25, 35 made of doped silicon, silicide film, etc. are formed on the surfaces of the gate insulating films 14, 24, 34 (gate electrode). Forming step).

Next, as shown in FIG. 4A, a coating ITO film 41 (conductive coating film) is formed on the surface of the gate electrodes 15, 25, and 35, that is, on the entire surface of the insulating substrate 2 (FIG. 4A). Conductive coating film forming step).

In this coating film formation, a liquid coating material is applied to the entire surface of the insulating substrate 2 by using a spin coating method or the like. The coating material used in the present embodiment is a liquid material in which organic indium and organic tin as precursors of the coated ITO film 41 are mixed in xylol at a ratio of 97: 3 to 8% (for example, Asahi Denka Kogyo Co., Ltd.). Trade name: ADEKA ITO coating film / ITO-103L), and can be applied to the surface side of the insulating substrate 2 by a spin coating method. When applying by spin coating, if the viscosity of the applied material is 20 cp, the rotation speed of the substrate is set to 2000 rpm, and a coating film (composition / precursor of organic indium and organic tin) of about 1 μm is formed. I do. Here, as the coating material, for example, a material having a ratio of organic indium to organic tin in a range of 99/1 to 90/10 can be used.

In this embodiment, the coating material applied to the front surface side of the insulating substrate 2 is subjected to heat treatment (baking) after drying and removing the solvent. At this time, the heat treatment is performed, for example, in air at 100 ° C. or in a non-reducing atmosphere.
After performing preliminary heat treatment of the quartile, 250 ° C to 450 ° C
Heat treatment in air or a non-reducing atmosphere for 30 minutes to 60 minutes, and then in a hydrogen-containing atmosphere or a reducing atmosphere at 200 ° C. to 400 ° C. for 30 minutes to 60 minutes.
Heat treatment for a minute. As a result, the organic component is removed, and a mixed film (the applied ITO film 41) in which the thickness of indium oxide and tin oxide is about several thousand angstroms is formed. The sheet resistance of the coated ITO film 41 formed in this way is 10 ⁴ Ω / □ to 10 ⁶ Ω / □.

When the coating ITO film 41 is formed in this way, the end portions of the gate electrodes 15, 25, and 35 correspond to the thicknesses of the gate electrodes 15, 25, and 35, respectively.
The TO film 41 becomes thick. For example, the gate electrodes 15, 2
The thickness of the gate insulating films 14, 24, and 34 is about 1200 angstroms, and the thickness of the ITO film 41 in the flat portion is about 1 angstroms.
If the thickness is 2,000 angstroms, the applied ITO film 41
Has a thickness of 2000 angstroms at a position about 0.5 μm away from the end of the gate electrode,
Around 5,35, the thickness is about 6000 Å. By utilizing such a difference in thickness, an LDD region is formed in the subsequent steps.

First, as shown in FIG. 4B, a region where the pixel TFT 10 is to be formed and a region where the N-type drive circuit TFT 20 is to be formed are covered with the resist mask 51 on the surface side of the insulating substrate 2. . In this state, acceptor-type impurities, for example, boron ions are deposited at 2.0 × 10 ¹⁵ cm.
^The source region 31 and the drain region 32 are formed by ion implantation at a dose of ^-2 (P-type high-concentration impurity introduction step).

As a result, the portion where the impurity is not introduced becomes the channel forming region 33. However, source region 3
1 and a portion of the drain region 32 facing the end of the gate electrode 35, a coated ITO film 41 covering the end thereof.
, The actual impurity introduction amount is about two orders of magnitude lower than other portions. Accordingly, in the source region 31 and the drain region 32, the low concentration source region 311 and the low concentration drain region 321 having the impurity concentration of about 2.0 × 10 ¹⁸ cm ⁻³ are included in the portion facing the end of the gate electrode 35.
It is formed with an LDD length of about 5 μm. On the other hand, the impurity concentration of the high-concentration source region 312 and the high-concentration drain region 322 other than that is approximately 2.0 × 10 ²⁰ cm ^−3.
Becomes Thus, the P-type driving circuit TFT 30
Is formed. Thereafter, the resist mask 51 is removed.

Next, as shown in FIG. 4C, the formation region of the P-type driving circuit TFT 30 is covered with a resist mask 52. In this state, donor-type impurities, for example, phosphorus ions are implanted at a dose of 1.0 × 10 ¹⁵ cm ⁻² , and the source region 11, the drain region 1, and the drain region 1 are doped.
2 and 22 are formed (N-type high-concentration impurity introduction step).

As a result, the portions where the impurities are not introduced become the channel forming regions 13 and 23. However, among the source regions 11 and 21 and the drain regions 12 and 22,
In the portion facing the end portions of the gate electrodes 15 and 25, the coated ITO film 41 covering the end portions is thicker, so that the actual impurity introduction amount is about two orders of magnitude lower than in other portions. Therefore, in the source regions 11 and 21 and the drain regions 12 and 22, the low-concentration source regions 111 and 211 having an impurity concentration of about 1.0 × 10 ¹⁸ cm ⁻³ are provided at portions facing the ends of the gate electrodes 15 and 25. , And the low concentration drain region 121,
221 is formed with an LDD length of about 0.5 μm. On the other hand, the high concentration source regions 112 and
2, and the impurity concentration of the high-concentration drain regions 122 and 222 are about 1.0 × 10 ²⁰ cm ⁻³ . Thus, the pixel TFT 10 and the N-type drive circuit T
The FT 20 is formed. After a while, the resist mask 5
Remove 2.

Next, as shown in FIG. 4D, the coated ITO 41 formed on the entire surface of the insulating substrate 2 is removed by etching (a conductive coating film removing step).

As the etching at this time, wet etching using an aqua regia-based etchant or a hydrogen bromide-based etchant can be used. When an aqua regia-based etchant is used, the etchant is set at about 40 ° C. and etching is performed for 30 seconds to 60 seconds. When a hydrogen bromide-based etchant is used, the etchant is kept at room temperature to perform etching for about 60 seconds. Since Al is resistant to a hydrogen bromide-based etchant, it is desirable to use a hydrogen bromide-based etchant for removing the applied ITO when the gate electrode is formed of Al.

Thereafter, as shown in FIG.
VD method, APCVD method, plasma CVD method, O ₃ TE
The thickness is about 0.8 by the OS method, the O ₂ TEOS method, or the like.
forming an interlayer insulating film 4 made of a silicon oxide film having a thickness of μm;
Annealing for activation is performed (interlayer insulating film forming step). For each TFT, after forming a contact hole in the interlayer insulating film 4, predetermined electrodes (data lines and pixel electrodes) are formed.

As described above, in the present embodiment, when the high concentration impurity is introduced in the impurity introduction step, the gate electrode 15,
Utilizing the fact that the coated ITO film 41 formed in advance on the surface side of 25, 35 forms a sidewall near the end of the gate electrode 15, 25, 35, without using a resist mask , Low concentration source regions 111, 211, 3
11, and low-concentration drain regions 121, 221, 32
Form one. Therefore, the N-type TFT 1 having the LDD structure
Only one impurity introduction step is required to produce 0 and 20;
In order to manufacture a P-type TFT having an LDD structure, only one impurity introduction step is required. Therefore, the number of times of forming a resist mask can be reduced. In addition, the gate electrodes 15, 2
LD with a resist mask that covers a little wider than 5 and 35
Unlike the method of preventing the introduction of high-concentration impurity ions into the D region (low-concentration source / drain regions), even when a large number of TFTs are formed on the large-sized insulating substrate 2, due to the mask alignment accuracy. No variation in LDD length occurs. In addition, in the conventional manufacturing method, when the impurity ions are introduced, charges are charged up in the gate insulating films 14, 24, and 34, and the gate insulating films 14, 24, and 34 may be damaged. According to the present invention, when the impurity ions are implanted, the surface thereof is covered with the applied ITO film 41.
No charge-up occurs. Therefore, it is possible to prevent the gate insulating films 14, 24, and 34 from being damaged when impurity ions are introduced. Therefore, according to this embodiment, the TFTs 10, 20, and 30 having the LDD structure can be formed with a small number of steps, so that the manufacturing cost can be reduced and the LD between the TFTs can be reduced.
Reduction of variation in D length, that is, reduction of variation in off-leak current and on-current can be achieved.

Further, in this embodiment, even though the coated ITO film 41 is formed, a spin coating method suitable for processing a large substrate is used, so that the manufacturing method is not complicated, and an inexpensive film forming apparatus and the like can be used. The applied ITO film 41 can be formed by a heat treatment apparatus.

[Embodiment 2] Another embodiment of the present invention will be described. In the following description, a method of manufacturing the pixel TFT 10 among the three TFTs shown in FIG. 1 will be described as an example.

In this embodiment, as shown in FIG. 5A, after the gate insulating film 14 and the gate electrode 15 are sequentially formed, the conductive coating film forming step described with reference to FIG. Before, as shown in FIG.
5 is used as a mask to perform a gate insulating film etching step of etching the gate insulating film 14. And FIG.
As shown in (c), a coated ITO film 41 (conductive coating film) is formed on the surface side of the gate electrode 15, that is, on the entire surface of the insulating substrate 2 (conductive coating film forming step). High concentration impurities are introduced (high concentration impurity introduction step). As a result, the source region 11 and the drain region 12 having the LDD structure or the offset gate structure can be formed on the silicon thin film 11a. After that, as shown in FIG. 5D, the applied ITO film 41 is removed (a conductive applied film removing step), and the interlayer insulating film 4 is formed.

As described above, when the impurity is introduced in the high-concentration impurity introduction step, the thickness of the film serving as a barrier for impurity introduction into the silicon thin film 11a at a position distant from the periphery of the gate electrode 15 has a predetermined difference. If the gate insulating film 14 is present there, since the thickness of the gate insulating film 14 is constant regardless of the location, the film serving as the barrier must be formed as a whole thicker. . However, in the present embodiment, the gate insulating film 14 does not exist on the surface side of the silicon thin film 11a except for the portion immediately below the gate electrode 15. Therefore, at the time of introducing the impurity, when trying to make a predetermined difference in the thickness of the film to be a barrier for introducing the impurity into the silicon thin film 11a at a position distant from the periphery of the gate electrode 15, the above-mentioned film is formed. The difference in thickness can be defined only by the applied ITO film 41. Therefore, since the film thickness can be reduced at a position distant from the gate electrode 15, energy for introducing impurities can be reduced. For example, if impurity ions are introduced through a film thickness of about 2000 angstroms, ¹¹ B ⁺
If it is 70 keV or more, if it is ³¹ P ⁺ , it is 200 k
Although energy of eV or more is required, as in this embodiment, if impurity ions are introduced through a film thickness of about 1000 angstroms, then 30 B is required for ¹¹ B ^+.
With 40 keV and ³¹ P ⁺ , energy of 80 to 100 keV is sufficient.

Third Embodiment As shown in FIG. 6A, after the gate insulating film 14 and the gate electrode 15 are sequentially formed, the conductive coating film described with reference to FIG. Before performing the forming step, as shown in FIG. 6B, after etching the gate insulating film 14 using the gate electrode 15 as a mask (gate insulating film etching step), FIG.
As shown in (c), an insulating coating film 49 (SOG) made of a silicon oxide film is formed on the surface side of the gate electrode 15, that is, on the entire surface of the insulating substrate 2 (insulating coating film forming step). Subsequently, a coating ITO film 41 (conductive coating film) may be formed by coating (conductive coating film forming step). Here, the sum of the thickness of the insulating coating film 49 and the thickness of the coating ITO film 41 is, for example, about 1000 angstroms.
Even when a high concentration impurity is introduced in this state (a high concentration impurity introduction step), the source region 11 having the LDD structure or the offset gate structure is formed in the silicon thin film 11a.
And the drain region 12 can be formed. After a while
As shown in FIG. 6D, the applied ITO film 41 is removed (conductive coating film removing step), and the interlayer insulating film 4 is formed on the surface side of the insulating coating film 49.

In the case of such a configuration, since the coating film (insulating coating film) is just below the coating ITO film 41, the thick coating film around the gate electrode 15 is used as described above. Thus, the amount of impurities introduced into this portion can be suppressed. Further, in the gate insulating film etching step shown in FIG. 6B, when the gate insulating film 14 is etched, the gate insulating film 1 immediately below the gate electrode 15 is removed.
The insulating coating film 49 can prevent the overhang structure from being formed even when the layer 4 is overetched.
Also in this case, the impurity is introduced because the gate insulating film 14 is not present on the surface side of the silicon thin film 11 a except immediately below the gate electrode 15, and the film thickness can be reduced at a position away from the gate electrode 15. Energy is small.

[Embodiment 4] Further, as shown in FIG. 7A, after the gate insulating film 14 and the gate electrode 15 are sequentially formed, the conductive coating film described with reference to FIG. Before performing the formation process, a mask 58 that covers the gate electrode 15 in a wide area may be formed, and the gate insulating film 14 may be etched using the mask 58 as shown in FIG. Film etching step). With this configuration, it is possible to suppress the amount of impurities introduced into this portion by utilizing the gate insulating film 14 remaining around the gate electrode 15 and the thick ITO film 41 formed around the gate electrode 15. Therefore, the silicon thin film 11a has:
The source region 11 and the drain region 12 having the LDD structure or the offset gate structure can be formed. After that, as shown in FIG. 7D, the applied ITO film 41 is removed (conductive coating film removing step), and the interlayer insulating film 4 is formed.

[Other Embodiments] First Embodiment
In order to prevent the charge-up occurring in the two impurity introduction steps performed in
Has been described as utilizing the conductivity of FIG.
As shown in the figure, the substrate holder 6 set to the ground potential
If the insulating substrate 2 is held from above and below at 0, the coated ITO film 41 formed on the entire surface of the insulating substrate 2 is electrically connected to the substrate holder 60. In a typical ion implantation apparatus, the insulating substrate 2 is set on a platen, and the insulating substrate 2 is fixed on the platen by a guard ring or a substrate holder that presses part or all of the outer periphery of the substrate. I have. Therefore, the applied ITO film 41 formed on the entire surface of the substrate has a structure that is electrically connected to the guard ring or the substrate holder. As a result, the applied ITO film 41 is forcibly maintained at the ground potential, so that charge-up when introducing impurity ions can be more reliably prevented.

In the above embodiment, the coated ITO film 41 is used as the conductive coating film. However, it can be formed on the surface side of the gate electrodes 15, 25, 35 by a coating film forming method.
As long as the film has conductivity, another conductive inorganic material or a conductive polymer such as polyacetylene may be used.

Further, in the above embodiment, the LDD region (low-concentration source / drain region) is formed in the source / drain region. However, when the amount of impurities introduced into the LDD region is extremely small, the offset region is formed. Can be considered to be done. That is, the T of the offset gate structure
FT can be manufactured.

The impurity ions are introduced by an ion doping method of implanting a hydrogen compound and hydrogen as an impurity element to be implanted by using a mass non-separation type ion implantation apparatus, or by using a mass separation type ion implantation apparatus. For example, an ion implantation method of implanting only impurity ions can be applied. Source gases for the ion doping method include phosphine (PH ₃ ) and diborane (B
_A hydride of an implanted impurity such as ₂ H ₆ ) is used. In addition, as a method for introducing impurities, a plasma doping method, a laser doping method, or the like can be used.

The TFT according to the present embodiment and the CMOS circuit constituted by the TFT include, in addition to the liquid crystal display device, a display device using a thin film electroluminescent element (thin film light emitting element), a contact type image sensor, SRAM (static Random Acces)
s Memories).

[0062]

As described above, in the method of manufacturing a thin film transistor according to the present invention, after forming a gate electrode, a conductive coating film is formed only on the surface side, and a sidewall is formed at an end of the gate electrode. It will be in the same state as formed. Therefore, only by introducing impurity ions in this state, the portion of the source / drain region facing the end of the gate electrode is filled with impurity due to the thickness of the conductive coating film formed thereon. The amount of introduced ions is considerably small. As a result, LDD regions and offset regions are automatically formed in the source / drain regions. Therefore, unlike a method in which a high concentration of impurity ions are prevented from being introduced into the LDD region and the offset region by using a resist mask that covers the gate electrode slightly wider, the number of steps for forming the resist mask is reduced, and the substrate is formed. Even if the size is increased, variations in LDD length and offset length due to mask alignment accuracy do not occur. Further, when the impurity ions are implanted, the surface thereof is covered with the conductive coating film, so that the charge up to the gate insulating film and the like does not occur. Therefore, it is possible to prevent the gate insulating film and the like from being damaged when the impurity ions are introduced.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view schematically showing an active matrix substrate on which three types of thin film transistors are formed.

FIG. 2A is an explanatory diagram of an active matrix substrate of a liquid crystal display device, and FIG. 2B is a diagram illustrating a CM used in a driving circuit thereof.
FIG. 3 is an explanatory diagram of an OS circuit.

FIGS. 3A to 3D are process cross-sectional views showing a process up to a gate electrode forming process in the method for manufacturing an active matrix substrate according to the first embodiment of the present invention;

FIGS. 4A to 4D are process cross-sectional views showing processes after the process of forming the gate electrode shown in FIG. 3;

FIGS. 5A to 5D are process cross-sectional views showing processes after a process of forming a gate electrode in the method of manufacturing an active matrix substrate according to the second embodiment of the present invention.

6 (a) to 6 (d) are cross-sectional views showing steps after a step of forming a gate electrode in the method of manufacturing an active matrix substrate according to Embodiment 3 of the present invention.

FIGS. 7A to 7D are process cross-sectional views showing a process after a process of forming a gate electrode in a method of manufacturing an active matrix substrate according to a fourth embodiment of the present invention.

FIG. 8 is an explanatory diagram showing a state in which the substrate holder set to the ground potential holds the substrate in the impurity introduction step performed in FIGS. 4B and 4C.

FIG. 9 is a graph showing transfer characteristics of a thin film transistor having a self-aligned structure.

FIG. 10 is a graph showing transfer characteristics of a thin film transistor having an LDD structure.

FIG. 11 is a process cross-sectional view showing a process after a process of forming a gate electrode in the conventional method of manufacturing an active matrix substrate.

[Explanation of symbols]

 Reference Signs List 1 active matrix substrate 2 insulating substrate 10 N-type pixel TFT 20 N-type drive circuit TFT 30 P-type drive circuit TFT 11, 21, 31 Source regions 12, 22, 32 Drain regions 13, 23, 33 channels Forming area 14, 24, 34 Gate insulating film 15, 25, 35 Gate electrode 41 Coated ITO film (conductive coating film) 60 Substrate holder 82 Data driver unit (drive circuit) 83 Scan driver unit (drive circuit) 90 Data line 91 Scan lines 111, 211, 311 Low concentration source region 121, 221, 321 Low concentration drain region

Claims (10)

[Claims] 1. A conductive coating method comprising: forming a semiconductor film on a substrate; sequentially forming a gate insulating film and a gate electrode on the surface of the semiconductor film; and forming a conductive coating film on the surface side of the gate electrode. A film forming step, an impurity introducing step of introducing impurity ions into the semiconductor film from the surface side of the conductive coating film to form source / drain regions, and a conductive coating film removing step of removing the conductive coating film And a step of forming an interlayer insulating film on the surface of the gate electrode after removing the conductive coating film. 2. The conductive coating film forming step according to claim 1, wherein in the conductive coating film forming step, a liquid coating material containing a precursor of the conductive coating film is applied over the entire surface of the substrate by spin coating, and then heat treatment is performed. A method for producing a thin film transistor, wherein the precursor is made conductive by heating. 3. The method for manufacturing a thin film transistor according to claim 1, wherein an ITO film is formed as the conductive coating film. 4. The method according to claim 1, wherein
The conductive coating film has a sheet resistance of 10 ⁷ Ω / □.
A method for manufacturing a thin film transistor, comprising forming the following conductive film. 5. The method according to claim 1, wherein
After sequentially forming the gate insulating film and the gate electrode, a gate insulating film etching step of etching the gate insulating film using the gate electrode as a mask is performed before performing the conductive coating film forming step. Manufacturing method of a thin film transistor. 6. An insulating coating according to claim 5, wherein after the gate insulating film etching step is performed and before the conductive coating film forming step is performed, an insulating coating film is formed on the surface side of the gate electrode. A method for manufacturing a thin film transistor, comprising performing a film forming step. 7. The method according to claim 1, wherein
After the gate insulating film and the gate electrode are sequentially formed, before performing the conductive coating film forming step, a mask that widely covers the gate electrode is formed, and the gate insulating film is etched using the mask. A method for manufacturing a thin film transistor, wherein a gate insulating film etching step is performed. 8. The method according to claim 1, wherein
In the method of manufacturing a thin film transistor, in the impurity introducing step, impurity ions are introduced while the conductive coating film is kept at a ground potential. 9. The conductive coating film according to claim 8, wherein said conductive coating film is held at a ground potential in said impurity introducing step so that a substrate holder set at a ground potential and said conductive coating film are in contact with each other. A method for manufacturing a thin film transistor, comprising: 10. A thin film transistor for a driving circuit for forming a driving circuit is formed on the substrate by using the method of manufacturing a thin film transistor according to claim 1. A method for manufacturing an active matrix substrate for a liquid crystal display device, comprising forming a pixel switching thin film transistor in a region.