JPH10308072A - Medium for recording and reproducing information, medium format device for recording and reproducing information and information recording and reproducing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent erroneous detection for an address mark caused by a reproduced pattern from a region in which a synchronizing pattern where a defective bit is included is recorded by recording a prescribed pattern as the address mark in which patterns of even numbers in which a symbol 1 appears are arranged for every specific channel bit in a region in which the address mark is recorded in a header region. SOLUTION: An address mark has the length of 48 channel bits and is constituted with patterns of which the run length of a symbol 0 is 13. The run length of a symbol 0 in the pattern of this address mark is arranged in order from the front as 3, 3, 13, 3, 3, 13, 3, and the patterns including a symbol 1 being '3, 3, 13' of odd numbers are repeated twice. Thus, it can be prevented that the other pattern is erroneously detected as the address mark by including the pattern in which the run length of the symbol 0 is 13 and which is not included in a run length limit (2, 10) code.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information recording / reproducing medium (optical disc) on which information can be recorded and reproduced by a laser beam, and an information recording / reproducing medium for applying a predetermined format to the information recording / reproducing medium. The present invention relates to a medium format device and an information recording / reproducing device for recording and reproducing data on and from the information recording / reproducing medium.

[0002]

2. Description of the Related Art An optical disc on which data can be recorded and reproduced by a laser beam is provided with concentric or spiral tracks and a plurality of sector areas each having a predetermined track length. The sector area includes a header area in which data is recorded by embossed pits, and a recording area in which data is recorded using a phase change. In addition, this header area contains
VFO (Voltage Frequency Oscillator) area, AM
(Address Mark) area, PID (Physical ID) area, and the like.

[0003] Address information is recorded in the PID area. In the AM area, an address mark that plays a role of detecting a block boundary when demodulating a fixed-length block code is recorded. Specifically, the address mark recorded in the AM area indicates the position of the address information recorded in the PID area. PLL in the VFO area
A synchronization pattern having a constant period serving as a pull-in area is recorded. More specifically, the synchronization pattern recorded in the VFO area is for synchronizing the frequency for reproducing the address information recorded in the PID area.

In such an optical disc, a bit information sequence (binary data) composed of "0" and "1" is used by using a code sequence composed of run-length limited codes except for a specific region (such as an AM region). Is recorded. In the bit information sequence consisting of “0” and “1”, the continuation of the same bit is called a run. In the run-length limited code, the continuation of “1” does not occur, and the run-length of “0” between “1” and “1” is limited to, for example, 2 or more and 10 or less. Such a run-length limit is abbreviated as RLL (2, 10) or the like. Incidentally, RLL is an abbreviation for Run Length Limited.

[0005] A fixed-length block code is used for coding data recorded in a recording area of an optical disk. The fixed-length block code refers to a code form in which coding is performed with a fixed value such as a code word-to-data word ratio of, for example, 2: 1. When demodulating the fixed-length block code, if the block boundaries are incorrect, correct demodulation cannot be performed.
Therefore, the AM provided at the front of the encoded data
An address mark is recorded in the area, and at the time of data reproduction, a correct block boundary is detected by this address mark and demodulation is performed. If a recorded portion of data that is not an address mark is erroneously determined as an address mark, subsequent data will not be correctly demodulated.

Incidentally, in the edge recording method, the NRZI (Non-Non-Inverting Mode) in which the polarity is inverted at the position of "1" in the channel bit string is used.
Return to Zero Inverted) operation is performed.

[0007]

The synchronous pattern recorded in the above-mentioned VFO area may include defective pits. However, the VFO containing this defective pit
Address marks may be erroneously detected due to a reproduced pattern affected by the defective pits obtained by reproducing the area.

(1) A first object of the present invention is to reproduce a VFO area containing a defective pit, which is affected by a defective pit obtained when the VFO area contains the defective pit. An object of the present invention is to provide an information recording / reproducing medium which can contribute to prevention of erroneous detection of an address mark by a pattern.

(2) A second object of the present invention is to provide, when a defective pit is included in a VFO region, a reproduction affected by a defective pit obtained by reproducing the VFO region including the defective pit. An object of the present invention is to provide an information recording / reproducing medium formatting device for formatting an information recording / reproducing medium that can contribute to preventing erroneous detection of an address mark by a pattern.

(3) A third object of the present invention is to reproduce a VFO area containing a defective pit, which is affected by a defective pit obtained when the VFO area contains the defective pit. An object of the present invention is to provide an information recording / reproducing apparatus which can prevent erroneous detection of an address mark due to a pattern.

[0011]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems and achieve the object, an information recording / reproducing medium, an information recording / reproducing medium format device, and an information recording / reproducing device of the present invention are configured as follows. ing.

The present invention has a concentric or spiral track, a plurality of sector areas having a predetermined track length, the sector area has a header area and a recording area, and the header area has an address. A first area in which information is recorded, a second area in which an address mark indicating the position of the address information is recorded, and a pattern subjected to a predetermined run-length restriction for reproducing the address information. In an information recording / reproducing medium having a third area in which a synchronization pattern for achieving frequency synchronization is recorded, a synchronization pattern having a constant period composed of 3 run lengths of symbol 0 with channel bits is written in the third area. And a pattern composed of 22 channel bits, the fourth channel bit, the eighth channel bit, and the 22 channel bit. Nerubitto th symbol 1 appears in the pattern is one that was recorded in the second region as an address mark specific pattern that is an even number arranged.

The present invention has a concentric or spiral track, a plurality of sector areas having a predetermined track length, the sector area has a header area and a recording area, and the header area has an address. A first area in which information is recorded, a second area in which an address mark indicating the position of the address information is recorded, and a pattern subjected to a predetermined run-length restriction for reproducing the address information. In an information recording / reproducing medium formatting device for formatting an information recording / reproducing medium so as to have a third area in which a synchronization pattern for frequency synchronization is recorded, a run length of symbol 0 is set to 3 by a channel bit. A synchronization pattern having a constant period is formatted in the third area, and a pattern composed of 22 channel bits is formed. A down, 4 channel bit,
Formatting means is provided for formatting the second area as a specific pattern in which an even number of patterns in which the symbol 1 appears at the 8th channel bit and the 22nd channel bit are arranged as address marks.

The present invention has a concentric or spiral track, a plurality of sector areas having a predetermined track length, the sector area has a header area and a recording area, and the header area has an address. A first area in which information is recorded, a second area in which an address mark indicating the position of the address information is recorded, and a pattern subjected to a predetermined run-length restriction for reproducing the address information. In an information recording / reproducing apparatus for recording and reproducing information on and from an information recording / reproducing medium having a third area in which a synchronization pattern for frequency synchronization is recorded, a symbol 0 has a run length of 3 with channel bits. The third area in which the synchronization pattern having a fixed period is recorded is reproduced, and a pattern composed of 22 channel bits is reproduced. I, 4-channel bit symbol to an 8-channel bit, and 22-channel bit 1
Address mark detection means for reproducing the second area in which a specific pattern in which an even number of patterns appearing is recorded as an address mark, and detecting an address mark from a reproduction pattern obtained by this reproduction; An information recording / reproducing means for recording / reproducing information in accordance with the address mark detected by the detecting means.

[0015]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram schematically showing a sector area provided on an optical disc as an information recording / reproducing medium according to an embodiment of the present invention.

The optical disk 1 is formed by, for example, coating a metal film layer of tellurium or bismuth in a donut shape on the surface of a substrate formed in a circle of glass or plastics. The optical disk is provided with concentric or spiral tracks (land tracks and groove tracks). Further, these tracks are provided with a plurality of sector areas each having a predetermined track length.

Here, a schematic configuration of the sector area will be described with reference to FIG.

As shown in FIG. 1, one sector is approximately 26
It consists of 97 bytes, 128 bytes of header area, 2
It consists of a byte mirror area and a 2567 byte recording area. Header area and mirror area are recorded as irregularities before shipment (pre-format)
It is the part that is done. The recording area only has lands and grooves. The channel bits recorded in the sector area (excluding the address mark AM area described later) have a format in which 8-bit data is modulated into 16-bit channel bits by 8-16 code. This 8-16 code modulation is based on RLL (2, 1
0) Sign.

In the header area, predetermined data is recorded when the optical disc 1 is manufactured. This header area is 4
It consists of two areas, namely, a header 1 area, a header 2 area, a header 3 area, and a header 4 area. The header 1 area and the header 3 area have 46 bytes, and the header 2 area and the header 4 area have 18 bytes.

The header 1 area and the header 3 area have a 36-byte synchronization code VFO (Variable Frequency Oscillat).
or) 1 area, 3 byte address mark AM (Address
Mark) area, 4-byte address PID (Physical ID)
) Area, 2-byte error detection code IED (ID Error
Detection Code) area, 1-byte postamble PA
(Post Ambles) area. On the other hand, the header 2 area and the header 4 area include an 8-byte synchronization code VFO 2 area, a 3-byte address mark AM area,
It is composed of a byte address PID area, a 2-byte error detection code IED area, and a 1-byte postamble PA area.

Address information is recorded in the PID area. Specifically, sector information (including a PID number) of 1 byte and a sector number of 3 bytes are recorded.

In the synchronization code VFO1 area and VFO2 area, a continuous repetition pattern (1000100010) for pulling in a PLL (Phase Locked Loop) is provided.
00 ...) is recorded. Specifically, this VFO
The pattern recorded in the area is for synchronizing the frequency for reproducing the address information recorded in the PID area.

An address mark is recorded in the AM area,
The address mark plays a role of detecting a block boundary when demodulating a fixed-length block code. Specifically, the address mark recorded in the AM area is a PI
This indicates the position of the address information recorded in the D area. A special pattern not appearing elsewhere is used for the address mark recorded in the AM area. The pattern of the address mark recorded in the AM area is a feature of the present invention, and the pattern is, for example, a specific pattern as shown in FIG. 2 (channel bit: 000100)
01000000000000000001000100010
000000000000010001).

The address mark has a length of 48 channel bits and is composed of a pattern (10000000000000000) in which the run length of symbol 0 is 13. In the RLL (2, 10) code, there is no pattern in which the run length of symbol 0 is 13. That is,
By including a pattern in which the run length of symbol 0 is 13 in the address mark, it is possible to prevent another pattern from being erroneously detected as the address mark.

The run length of the symbol 0 in the pattern of the address mark, which is a feature of the present invention, is 3, 3, 13, 3, 3, 13, 3 in order from the front. 3, 13 ", a pattern including an odd number of symbols 1 (00010001000000000000
1) is repeated an even number of times (for example, twice). As a result, the DC component is canceled. Incidentally, the address mark has a VFO adjacent to a pattern (10000000000000000) in which the run length of symbol 0 is 13.
The pattern (1) that constitutes the synchronization pattern recorded in the area
000) is arranged.

In the error detection code IED area, an error (error) detection code for a sector address (including an ID number) is recorded, and the presence or absence of an error in the PID read by this error detection code is detected.

State information necessary for demodulation is recorded in the postamble PA1 area and the PA2 area, and also has a role of polarity adjustment so that the header area ends with a space.

The mirror area is used for offset correction of a tracking error signal, timing generation of a land / groove switching signal, and the like.

The recording area is (10 + J / 1)
6) Gap area of byte, guard 1 area of (20 + K) bytes, VFO3 area of 35 bytes, PS of 3 bytes
(Pre-synchronous code) area, 2418-byte data area, 1-byte postamble PA3 area, (55
-K) Guard 2 area of bytes, and (25-J / 1)
6) It is composed of a byte buffer area. Incidentally, J takes an integer of 0 to 15 and K takes an integer of 0 to 7 and takes a random value.

The gap area is an area where nothing is recorded.

The guard 1 area is an area provided to prevent the terminal deterioration at the time of repetitive recording peculiar to the phase change recording medium from reaching the VFO3 area.

The VFO3 area is also an area for PLL lock, but is also an area for inserting a synchronization code in the same pattern to synchronize byte boundaries.

The PS area is a tuning area for connecting to the data area.

The data area includes a data ID and a data ID error correction code IED (Data ID Error Detection Code).
e), synchronization code, ECC (Error Collection Code)
), An EDC (Error Detection Code), user data, and the like. The data ID is a sector ID 1 of 4 bytes (32 channel bits) of each sector.
~ ID16. Data ID error correction code IED
Is a 2-byte (16-bit) error correction code for data ID.

The postamble PA3 area contains state information necessary for demodulation, and indicates the end of the last byte of the previous data area.

The guard 2 area is an area provided in order to prevent the end deterioration at the time of repetitive recording peculiar to the phase change recording medium from reaching the data area.

The buffer area is an area provided for absorbing rotation fluctuation of the motor for rotating the optical disk 1 so that the data area does not overlap the next header area.

Next, an example of erroneous detection of a VFO pattern recorded in the VFO area will be described with reference to FIG. In the VFO area, “100” is displayed in channel bit display.
A pattern in which "0" is repeated is recorded. Such a pattern has a period of 4T when the period is represented by a channel clock period T.
Therefore, it is also called a 4T pattern or the like. The recording pit is formed such that the position corresponding to the symbol 1 of the channel bit becomes a fulcrum or an end point. In FIG.
The pit shall be represented by an oval figure.

FIG. 3A shows a state in which a normally recorded VFO pattern is normally detected. The reproduced signal obtained from the pit train has a waveform as shown by the solid line at the interruption. This reproduced signal is converted into a binarized signal at the binarized level shown by the dotted line. This binary signal is called a binary signal. The binarization level is determined, for example, by calculating a DSV (Digital Sum Value) from the duty of the binarization signal and performing feedback control using the calculated value as a deviation. The edge of the binarized signal corresponds to symbol 1 of the reproduced bit string.

FIG. 3 (b) shows the V that was not recorded normally.
It is a figure showing the state where the FO pattern was detected. The VFO pattern that has not been recorded normally is, for example, a VFO pattern including pits with insufficient unevenness. The pits with insufficient ruggedness are indicated by hatching in the figure. Such a phenomenon that pits with insufficient unevenness are formed is, for example, that the resin is insufficiently filled during mastering, a pit unit defect exists on the disk substrate for some reason, This can be caused by dust adhering to the surface. Hereinafter, the shaded pit is referred to as a defective pit.

In the case of a defective pit, the depth of the pit (when the pit is considered to be concave) has not reached λ / 4 at which the maximum change in reflectivity is theoretically obtained, and the reproduced signal is not detected at the defective pit position. It does not drop enough. Here, λ is a laser wavelength, for example, a value such as 650 [nm]. In such a case, the defective pit is not recognized as a pit. As a result, a 12T pattern that does not occur in the RLL (2, 10) code as shown in FIG. 3B is detected.

The address mark recorded in the AM area is
A pattern (100000000000000000) that violates the run-length restriction code is distinguished from other patterns.
0) is used. More specifically, even a pattern violating the run-length limit code has a larger run-length (a pattern exceeding the run-length limit).
Is used.

When an area including a defective pit is reproduced, it is impossible to prevent an erroneous reproduced signal from being obtained. The address mark recorded in the address mark AM area has a role of detecting a block boundary. This address mark is arranged at the head of a data recording area where demodulation is required and is a pull-in area of a PLL. It is located immediately after the VFO area. That is, a VFO pattern is always recorded at the front of the address mark, and when a defective pit occurs in this VFO pattern, a pattern violating a specific run-length restriction code often occurs. This is a point significantly different from the case where a defective pit occurs in arbitrary data.

In the present invention, erroneous detection of the address mark is prevented by utilizing this fact. That is, when a defective pit that is not recognized as a pit is included in the VFO area, a pattern different from the reproduction pattern affected by the defective pit is adopted as an address mark recorded in the AM area. This can prevent the address marks from being erroneously detected due to the reproduction pattern affected by the defective pits. An example of the address mark pattern is a specific pattern shown in FIG.

The specific pattern shown in FIG.
Pattern with a run length of 13 (1,000,000
00000000). This pattern never appears in a reproduced pattern affected by defective pits as shown in FIG. Of course, this pattern does not appear in a reproduced pattern affected by a plurality of defective pits.

FIG. 3 (c) shows the V that was not recorded normally.
It is a figure showing the state where FO pattern was erroneously detected. The VFO pattern that has not been recorded normally is a pattern including defective pits as described above. In addition, the erroneous detection referred to here is a state detected by a binarized level shifted for some reason. The binarized repel may deviate from the amplitude center of the reproduced signal in the VFO region if there is a large defect or the like.

FIG. 3C shows a case where the binarized level shifts to a lower level with respect to the reproduced signal. In this case, the defective pit portion is detected as a violation pattern (the run length of symbol 0 is 13) whose run length is larger by 2 bits than in FIG. in this case,
This violation pattern becomes the same as the pattern exceeding the run-length limit included in the specific pattern shown in FIG.

However, the specific pattern shown in FIG. 2 includes a pattern (10) constituting a VFO pattern recorded in the VFO area adjacent to a pattern exceeding the run length limit.
00) are always different from the reproduction pattern reproduced by the shifted binarization level as shown in FIG. Thus, by employing the code pattern shown in FIG. 2 as an address mark, erroneous detection of the address mark can be prevented even when the pattern shown in FIG. 3C is reproduced.

Next, the DSV of the specific pattern shown in FIG. 2 will be described with reference to FIG. FIG. 4 shows a change in DSV of a pattern obtained by repeating an odd pattern twice. The odd pattern is a pattern including an odd number of symbols 1 in the pattern, and the polarity of the start point and the end point is reversed when performing NRZI conversion. In FIG. 4, what is called an odd pattern is a pattern of 4T-14T-4T, which is an odd pattern including three symbols 1 (the pattern shown in FIG. 2).

The upper part of FIG. 4 shows an example of a specific pattern of an address mark having a total length of 48 channel bits. The high level of the binary waveform corresponds to a space, and the low level corresponds to a pit. At the top of the binary waveform, the length of each pit or space is represented using the channel bit period T. The channel bit expression of the address mark shown in FIG. 4 is 00010001000000000000
00100010001000000000000001
0001. The lower part of FIG. 4 shows a change in DSV value for each bit in the above pattern. 2 odd patterns
Since it is repeated several times, the shape of the change is symmetrical and ends up with a value close to zero in the end. Repeating the odd pattern even number of times cancels each other's DSV, resulting in such a result. When a violation mark having a large run length is used as an address mark in order to prevent erroneous detection in the run length limit code, a pattern in which an odd number pattern is repeated an even number of times to suppress a DC component is employed as an address mark. This is a very effective means from the viewpoint that can be simplified.

Here, the pattern of the address mark of the present invention will be strictly described. The pattern shown in FIG. 2 is only an example of the specific pattern of the present invention. The specific pattern of the present invention can be expressed as follows.

Symbol 0 of VFO pattern in VFO area
Is the upper limit value of the run length of the symbol 0, the specific pattern of the present invention is a run length n of symbol 0 (n> m, n
≠ rm + (r−1), where r is a natural number). Further, a pattern having a run length m of symbol 0 is arranged adjacent to a pattern satisfying the run length n of symbol 0. Further, this pattern is a pattern obtained by repeating a pattern including an odd number of symbols 1 an even number of times.

The case where m = 3, n = 13 and r = 3 is satisfied is the specific pattern shown in FIG.

Next, with reference to FIG. 5, an outline of the master recording apparatus for recording the above-described specific pattern of the address mark of the present invention on the master will be described.

In the master recording apparatus shown in FIG. 5, a laser beam (for example, an Ar laser or a Kr laser) emitted from a laser light source 41 enters a laser optical axis control system 42 for adjusting the optical axis, and the temperature of the laser beam is adjusted. The optical axis fluctuation due to the change is dealt with. The laser light is reflected by the mirror 43,
The beam is modulated into a laser beam having an arbitrary signal (address mark of the present invention) by a beam modulation system 44 including E / O modulators 44a and 44b controlled by a format circuit 49 as a format means. Here, the laser beam can be modulated into a predetermined format signal (specific pattern of the address mark of the present invention). The format circuit 49 controls the beam modulation system 44 so as to modulate the laser light according to a cutting operation described later. The laser beam passes through a beam shaping system 45 composed of pinholes and slits, and the beam diameter and shape are adjusted.
The adjustment of the laser beam is completed up to here, and the beam monitor system 4
At 6, the beam shape can be confirmed.

The laser light is further guided by the mirror 47 and focused and irradiated on the optical recording master 40 by the objective lens 48. As the optical recording master 40, for example, a glass disk is used. A photosensitive paint (photoresist) is applied on the glass disk, and the surface of the photosensitive paint is irradiated with laser light. The portion exposed by the laser beam becomes concave when etched. The surface shape formed by this laser light irradiation is made into a desired uneven shape, and a groove and a format pattern are recorded. A stamper is manufactured based on the glass disk thus processed.

At the time of cutting, rotating means 3 such as a motor
In step 9, the glass disk 40 is rotated, for example, at a constant speed. Further, an optical pickup having an objective lens 48 for irradiating a predetermined position on the glass disk 40 with laser light moves at a constant speed from the inner peripheral side to the outer peripheral side of the crow disk 40. At the time of cutting, the optical pickup moves at a constant speed from the inner peripheral side to the outer peripheral side on a splitter corresponding to the track pitch per one rotation of the disk, and moves the irradiation position of the laser light with this movement. Due to the optical pickup moving in this way, the portion irradiated with the laser beam becomes a group, and the portion not irradiated becomes a land. In the header region, uneven pits are formed by blinking a laser beam.

Next, with reference to FIG. 6, an outline of an optical disk apparatus as an information recording / reproducing apparatus for recording and reproducing data on and from the optical disk on which the code pattern of the address mark AM described above is recorded according to the present invention will be described. I do.

The optical disk apparatus shown in FIG. 6 records data on the optical disk 1 using focused light, or reproduces recorded data. Optical disk 1
Is rotated by the motor 3 at a different rotation speed for each zone, for example. The motor 3 is controlled by a motor control circuit 4. Recording data on the optical disc 1,
Reproduction is performed by the optical head 5 as information recording / reproduction means. The optical head 5 is fixed to a drive coil 7 constituting a movable part of a linear motor 6, and the drive coil 7 is connected to a linear motor control circuit 8.

A speed detector 9 is connected to the linear motor control circuit 8, and the optical head 5 detected by the speed detector 9
Is sent to the linear motor control circuit 8. A permanent magnet (not shown) is provided at a fixed portion of the linear motor 6. When the drive coil 7 is excited by the linear motor control circuit 8, the optical head 5 is moved in the radial direction of the optical disc 1.

The optical head 5 is provided with an objective lens 10 supported by a wire or a leaf spring (not shown). The objective lens 10 can be moved in the focusing direction (the direction of the optical axis of the lens) by driving the drive coil 11, and can be moved in the tracking direction (the direction orthogonal to the optical axis of the lens) by driving the drive coil 12. Is possible.

A laser light beam is emitted from the semiconductor laser oscillator 9 by the drive control of the laser control circuit 13.
The laser control circuit 13 includes a modulation circuit 14 and a laser drive circuit 15, and operates in synchronization with a recording clock signal supplied from the PLL circuit 16. The modulation circuit 14 modulates the recording data supplied from the error correction circuit 32 into a signal suitable for recording, that is, 8-16 modulated data. The laser drive circuit 15 drives a semiconductor laser oscillator (or an argon-neon laser oscillator) 19 according to the 8-16 modulation data from the modulation circuit 14.

The PLL circuit 16 stores the crystal oscillator 1 during recording.
7 is divided by a dividing value set by the CPU 30 or divided by a frequency corresponding to a time interval (header interval) at which a header area on the optical disk 1 is reproduced, thereby obtaining a recording signal. A clock signal is generated, and at the time of reproduction, a reproduction clock signal corresponding to the reproduced synchronization code is generated. Also, PL
The L circuit 16 selectively outputs a recording or reproduction clock signal according to a control signal from the CPU 30 and a signal from the binarization circuit 41 of the data reproduction circuit 18 as information recording / reproduction means.

The laser beam emitted from the semiconductor laser oscillator 19 is irradiated on the optical disk 1 via the collimator lens 20, the half prism 21, and the objective lens 10. The reflected light from the optical disc 1
0, a half prism 21, a condenser lens 22, and a cylindrical lens 23, and are guided to a photodetector 24.

The photodetector 24 is a four-divided photodetector cell 24.
a, 24b, 24c, and 24d. The output signal of the photodetector cell 24a is supplied to one end of the adder 26a via the amplifier 25a. The output signal of the light detection cell 24b is supplied to one end of an adder 26b via an amplifier 25b. The output signal of the light detection cell 24c is
5c is supplied to the other end of the adder 26a. The output signal of the light detection cell 24d is supplied to the other end of the adder 26b via the amplifier 25d.

Further, the output signal of the light detection cell 24a is
The signal is supplied to one end of the adder 26c via the amplifier 25a. The output signal of the light detection cell 24b is supplied to one end of an adder 26d via an amplifier 25b. Photodetection cell 24
The output signal of c is supplied to the other end of the adder 26d via the amplifier 25c. The output signal of the light detection cell 24d is supplied to the other end of the adder 26c via the amplifier 25d.

The output signal of the adder 26a is a differential amplifier OP
2, and the output signal of the adder 26b is supplied to the non-inverting input terminal of the differential amplifier OP. The differential amplifier OP2 outputs a signal related to the focus point according to the difference between the two output signals of the adders 26a and 26b. This output is supplied to the focusing control circuit 27. The output signal of the focusing control circuit 27 is supplied to the focusing drive coil 12. Thus, the laser light beam is controlled to be always just focused on the optical disc 1.

The output signal of the adder 26c is the differential amplifier OP
1, and the output signal of the adder 26d is supplied to the non-inverting input terminal of the differential amplifier OP1. The differential amplifier OP1 outputs a track difference signal according to the difference between the two output signals of the adders 26c and 26d. This output is supplied to the tracking control circuit 28. The tracking control circuit 28 creates a track drive signal according to the track difference signal from the differential amplifier OP1.

The track driving signal output from the tracking control circuit 28 is
1 is supplied. Further, a track difference signal used in the tracking control circuit 28 is supplied to the linear motor control circuit 8.

By performing the focusing and tracking, each of the light detection cells 24a,
... the sum signal of the output signals of 24d,
The change in the reflectance from the pits (recording data) formed on the track is reflected in the output signal of the adder 26e, which is the addition of the two output signals c and 26d. This signal is supplied to the data reproducing circuit 18. Data reproduction circuit 18
Reproduces recorded data based on a reproduction clock signal from the PLL circuit 16.

The data reproducing circuit 18 has an adder 26
e, the sector mark SM in the preformat data is detected based on the output signal of e and the reproduction clock signal from the PLL circuit 16, and based on the binarized signal and the reproduction clock signal supplied from the PLL circuit 16, A PID area (track number and sector number) as address information is reproduced from the binarized signal.

The reproduced data of the data reproducing circuit 18 is
9 is supplied to the error correction circuit 32. The error correction circuit 32 outputs an error correction code (EC
C) to correct the error, or add an error correction code (ECC) to the recording data supplied from the interface circuit 35 and output it to the memory 2.

The reproduced data whose error is corrected by the error correction circuit 32 is transmitted to the bus 29 and the interface circuit 3.
5 is supplied to an optical disk control device 36 as an external device. The recording data emitted from the optical disk control device 36 is transmitted to the interface circuit 35 and the bus 29.
Is supplied to the error correction circuit 32 via the.

When the objective lens 10 is moved by the tracking control circuit 28, the linear motor 6, that is, the optical head 5 is moved by the linear motor control circuit 8 so that the objective lens 10 is located near the center position in the optical head 5. Be moved.

The D / A converter 31 includes a focusing control circuit 27, a tracking control circuit 28, a linear motor control circuit 8, and a CPU 30 for controlling the entire optical disk apparatus.
Used to transfer data between and.

The motor control circuit 4, the linear motor control circuit 8, the laser control circuit 15, the PLL circuit 16, the data reproduction circuit 18, the focusing control circuit 27, the tracking control circuit 28, the error correction circuit 32, and the like are connected via a bus 29. It is controlled by the CPU 30. The CPU 30 performs a predetermined operation according to a program recorded in the memory 2.

Here, the details of the data reproducing circuit will be described with reference to FIG.

The data reproducing circuit 18 includes a binarizing circuit 61, a shift register 62, and a demodulating circuit 6 as shown in FIG.
3. An address mark detection circuit 64 as an address mark detection means, a word boundary counter 65, an IED check circuit 66, an address comparison circuit 67, and a header detection signal generation circuit 68.

The binarization circuit 61 binarizes the addition signal from the adder 26e. This binarization circuit 6
The binary signal from 1 is supplied to the PLL circuit 16,
It is converted into a data sequence (channel data) synchronized with the reproduction clock signal (channel clock).

A channel clock and channel data as output signals of the PLL circuit 16 are supplied to a shift register 62 having a 16-bit configuration. This channel clock is
It is also supplied to a demodulation circuit 63, an address mark detection circuit 64, and a word boundary counter 65.

The shift register 62 converts the supplied channel data into 16-bit parallel data and outputs it. The 16-bit channel data from the shift register 62 is supplied to a demodulation circuit 63 and an address mark detection circuit 64.

The demodulation circuit 63 outputs, as ROM output data, data stored at an address corresponding to the 16-bit address data from the shift register 62 when the word boundary signal from the word boundary counter 65 is supplied. A demodulation ROM (not shown) and R from the demodulation ROM
It comprises a parallel-serial converter (not shown) which converts demodulated data as OM output data into serial data according to a data clock generated by dividing the channel clock from the PLL circuit 16 and outputs the data. .

The ROM output data has a predetermined value, for example, 8-16 corresponding to the address data.
This is data that is demodulated based on the code modulation rule, that is, 16-bit channel bits are demodulated into 8-bit data.

The demodulated data signal from demodulation circuit 63 is I
It is output to the ED check circuit 66 and the address comparison circuit 67. The data clock generated by the demodulation circuit 63 is output to the IED check circuit 66, the address comparison circuit 67, and the header detection signal generation circuit 68.

The address mark detection circuit 64 is composed of a comparator. Each time a channel clock is supplied from the PLL circuit 16, the 16-bit channel data from the shift register 62 matches the 16-bit address mark. The address mark detection signal is output when they match with each other. The address mark detection signal from the address mark detection circuit 64 is output to a word boundary counter 65, an IED check circuit 66, an address comparison circuit 67, and a header detection signal generation circuit 68.

The word boundary counter 65 counts using the address mark detection signal from the address mark detection circuit 64 as a trigger and outputs a word boundary signal for each fixed-length block code (16 channel bits). The word boundary signal from the word boundary counter 65 is output to the demodulation circuit 63.

After the address mark detection signal from the address mark detection circuit 64 is supplied to the IED check circuit 66, the sector address of the 6-byte address part PID supplied from the demodulation circuit 63 and the error detection code IED
Is accepted based on the data clock, and whether or not the sector address is correct is determined based on whether or not the operation result of the accepted sector address with the error detection code IED is “0”.

The check result of the IED check circuit 66 is output to the header detection signal generation circuit 68.

After receiving the address mark detection signal from the address mark detection circuit 64, the address comparison circuit 67 receives the 4-byte sector address of the address part PID supplied from the demodulation circuit 63 based on the data clock. The ID number in the received sector address is compared with any one of "1" to "4", and a signal corresponding to the matching ID number is output.
The signal corresponding to the ID number from the address comparison circuit 67 is output to the header detection signal generation circuit 68. For example,
When the ID number is “1”, “00” is output, and when the ID number is “2”, “01” is output, and the ID number is “3”.
In this case, "10" is output, and when the ID number is "4", "11" is output.

The address comparing circuit 67 outputs the received sector address to the CPU 30 as address data.

The header detection signal generation circuit 68 generates a signal corresponding to the ID number supplied from the address comparison circuit 67 when the check result from the IED check circuit 66 is correct, and an address from the address mark detection circuit 64. A header detection signal is generated corresponding to the end of the mirror mark area in accordance with the mark detection signal and the number of bytes counted by the data clock from the demodulation circuit. For example, the address mark detection signal is supplied. Is a binary counter for counting the number of bytes from the data clock by the data clock from the demodulation circuit. The header detection signal from the header detection signal generation circuit 68 is
And output to the CPU 30. For example, when a signal indicating that the check result is correctly “1” as the ID number is supplied, a header detection signal is generated 94 bytes after the address mark detection signal is supplied from the address mark detection circuit 64, and the check result is output. When a signal indicating "2" is correctly supplied as an ID number, a header detection signal is generated 76 bytes after the address mark detection signal is supplied from the address mark detection circuit 64, and the check result indicates that the ID number is correctly "ID". When a signal indicating "3" is supplied, a header detection signal is generated 30 bytes after the address mark detection signal is supplied from the address mark detection circuit 64, and the check result is a signal indicating "4" as the ID number correctly. Is supplied, an address mark detection signal from the address mark detection circuit 64 is supplied. And it generates a header detection signal after 12 bytes from being.

When the address mark detection circuit 64 of the data reproduction circuit 18 described above detects the pattern shown in FIG. 2, this pattern is recognized as an address mark. As already described, the specific pattern of the address mark shown in FIG. 2 is a pattern which does not appear in the reproduction pattern affected by the defective pit in the VFO area and the reproduction pattern reproduced by the shifted binarization level. It is. Therefore, erroneous detection of the address mark can be prevented by adopting the specific pattern as shown in FIG. 2 as the address mark.

[0094]

According to the present invention, the following information recording / reproducing medium, information recording / reproducing medium format device, and information recording / reproducing device can be provided.

(1) When a defective pit is included in the VFO area, it is possible to prevent erroneous detection of an address mark by a reproduction pattern affected by the defective pit obtained by reproducing the VFO area including the defective pit. A medium for information recording and reproduction that can contribute.

(2) A second object of the present invention is to reproduce a VFO area containing a defective pit, which is affected by a defective pit obtained when the VFO area contains the defective pit. An information recording / reproducing medium formatting device for formatting an information recording / reproducing medium which can contribute to preventing erroneous detection of an address mark by a pattern.

(3) A third object of the present invention is to provide a reproducing apparatus which is affected by a defective pit obtained by reproducing a VFO area containing a defective pit when the VFO area contains the defective pit. An information recording / reproducing apparatus capable of preventing erroneous detection of an address mark due to a pattern.

[Brief description of the drawings]

FIG. 1 is a diagram schematically showing a sector area provided on an optical disc as an information recording / reproducing medium according to an embodiment of the present invention.

FIG. 2 is a diagram showing an example of an address mark according to the present invention.

FIG. 3 shows a state where a normally recorded VFO area is reproduced at a regular binarization level, and a VFO including defective pits is shown.
FIG. 7 is a diagram illustrating a state where an area is reproduced at a normal binarization level and a state where a VFO area including a defective pit is reproduced at a shifted binarization level.

FIG. 4 is a conceptual diagram showing a DSV value of an address mark according to the present invention.

FIG. 5 is a diagram schematically showing a formatting device according to an embodiment of the present invention.

FIG. 6 is a diagram schematically showing an information recording / reproducing apparatus according to an embodiment of the present invention.

FIG. 7 is a diagram schematically showing a data reproducing circuit in the information recording / reproducing apparatus.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Optical disk 5 ... Optical head 15 ... Laser drive circuit 16 ... PLL circuit 18 ... Data reproduction circuit 64 ... Address mark detection circuit

Claims (3)

[Claims] The present invention has a concentric or spiral track, a plurality of sector areas each having a predetermined track length, a sector area having a header area and a recording area, and the header area having an address information. A first area to be recorded, a second area to record an address mark indicating the position of the address information, and a frequency-synchronized pattern for reproducing the address information, the pattern being restricted by a predetermined run length. In the information recording / reproducing medium having a third area in which a synchronization pattern is recorded for recording, a synchronization pattern having a constant period in which the run length of symbol 0 is 3 in channel bits is recorded in the third area. And a pattern composed of 22 channel bits, the fourth channel bit, the eighth channel bit,
An information recording / reproducing medium, wherein a specific pattern in which an even number of patterns in which a symbol 1 appears in a second channel bit is arranged is recorded in the second area as an address mark. 2. It has concentric or spiral tracks and has a plurality of sector areas each having a predetermined track length. The sector areas have a header area and a recording area, and the header area has an address information. A first area to be recorded, a second area to record an address mark indicating the position of the address information, and a frequency-synchronized pattern for reproducing the address information, the pattern being restricted by a predetermined run length. In the information recording / reproducing medium formatting device for formatting the information recording / reproducing medium so as to have a third area in which a synchronization pattern for recording is recorded, a fixed period in which the run length of symbol 0 is 3 by channel bits In the third area, and is a pattern composed of 22 channel bits. The fourth channel bit, the eighth channel bit,
And information formatting means for formatting the second area as a specific pattern in which an even number of patterns in which the symbol 1 appears in the 22nd channel bit is arranged as an address mark. Media formatting device. 3. It has a concentric or spiral track, has a plurality of sector areas having a predetermined track length, the sector area has a header area and a recording area, and the header area has the address information. A first area to be recorded, a second area to record an address mark indicating the position of the address information, and a frequency-synchronized pattern for reproducing the address information, the pattern being restricted by a predetermined run length. An information recording / reproducing apparatus for recording and reproducing information on and from an information recording / reproducing medium having a third area in which a synchronization pattern for recording a symbol is recorded, wherein the run length of symbol 0 is 3 with channel bits. The third area in which the synchronization pattern of a predetermined period is recorded is reproduced, and is a pattern composed of 22 channel bits. The second area in which a specific pattern in which an even number of patterns in which the symbol 1 appears at the channel bit, the eighth channel bit, and the twenty-second channel bit is arranged as an address mark is reproduced, and the reproduction obtained by this reproduction is performed. An information recording / reproducing apparatus comprising: address mark detecting means for detecting an address mark from a pattern; and information recording / reproducing means for recording / reproducing information according to the address mark detected by the address mark detecting means. .