JPH10307805A - Autonomous evolution type system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent system down and malfunctions from being generated by autonomously changing hardware constitution corresponding to the change of an environment. SOLUTION: An adaptation evaluation part 2 evaluates the adaptation to the environment of respective circuits when the circuits indicated by chromosome data inputted from a circuit generation part 1 are constituted on arithmetic/ control processing parts 6-1 and 6-2, that is a processing how much adapted to the environment the circuits generated by the circuit generation part 1 can execute as the circuits of the arithmetic/control processing parts 6-1 and 6-2. Further, by operating the adaptation evaluation part 2 even during the normal operation of a system, the evaluated value of the arithmetic/control processing parts 6-1 and 6-2 in a valid state is obtained at all times, and when the evaluated value becomes lower than a reference value, it is judged that the arithmetic/ control processing parts 6-1 and 6-2 can not cope with the environment, that is can not maintain initial performance, and this system automatically starts the reconstitution processing of the circuits.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system for performing arithmetic and control operations by combining various types of hardware, and more particularly to an autonomous evolution type system for autonomously changing a hardware configuration in response to a change in environment.

[0002]

2. Description of the Related Art Conventionally, in a system in which various kinds of hardware such as a selector, a counter, an adder, and a multiplier are combined and operated and controlled, an environment in which the system is to be placed in the future is predicted at the design stage and adapted. The hardware and software configurations are defined as follows.
FIG. 10 shows such a conventional system, in which an operation / control device 101 performs processing on an operation / control object 102 based on an execution command signal and a feedback signal, and responds to the processing result from the operation / control object 102. By returning the feedback signal, the influence of disturbance or the like is compensated within a range predicted in advance.

[0003]

In the conventional system,
When an unpredictable situation occurs due to a change in environment, there is a problem that it is difficult to maintain the initial performance of the system, or a system down or malfunction occurs.

As a countermeasure, the software and hardware of the system have been changed in response to a change in the environment. Conventionally, however, the change has been mainly performed by changing the software, and the situation was not predicted at the design stage. In the event that a problem occurred and the software could not handle it, the method of changing the hardware was used. However, in order to change the software or hardware, in any case, the system must be stopped, the cause must be clarified, the software and hardware must be changed based on the results, and then the system must be restarted. There is a problem that it takes time and labor because it is necessary to perform the operation.

When the hardware cannot be changed directly as in a system connected via a network, a method of changing only the software by communication can be considered. In this method, until the system is restarted. Requires a lot of time.

Further, it is conceivable to change software autonomously by a genetic algorithm. However, there is a problem that the change of software alone cannot cope with a change in environment and the execution speed is reduced.

The present invention has been made to solve such a problem, and an object of the present invention is to provide an autonomous evolution type system which autonomously changes a hardware configuration in response to an environmental change. .

[0008]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention has a circuit configured to be reconfigurable, and performs arithmetic and control means for performing at least one of arithmetic and control operations of an arithmetic and control target. And means for evaluating the adaptability of the circuit formed on the arithmetic and control means to the environment and reconfiguring the circuit of the arithmetic and control means based on the evaluation result.

More specifically, the autonomous evolution type system of the present invention has a circuit configured to be reconfigurable, and performs operation / control means for performing at least one process of operation and control of an operation / control object; A circuit generating means for generating a circuit to be configured on the arithmetic and control means and outputting circuit configuration information indicating the configuration of the circuit; and when the circuit generated by the circuit generating means is configured on the arithmetic and control means. Fitness evaluation means for evaluating the fitness of the circuit to the environment, and evolutionary processing means for performing a process of changing and evolving a circuit generated by the circuit generation means based on the evaluation result of the fitness evaluation means. Receiving from the circuit generation means circuit configuration information indicating the configuration of the circuit evolved by the evolutionary processing means,
Reconfiguration processing means for reconfiguring the circuit of the arithmetic and control means based on the circuit configuration information.

Here, it is desirable to multiplex the arithmetic / control means and reconfigure the circuit without stopping the processing of the arithmetic / control means by the reconfiguration processing means. Further, it is desirable that the circuit generation means changes a circuit which generates any one of a functional block level, a circuit configuration information bit level, a logic gate level, and a keyword level of a hardware description language as a minimum change unit.

Further, the circuit generation means generates a plurality of circuits, the fitness evaluation means evaluates each of the plurality of circuits, and the evolutionary processing means executes a plurality of circuits by a genetic algorithm based on the evaluation results of the plurality of circuits. It is desirable to find a circuit that has evolved by changing the circuit.

At this time, when a plurality of circuits are respectively described by a plurality of pieces of chromosome information composed of bit strings corresponding to function change units in the circuit generation means, and when a plurality of circuits are changed by the genetic algorithm in the evolutionary processing means, a plurality of circuits are used. A first process of selecting any of the chromosome information and removing the chromosome information that has not been selected, and a second process of exchanging an arbitrary part of a bit string among the plurality of chromosome information.
It is more desirable to perform the processing in combination with the third processing for inverting an arbitrary part of the bit string of the plurality of pieces of chromosome information.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) FIG. 1 is a block diagram showing a configuration of a system according to a first embodiment of the present invention. This system includes an arithmetic and control unit 5 that performs arithmetic or control processing on an arithmetic and control target 9, a circuit generation unit 1 for changing the hardware configuration of the arithmetic and control unit 5, a fitness evaluation unit 2, an evolution It comprises a dynamic processing unit 3 and a reconstruction processing unit 4.

The arithmetic and control unit 5 includes an arithmetic and control processing unit 6
-1, 6-2, an input control circuit 7 and an output control circuit 8. The calculation / control processing units 6-1 and 6-2 have circuits configured to be reconfigurable. Arithmetic / control processing unit 6
Each of the circuits -1 and 6-2 is provided with a plurality of reconfigurable elements corresponding to the function change, and the function of the circuit is determined by the use state and connection state of the plurality of reconfigurable elements. You.

Here, the arithmetic / control processing units 6-1 and 6-2
Are duplicated, are provided with the same type and the same number of reconfigurable elements, and are configured such that the circuits that can be realized by each are the same. At this time, all of the hardware of the operation / control processing units 6-1 and 6-2 may be duplicated, or only the reconfigurable area, that is, only the circuit portion configured by the reconfigurable element may be duplicated. If at least the configuration of the reconfigurable element is the same between the arithmetic / control processing units 6-1 and 6-2, a circuit having the same function with the same configuration is obtained. In the present embodiment, only one of the calculation / control processing units 6-1 and 6-2 is set to the valid state, and the processing on the calculation / control target 9 is performed.

The reconfigurable element is actually set in correspondence with a functional block of a circuit, a circuit configuration information bit, a logic gate, a keyword of a hardware description language, or the like. The functional blocks are a selector, a counter, an adder, a multiplier, and the like, and the circuit configuration is changed by changing a use state or a connection state of each functional block.

The circuit configuration information bit is a PLD (Progra
mmable Logic Device) and FPGA (Field Programmab)
le Gate Array), and the circuit configuration is changed by directly changing the configuration bit.

The logic gates are AND gates, OR gates, NAND gates, NOR gates, EX-OR gates, etc. As in the case of the functional block, the use state and connection state of each gate are changed. Rewriting the contents of ROM composed of gates and PL
The circuit configuration is changed by performing switching by A or a multiplexer.

The keywords of the hardware description language are as follows.
For example, as shown in FIG.
Gate 42, three NOT gates 43 and eight NAs
A 3 to 8 decoder constituted by an ND gate 44 is indicated by a dotted line 45 when described as shown in FIG.
The contents correspond to description contents such as and 46, and the circuit configuration is changed by rewriting these description contents.

Even if each reconfigurable element provided in the circuit corresponds to only one of the functional block, the circuit configuration information bit, the logic gate, and the keyword of the hardware description language, the functional block, It may optionally correspond to a circuit configuration information bit, a logic gate, or a keyword of a hardware description language.

By the way, in this system, the following chromosome data is used to identify various circuits formed in the operation / control processing units 6-1 and 6-2 according to the configuration of the reconfigurable element.

The chromosome data is calculated by the arithmetic / control processing unit 6-
Data represented by a bit string corresponding to the minimum unit of function change of the circuits 1 and 6-2. The chromosome data alone, for example, the type and number of reconfigurable elements provided in the circuit, each reconfigurable element The information necessary for changing the circuit configuration, such as the use state and connection state, can be determined.

The chromosome data is processed by the arithmetic / control processing unit 6.
-1, 6-2 are described in correspondence with reconfigurable elements, that is, function blocks, circuit configuration information bits, logic gates, or keywords of a hardware description language. Therefore, the arithmetic / control processing unit 6
The minimum unit for changing the functions of the circuits -1 and 6-2 is any one of a functional block level, a circuit configuration information bit level, a logic gate level, and a keyword level of a hardware description language.

FIG. 4 shows an example of such chromosome data. Here, the circuit 31 and the circuit 32 have the same type and the same number of functional blocks. The circuit 31 has chromosome data indicated as “1101101”, and C = A × B based on N-bit input signals A and B. After performing the operation of −1, the circuit 32 has a function of outputting a 2N-bit output signal C. The circuit 32 indicates that the chromosome data is “1101110”, and based on the N-bit input signals A and B, C = A
It is assumed that the device has a function of outputting a 2N-bit output signal C after performing the operation of × B-1.

In this case, by the genetic processing described later,
The chromosome data of the circuit 31 is changed from “1101101” to “1”.
101110 ", the circuit 31 changes the circuit configuration so as to realize the same function as the circuit 32, in this case, changes the use state and connection state of a plurality of functional blocks. If 1101101 "is indicated, it can be determined that the circuit has the same structure and the same function as the circuit 31, and similarly, the chromosome data is" 1 ".
If 101110 ″ is indicated, it can be determined that the circuit 32 has the same structure and the same function.

Hereinafter, the operation of this system will be described separately for normal operation and circuit reconfiguration. At the time of normal operation, mainly the arithmetic and control device 5 is operated to perform processing on the arithmetic and control target 9. Specifically, an execution command signal and a feedback signal are input to the input control circuit 7, and the input control circuit 7 calculates the execution command signal and the feedback signal by using the arithmetic / control processing unit 6-1 or 6-
2, one of the signal lines 22-
The signal is output via 1, 23-1, or the signal lines 22-2, 23-2. Note that two sets of signal lines 22-1 and 23-1 or signal lines 22-1 and 22-1 connected to the input control circuit 7 in advance according to the validity / invalidity of the arithmetic / control processing units 6-1 and 6-2.
One of the sets 2, 23-2 is effectively switched.

Of the operation / control processing units 6-1 and 6-2, those in the valid state generate operation / control signals based on an execution command signal and a feedback signal input from the input control circuit 7, and generate the operation / control signals. The calculated / control signal is transferred to the signal line 24.
Output to the control circuit 8 via -1, 24-2.

The output control circuit 8 processes the operation / control object 9 based on the operation / control signals input from the operation / control processing units 6-1 and 6-2 in the valid state. The operation / control target 9 outputs a feedback signal corresponding to the result to the input control circuit 7. The operation / control processing unit 6-
One of the signal lines 24-1 and 24-2 of the output control circuit 8 is switched to be valid according to the valid / invalid state of 1, 6-2.

By operating the fitness evaluation unit 2 during normal operation as described later, the evaluation values of the computation / control processing units 6-1 and 6-2 in the effective state are always obtained. Calculation / control processing unit 6-1 and 6-2 in the valid state
Therefore, it is desirable that the system autonomously starts circuit reconfiguration when it becomes impossible to adapt to the environment.

Next, the case where the circuits of the arithmetic / control processing units 6-1 and 6-2 are reconfigured will be described. In this system, in order to obtain a circuit to be configured on the arithmetic / control processing units 6-1 and 6-2, that is, a circuit having a high degree of adaptability to the environment, a circuit simulation is performed by focusing on chromosome data, and an optimal circuit is obtained. Conversely, the actual calculation and control processing unit 6-
Reconfigure the circuits 1, 6-2.

More specifically, as shown in the flowchart of FIG. 5, first, the circuit generation unit 1 generates a plurality of circuits to be formed on the arithmetic / control processing units 6-1 and 6-2, and A plurality of corresponding chromosome data is set as an initial group of chromosome data (step S1). In this case, the circuit generation unit 1 changes the circuit to be generated by using any one of the functional block level, the circuit configuration information bit level, the logic gate level, and the keyword level of the hardware description language as a minimum change unit. .

However, as described above, the chromosome data is described corresponding to the functional block level, the circuit configuration information bit level, the logic gate level, or the keyword level of the hardware description language. Generates n pieces of chromosome data directly by changing the bit string of the chromosome data indicating the circuits of the operation / control processing sections 6-1 and 6-2 held in a valid state by an appropriate random number generation process, These n pieces of chromosome data are used as an initial group of chromosome data corresponding to n types of circuits.

The n pieces of chromosome data generated by the circuit generation unit 1 are output to the fitness evaluation unit 2 and the evolutionary processing unit 3 via signal lines 10-1 to 10-n. Next, the fitness evaluation section 2 evaluates the fitness of n types of circuits corresponding to the n pieces of chromosome data input from the circuit generation section 1 to obtain n evaluation values (step S2).

At this time, the fitness evaluation unit 2 is provided with the circuit generation unit 1
Of the circuits to the environment when the circuits indicated by the chromosome data input from the processor are configured on the operation / control processing units 6-1 and 6-2, in other words, the circuit generation unit 1
Are generated by the arithmetic and control processing units 6-1 and 6
It is evaluated to what degree the circuit suitable for the environment can be executed as the circuit of -2.

Therefore, the fitness evaluation section 2 has a model (hereinafter, element model) corresponding to the reconfigurable elements provided in the operation / control processing sections 6-1 and 6-2 and an operation / control object 9 Model (hereinafter referred to as a target model) is defined in advance, a circuit model corresponding to chromosome data is created by each element model, a simulation is performed using this circuit model and the target model, and the simulation result is obtained. Output as evaluation value.

In order to execute this simulation,
The fitness evaluation unit 2 actually calculates the execution command signal input to the calculation and control unit 5 through the processing of the calculation and control processing units 6-1 and 6-2 in an effective state based on the execution command signal. The operation / control signal obtained by the control device 5, the evaluation signal output from the operation control object 9, and the environment change signal are input. The evaluation signal is included in the feedback signal, and is used to monitor the state of the operation / control target 9. The environment change signal is also included in the feedback signal, and responds to disturbance due to the environment change.

The fitness evaluation unit 2 combines the n evaluation values obtained by the simulation together with the corresponding n chromosome data through the signal lines 12-1 to 12-n. Output to

Further, the fitness evaluation unit 2 outputs the chromosome data for which the best evaluation value is obtained to the circuit generation unit 1 via the signal line 13 together with the maximum evaluation value, and calculates the valid state.
A signal indicating that a circuit more adapted to the environment than the circuits of the control processing units 6-1 and 6-2, that is, an evolved circuit, is output to the reconstruction processing unit 4 via the signal line 14.

In the fitness evaluation section 2, the evaluation values of the operation / control processing sections 6-1 and 6-2 in the valid state are also determined at the same time, and the maximum evaluation value obtained by the simulation is calculated in the valid state. The above-described signals may be output to the circuit generation unit 1 and the reconstruction processing unit 4 only when the evaluation values of the circuits of the controls 6-1 and 6-2 are exceeded.

Further, by operating the fitness evaluation unit 2 even during the normal operation of the system, the evaluation values of the operation / control processing units 6-1 and 6-2 in the effective state are always obtained. When the value falls below an appropriate reference value, the arithmetic and control processing units 6-1 and 6-2 determine that the environment cannot respond to the environment, that is, the initial performance cannot be maintained, and the system automatically operates. It is desirable to start the circuit reconfiguration processing.

On the other hand, the circuit generation unit 1 calculates the chromosome data of the maximum evaluation value input from the fitness evaluation unit 2 for the next-generation
As chromosome data that is a candidate for a circuit of the control processing units 6-1, 6-2, the chromosome data is stored in place of the chromosome data stored at that time (step S3). In order to determine whether or not the evolution has been achieved, the maximum evaluation value sent from the fitness evaluation unit 2 together with the chromosome data is compared with a preset reference value (step S4).

If the maximum evaluation value is smaller than the reference value as a result of the comparison by the circuit generation unit 1 (N in step S4)
o) Assuming that the circuit has not evolved sufficiently, the evolutionary processing unit 3 applies the following genetic processing to each chromosome data (step S5), and the fitness evaluation unit 2 continues to simulate Is set (step S6).

FIG. 6 is a diagram for specifically explaining the genetic processing by the evolutionary processing unit 3. Here, the chromosome data to be subjected to genetic processing are chromosome data 41 to 4 having a total number n = 4 as shown in block 61.
Consider that 4 has been entered.

The genetic processing in the evolutionary processing unit 3 is executed according to the genetic algorithm described below. First, a selection process of selecting arbitrary chromosome data 41 to 44 from the chromosome data 41 to 44 and removing and selecting unselected chromosome data 41 to 44 is performed. At this time, the chromosome data 41 to 4 in the initial state
In order to keep the total number of data n = 4, n = 4, the selected chromosome data 41 to 44 are expanded so that the chromosome data 41 to 44 corresponding to the multiplication are removed. For example, in the selection process from block 61 to block 62, the chromosome data 41 is selected and the chromosome data 44 is selected.
Are removed, and in the block 62, the same bit string data as the chromosome data 41 is set as new chromosome data 44.

As reference values for selection and selection, the evaluation values of the chromosome data 41 to 44 are used. For example, the higher the evaluation value, the higher the probability of selection, and conversely, the lower the evaluation value, the higher the evaluation value. The selection and selection of the chromosome data 41 to 44 are performed by a probabilistic process or the like that facilitates selection.

Next, any two chromosome data 41 to 4
A crossover process of exchanging bit strings of an arbitrary part between the four is performed. For example, in the crossover process from the block 62 to the block 63, the chromosome data 41 and the chromosome data 4
2, the bit strings 45 and 46 are exchanged,
Further, the bit strings 47 and 48 are exchanged between the chromosome data 43 and the chromosome data 44.

Further, a mutation process for inverting an arbitrary bit string of the arbitrary chromosome data 41 to 44 is performed.
For example, in the mutation process from block 63 to block 64, the bit string 49 of the chromosome data 44 is inverted.

The above-described selection, crossover, and mutation processes are repeated until chromosome data 41 to 44 satisfying preset termination conditions are obtained. The final generation, that is, a new group of chromosome data for performing the next simulation in the fitness evaluation unit 2 is set.

If the bit sequence of the chromosome data itself is changed in this way, the changed chromosome data may not be meaningful as the circuits of the operation / control processing units 6-1 and 6-2. Therefore, at least the chromosome data 41 to 44 are included in the above-mentioned termination condition.
Chromosome data 41 to 4 indicating circuits that can be simulated by the fitness evaluation unit 2 at least.
Repeat the genetic treatment until 4 is obtained. The selection, crossover, and mutation processes need not be repeated one by one as described above, and the order and number of each process can be arbitrarily determined.

FIG. 7 shows a change in the circuit configuration of the arithmetic and control processing unit when the chromosome data is changed by the genetic processing. A and B represent input signals, and C represents an output signal.

For example, regarding the circuit 51 of the arithmetic / control processing unit 6-1 or 6-2 in which six functional blocks a to f are arranged, before performing the genetic processing (before evolution), each functional block a To f are not connected. At this time, by changing the chromosome data of the circuit 51 by genetic processing, the use state and connection state of each of the functional blocks a to f are changed as in the circuits 52 and 53. In this case, since the bit string itself of the chromosome data is changed, the functional blocks a and
In some cases, such as c and the functional block b of the circuit 53, there is a portion that is not connected to the processing of the entire circuit just because it is connected to another functional block. Then, such a genetic process is repeated, and the use state and the connection state of the functional blocks a to f of the last generation are determined as in the circuits 54 and 55.

Returning to the description, the evolutionary processing unit 3 converts each chromosome data obtained by the above-described genetic processing into a signal line 1.
Output to the circuit generator 1 through 7-1 to 17-n. The circuit generation unit 1 sends the chromosome data input from the evolutionary processing unit 3 to the fitness evaluation unit 2 via the signal lines 10-1 to 10-n, and based on these new chromosome data, At 2, the simulation is continued.

Processing of steps S2 to S6 as described above,
That is, the fitness evaluation unit 2 calculates the evaluation value of the circuit corresponding to each chromosome data, compares the maximum evaluation value with the reference value in the circuit generation unit 1, and performs genetic processing on the chromosome data in the evolutionary processing unit 3. The generation unit 1, the fitness evaluation unit 2, and the evolutionary processing unit 3 are repeated while being enabled in parallel.

The maximum evaluation value of the chromosome data obtained by the simulation of the fitness evaluation unit 2 is
(Step S4: Yes), it is considered that the circuit indicated by the chromosome data has sufficiently evolved, and the calculation / control processing units 6-1 and 6 are actually used. The circuit of -2 is reconfigured (step S7).

At this time, the invalid operation / control processing unit 6
The circuit is reconfigured with respect to -1 and 6-2, and after the reconfiguration is completed, the valid / invalid state of the arithmetic / control processing units 6-1 and 6-2 is switched to each other, so that the valid state has been obtained. The operation of the reconfigured operation / control processing units 6-1 and 6-2 is started instead of the operation / control processing units 6-1 and 6-2 (step S8).

In this case, the circuit generator 1 first converts the chromosome data having the maximum evaluation value larger than the reference value into circuit configuration information according to the circuit configuration information bit format for actually changing the circuit configuration. The obtained circuit configuration information is output to the reconstruction processing unit 4 via the signal line 11.

The reconfiguration processing unit 4 converts the circuit configuration information input from the circuit generation unit 1 into an invalid operation / control processing unit 6.
1, 6-2 via the signal lines 18-1 and 18-1, and also generates a reconfiguration control signal required for reconfiguration of the circuit, and similarly performs an invalid operation / control process. Signal lines 19-1 and 19-2 toward sections 6-1 and 6-2
Output via.

Calculation / control processing units 6-1 and 6 in the invalid state
Based on the circuit configuration information and the reconfiguration control information input from the reconfiguration processing unit 2, the reconfiguration circuit 2 reconfigures the circuit by changing the use state and the connection state of the reconfigurable element.

Calculation / control processing units 6-1 and 6 in the invalid state
When the reconfiguration of the circuit No. 2 is completed, the reconfiguration processing unit 4 switches the reconfigured operation / control processing units 6-1 and 6-2 to the valid state, and performs the operation / control processing that was in the valid state until then. The sections 6-1 and 6-2 are switched to the invalid state. Further, the reconfiguration processing unit 4 outputs the input control signal and the output control signal to the input control circuit 7 and the output control circuit 8 via the signal lines 20 and 21, respectively, and outputs the signal lines 22-1 and 22 of the input control circuit 7. -2 and signal lines 23-1, 23-
2. Switching between valid / invalid of the signal lines 24-1 and 24-2 of the output control circuit 8 is performed.

As a result, the arithmetic and control processing units 6-1 and 6-2 whose circuits have been reconfigured replace the arithmetic and control processing units 6-1 and 6-2 which were in the valid state until then. The processing for the control target 9 is started.

As described above, in the system according to the present embodiment, the operation / control processing units 6-1 and 6-2 capable of reconfiguring the circuit are provided in the operation / control device 5, and the operation / control device 5 is provided. 5 needs to be adapted to the environment, the circuit generation unit 1 generates a circuit to be configured on the operation / control processing units 6-1 and 6-2, and focuses on chromosome data indicating the configuration of this circuit. Then, the fitness evaluation unit 2 evaluates the fitness of the circuit to the environment by performing a simulation when the circuit indicated by the chromosome data is configured on the arithmetic / control processing units 6-1 and 6-2. Genetic processing is performed on the chromosome data by the evolutionary processing unit 3 based on the evaluation result, thereby performing processing of changing and evolving the circuit generated by the circuit generation unit 1, and as a result, the evolved circuit Chromosome data showing structure Reconstructing the circuit of the arithmetic and control unit 6-1, 6-2 by the reconstruction processing unit 4 on the basis of.

In this way, even if the operating arithmetic and control unit 5 cannot fully adapt to the environment or maintain its initial performance, the arithmetic and control processing unit 6 cannot operate.
The 1,6-2 circuits are reconfigured to adapt to the environment. In other words, the arithmetic and control unit 5 has an autonomous evolution function of autonomously changing the hardware configuration in response to a change in the environment, so that it takes time and effort to change the function of the system as in the related art. Eliminates the need. In addition, since the circuit configuration of the arithmetic and control processing units 6-1 and 6-2, that is, the hardware configuration of the arithmetic and control unit 5 is directly changed, it is possible to cope with a large environmental change that cannot be changed by changing the software. Can also be kept fast.

The operation / control processing units 6-1 and 6-2 are duplicated, and only one of the operation / control processing units 6-1 and 6-2 is enabled to process the operation / control object 9.
When reconfiguring the circuit of 6-2, the operation of the operation / control processing units 6-1 and 6-2 in the valid state is not changed, and the operation / control processing units 6-1 and 6-2 in the invalid state are targeted. The circuit is reconfigured as follows, and after the reconfiguration is completed, the valid / invalid state is switched between each other.
The arithmetic and control unit 5 for reconfiguring the circuits 1 and 6-2
Need not be stopped.

The chromosome data is calculated by the arithmetic and control
It is described by a bit string corresponding to the minimum unit of the function change of the circuits 1 and 6-2. When the circuit is changed in the evolutionary processing unit 3, a genetic selection such as a selection process, a crossover process, or a mutation process is performed. Since the bit sequence itself of the chromosome data is changed by the processing, it is possible to perform simulations on various circuits that can be realized in the operation / control processing units 6-1 and 6-2, and to flexibly change the environment. Can be handled.

Next, an example in which the above-described system is applied to an image recognition device will be described with reference to FIG. This image recognition device includes an image recognition unit 71, a recognition rate evaluation unit 72, and a filter configuration change unit 73. The image recognition unit 71 includes a filtering unit 74 and a matching unit 75. Considering the relationship between this image recognition device and the system shown in FIG. 1, the image recognition unit 71 corresponds to the arithmetic and control unit 5, and the filtering unit 74 is the arithmetic and control processing unit 6-1.
6-2. The recognition rate evaluation unit 72 corresponds to the fitness evaluation unit 2, and the filter configuration change unit 73 corresponds to the circuit generation unit 1, the evolutionary processing unit 3, and the reconstruction processing unit 4. Further, the image signal corresponds to the operation / control object 9 and the arithmetic processing based on the image signal is performed. In this case, by providing a circuit composed of reconfigurable elements in the filtering unit 74, it is possible to change the filter configuration such as the order of the filter and the band division width.

When an image signal is input to the image recognizing unit 71, a filtering process is performed on the image signal by the filtering unit 74, so that, for example, edge enhancement,
A feature is extracted by performing image sharpening and noise removal, and the matching unit 75 performs matching with a predetermined recognition target based on the extracted feature to output a recognition result.

The recognition result is input to the recognition rate evaluation section 72. For example, when the recognition rate is reduced by changing a character, a figure, or another recognition target, these recognition rate evaluation sections 72 are used.
A simulation is performed on the new filter configuration of the filtering unit 74 by the filter configuration changing unit 73, and the filter configuration of the filtering unit 74 is changed based on the simulation result.

By doing so, the configuration of the filtering unit 74 is changed in accordance with the change in the recognition target, and the filtering process on the image signal can always be performed optimally, so that a high recognition rate can be maintained. become.
Furthermore, when the optimum filter configuration is not known in advance, such as when the recognition target is unknown, the processing is started for the time being, simulation is performed immediately, and the filter configuration of the filtering unit 74 is changed. The filter configuration is optimally changed. That is,
The image recognition device learns the optimum filter configuration for an unknown recognition target by itself.

(Second Embodiment) FIG. 2 shows a second embodiment of the present invention.
It is a block diagram showing the composition of the system concerning an embodiment. In the following, portions corresponding to those in FIG. 1 are denoted by the same reference numerals, and description will be made focusing on differences from the first embodiment.

In this embodiment, a plurality of arithmetic / control processing units are configured by combining multiplexing and parallelization.
That is, the arithmetic and control unit 5 is provided with n arithmetic and control processing units 6-1 to 6-n (multiplexing), and all of the arithmetic and control processing units 6-1 to 6-n during normal operation. 6-n is operated (parallelization). At this time, the output control circuit 8 outputs, for example, the output signals 24-of the operation / control processing units 6-1 to 6-n.
1 to 24-n are output as weighted sums as operation / control signals. Further, as described later, in this system, it is necessary to temporarily suspend a part of the operation / control processing units 6-1 to 6-n for circuit reconfiguration. Make sure that no errors occur.

Here, similarly to the first embodiment, even if the same type and the same number of reconfigurable elements are provided in the respective circuits of the operation / control processing units 6-1 to 6-n, the respective circuits are different from each other. A reconfigurable element may be provided. In the latter case,
In the fitness evaluation unit 2, element models corresponding to all reconfigurable elements provided in the circuits of the arithmetic processing units 6-1 to 6-n are defined.

In this system, when reconfiguring a circuit, a simulation is performed with all the operation / control processing units 6-1 to 6-n operating, and the circuit should be reconfigured according to the simulation result. Arithmetic / control processing unit 6
Select Then, the selected arithmetic / control processing unit 6-
1 to 6-n are temporarily stopped, and the other calculation / control processing units 6-1 to 6-n are kept operating, while the selected calculation / control processing units 6-1 to 6-n are kept operating. The circuit of -n is reconfigured, and after the reconfiguration is completed, the operation is restarted in synchronization with the other operation / control processing units 6-1 to 6-n that are operating.

By doing so, the circuits of the plurality of arithmetic / control processing units 6-1 to 6-n can be simultaneously reconfigured, and each circuit has a different configuration, that is, a different function. Since the hardware configuration can be changed, the hardware configuration of the arithmetic and control unit 5 is changed more flexibly than in the first embodiment, and it is possible to appropriately cope with a change in the environment. In addition, the necessary minimum operation / control processing unit 6-1
A sufficient effect can be obtained only by reconfiguring the circuits of .about.6-n.

[0074]

As described above, according to the present invention, the adaptability of the circuit formed on the operation / control means to the environment is evaluated, and the circuit of the operation / control means is reconfigured based on the evaluation result. By doing so, the hardware configuration of the system is autonomously changed according to changes in the environment.

At this time, a circuit to be formed on the arithmetic and control means is generated, the adaptability to the environment when the circuit is formed on the arithmetic and control means is evaluated, and the circuit is evaluated based on the evaluation result. Is changed and evolved, and as a result, the evolved circuit is reconfigured into the arithmetic and control means, so that it is possible to flexibly and appropriately respond to environmental changes.

The operation and control means are multiplexed, and the processing of the operation and control means is not stopped by the reconstruction processing means.
Since the circuit is reconfigured, it is possible to improve only the adaptability to the environment while continuing the processing on the operation / control object.

The circuit generating means generates a plurality of circuits, the fitness evaluation means evaluates each of the plurality of circuits, and the evolutionary processing means generates a plurality of circuits by the genetic algorithm based on the evaluation results of the plurality of circuits. Since it has been changed, various circuits that can be realized can be analyzed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a system according to a first embodiment of the present invention.

FIG. 2 is an exemplary view for explaining keywords of a description language of a hardware configuration according to the embodiment;

FIG. 3 is an exemplary view for explaining keywords of a description language of a hardware configuration according to the embodiment;

FIG. 4 is a view for explaining chromosome data in the embodiment.

FIG. 5 is a flowchart for explaining circuit reconfiguration processing in the embodiment;

FIG. 6 is an exemplary view for explaining genetic processing according to the embodiment;

FIG. 7 is a view showing an example of a change in circuit configuration due to a change in chromosome data in the embodiment.

FIG. 8 is a block diagram showing an example in which the embodiment is applied to an image recognition device.

FIG. 9 is a block diagram showing a configuration of a system according to a second embodiment of the present invention.

FIG. 10 is a diagram showing an example of a conventional system.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Circuit generation part 2 ... Fitness evaluation part 3 ... Evolutionary processing part 4 ... Reconstruction processing part 5 ... Arithmetic and control device 6-1 to 6-n ... Arithmetic and control processing part 7 ... Input control device 8 ... Output Control device 9 ... Calculation / control target

Claims (6)

[Claims] An arithmetic and control means having a circuit configured to be reconfigurable and performing at least one of arithmetic and control operations of an arithmetic and control object, and a circuit configured on the arithmetic and control means. Means for evaluating adaptability to the environment and reconfiguring the circuit of the arithmetic and control means based on the evaluation result. 2. An arithmetic and control unit having a circuit configured to be reconfigurable and performing at least one of arithmetic and control processing of an arithmetic and control object, and a circuit to be configured on the arithmetic and control unit. Circuit generating means for generating and outputting circuit configuration information indicating the configuration of the circuit; and determining the fitness of the circuit to the environment when the circuit generated by the circuit generating means is configured on the arithmetic / control means. A fitness evaluation means for evaluating, an evolution processing means for performing a process of changing and evolving a circuit generated by the circuit generation means based on an evaluation result of the fitness evaluation means; Reconfiguration processing means for receiving circuit configuration information indicating a configuration of an evolved circuit from the circuit generation means, and reconfiguring the circuit of the arithmetic / control means based on the circuit configuration information. An autonomous evolution type system to be characterized. 3. The apparatus according to claim 2, wherein said arithmetic and control means is multiplexed, and said reconstruction processing means reconfigures a circuit without stopping processing of said arithmetic and control means. The autonomous evolution system described. 4. The circuit generating means changes a circuit to be generated by using any one of a functional block level, a circuit configuration information bit level, a logic gate level, and a keyword level of a hardware description language as a minimum change unit. The autonomous evolution type system according to claim 2, wherein 5. The circuit generating means generates a plurality of circuits, the fitness evaluation means evaluates each of the plurality of circuits, and the evolutionary processing means generates an evaluation result of each of the plurality of circuits. The autonomous evolution system according to claim 2, wherein the plurality of circuits are changed based on a genetic algorithm based on the plurality of circuits, and the evolved circuit is obtained. 6. The circuit generating means describes each of the plurality of circuits with a plurality of pieces of chromosome information composed of a bit string corresponding to a minimum function change unit, and the evolutionary processing means uses the genetic algorithm to describe the plurality of circuits. When the circuit is changed, any one of the plurality of pieces of chromosome information is selected, a first process for removing unselected chromosome information, and a second step of exchanging an arbitrary part of a bit string between the plurality of pieces of chromosome information. And a third step of inverting an arbitrary part of the bit string of the plurality of pieces of chromosome information.
6. The method according to claim 5, wherein the processing is performed in combination with
Autonomous evolution type system described in 1.