JP3649551B2 - Autonomous evolution system - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a system that performs calculation and control by combining various types of hardware, and more particularly to an autonomous evolution system that autonomously changes a hardware configuration in response to environmental changes.
[0002]
[Prior art]
Conventionally, in a system that performs calculation and control by combining various hardware such as selectors, counters, adders, and multipliers, the hardware and hardware are designed to predict and adapt to the future environment in the design stage. Defines the software configuration. FIG. 10 shows such a conventional system. The arithmetic / control device 101 performs processing on the arithmetic / control target 102 based on the execution command signal and the feedback signal, and the arithmetic / control target 102 responds to the processing result. By returning the feedback signal, the influence of disturbance or the like is compensated within the range predicted in advance.
[0003]
[Problems to be solved by the invention]
In the conventional system, when an unpredictable situation occurs due to environmental changes, there are problems that it is difficult to maintain the initial performance of the system, or that the system goes down or malfunctions.
[0004]
As a countermeasure, system software and hardware have been changed in response to changes in the environment. Traditionally, however, software changes have mainly been dealt with, and a situation unforeseen at the design stage has occurred. The method of changing the hardware when it became impossible to cope with was taken. However, in order to change the software or hardware, in any case, stop the system once to elucidate the cause, change the software or hardware based on the result, and then start the system again. There is a problem that it takes manpower and time because it is necessary.
[0005]
In addition, when the hardware cannot be changed directly as in a system connected via a network, a method of changing only the software by communication can be considered, but this method requires a great deal of time until the system is restarted. Time is needed.
[0006]
Furthermore, although it is conceivable to change the software autonomously by a genetic algorithm, there are problems that the change of the software alone cannot cope with the change of the environment or the execution speed becomes slow.
[0007]
The present invention has been made to solve such problems, and an object of the present invention is to provide an autonomous evolution system that autonomously changes the hardware configuration in response to environmental changes.
[0008]
[Means for Solving the Problems]
In order to solve the above-described problems, the present invention has a circuit configured to be reconfigurable, and includes an arithmetic / control unit that performs at least one of arithmetic / control processing on the arithmetic / control target, and the arithmetic / control unit. Means for evaluating the adaptability of the constructed circuit to the environment and means for reconfiguring the circuit of the calculation / control means based on the evaluation result are provided.
[0009]
In more detail, the autonomous evolution system of the present invention has a circuit configured to be reconfigurable, an arithmetic / control means for performing at least one of arithmetic / control processing of an arithmetic / control target, and the arithmetic / control A circuit generating means for generating a circuit to be configured on the means and outputting circuit configuration information indicating the circuit configuration; and a circuit when the circuit generated by the circuit generating means is configured on the arithmetic / control means. The fitness evaluation means for evaluating the fitness for the environment, the evolution processing means for performing the evolution process by changing the circuit generated by the circuit generation means based on the evaluation result of the fitness evaluation means, and this evolution Reconfiguration processing means for receiving from the circuit generation means circuit configuration information indicating the circuit configuration evolved by the general processing means and reconfiguring the circuit of the arithmetic / control means based on the circuit configuration information. Those were.
[0010]
Here, it is desirable to multiplex the arithmetic / control means and reconfigure the circuit without stopping the processing of the arithmetic / control means by the reconfiguration processing means.
Further, it is desirable that the circuit generation means change the circuit to be generated with the function block level, the circuit configuration information bit level, the logic gate level, or the keyword level of the hardware description language as a minimum change unit.
[0011]
Furthermore, the circuit generation unit generates a plurality of circuits, the fitness evaluation unit evaluates each of the plurality of circuits, and the evolutionary processing unit changes the plurality of circuits by a genetic algorithm based on each evaluation result of the plurality of circuits. It is desirable to find a circuit that has evolved.
[0012]
At this time, when the plurality of circuits are described by the plurality of chromosome information composed of bit strings corresponding to the function change units in the circuit generation means, and the plurality of circuits are changed by the genetic algorithm in the evolutionary processing means, the plurality of chromosome information A first process for selecting any of the chromosome information and removing the unselected chromosome information; a second process for exchanging an arbitrary part of the bit string between the plurality of chromosome information; and a plurality of bit information of the chromosome information It is further desirable to perform in combination with the third process for inverting the arbitrary portion.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
(First embodiment)
FIG. 1 is a block diagram showing a configuration of a system according to the first embodiment of the present invention. This system includes an arithmetic / control device 5 that controls arithmetic or control processing on an arithmetic / control target 9, a circuit generation unit 1 for changing the hardware configuration of the arithmetic / control device 5, an fitness evaluation unit 2, an evolution The processing unit 3 and the reconstruction processing unit 4 are configured.
[0014]
The arithmetic / control device 5 includes arithmetic / control processing units 6-1 and 6-2, an input control circuit 7 and an output control circuit 8. The arithmetic / control processing units 6-1 and 6-2 have circuits configured to be reconfigurable. Each circuit of the arithmetic / control processing units 6-1 and 6-2 is provided with a plurality of reconfigurable elements corresponding to the function change. Depending on the use state and connection state of the plurality of reconfigurable elements, etc. The function of the circuit is determined.
[0015]
Here, the arithmetic / control processing units 6-1 and 6-2 are duplicated, and the same kind and the same number of reconfigurable elements are provided, and the circuits that can be realized in each are configured to be the same. Yes. At this time, even if all of the hardware of the arithmetic / control processing units 6-1 and 6-2 are duplicated, only a reconfigurable region, that is, a circuit part constituted by a reconfigurable element may be duplicated. If at least the reconfigurable elements have the same configuration between the arithmetic / control processing units 6-1 and 6-2, a circuit having the same configuration and the same function is obtained. In the present embodiment, only one of the calculation / control processing units 6-1 and 6-2 is set to the valid state, and the process for the calculation / control target 9 is performed.
[0016]
The reconfigurable element is actually set corresponding to a functional block of a circuit, a circuit configuration information bit, a logic gate, or a keyword of a hardware description language. Functional blocks are selectors, counters, adders, multipliers, and the like, and the circuit configuration is changed by changing the use state and connection state of each functional block.
[0017]
The circuit configuration information bits are configuration bits of PLD (Programmable Logic Device) and FPGA (Field Programmable Gate Array), and the circuit configuration is changed by directly changing the configuration bits.
[0018]
Logic gates are AND gates, OR gates, NAND gates, NOR gates, EX-OR gates, etc., and change the use state and connection state of each gate in the same way as functional blocks, and are composed of several gates. The circuit configuration is changed by rewriting the contents of the ROM to be read and switching by PLA or multiplexer.
[0019]
The keyword of the hardware description language is, for example, as shown in FIG. 3 for a 3to8 decoder including NOT gate 41, NOR gate 42, three NOT gates 43, and eight NAND gates 44 as shown in FIG. This corresponds to the description contents of the dotted line portions 45 and 46, etc., and the circuit configuration is changed by rewriting these description contents.
[0020]
Note that even if each reconfigurable element provided in the circuit supports only one of the functional block, circuit configuration information bit, logic gate, and hardware description language keyword, the functional block and circuit configuration information Bits, logic gates, or hardware description language keywords may be arbitrarily supported.
[0021]
By the way, in this system, the following chromosomal data is used to identify various circuits formed in the arithmetic / control processing units 6-1 and 6-2 according to the configuration of the reconfigurable element.
[0022]
Chromosome data is data indicated by a bit string corresponding to the minimum unit of function change of the circuit of the arithmetic / control processing units 6-1 and 6-2, and can be reconfigured, for example, provided in the circuit only by this chromosome data. Information necessary for changing the circuit configuration, such as the type and number of elements, the use state and connection state of each reconfigurable element, can be determined.
[0023]
Chromosome data corresponds to reconfigurable elements provided in each circuit of the arithmetic / control processing units 6-1 and 6-2, that is, functional blocks, circuit configuration information bits, logic gates, or keywords of hardware description languages. Is described. Therefore, the minimum unit of function change of the circuits of the arithmetic / control processing units 6-1 and 6-2 is any one of the function block level, the circuit configuration information bit level, the logic gate level, or the keyword level of the hardware description language. .
[0024]
FIG. 4 shows an example of such chromosome data. Here, the circuit 31 and the circuit 32 have the same type and the same number of functional blocks, and the circuit 31 has the chromosome data “1101101”, and C = A × B based on the N-bit input signals A and B. The circuit 32 has a function of outputting a 2N-bit output signal C after performing an operation of −1, and the circuit 32 indicates that the chromosome data is “1101110”. Based on the N-bit input signals A and B, C = Ax B and It is assumed that a 2N-bit output signal C is output after performing this operation.
[0025]
In this case, if the chromosome data of the circuit 31 is changed from “1101101” to “1101110” by genetic processing described later, the circuit 31 has a circuit configuration so as to realize the same function as the circuit 32. Change the usage status and connection status of the function block. If the chromosome data of a certain circuit is indicated as “1101101”, it can be determined that the circuit has the same structure and the same function as the circuit 31, and the chromosome data is indicated as “1101110”. Thus, it can be determined that the circuit 32 has the same structure and the same function.
[0026]
Hereinafter, the operation of this system will be described separately for normal operation and circuit reconfiguration.
During normal operation, only the arithmetic / control device 5 is operated to perform processing on the arithmetic / control target 9. Specifically, an execution command signal and a feedback signal are input to the input control circuit 7, and the input control circuit 7 outputs the execution command signal and the feedback signal to a valid state in the arithmetic / control processing unit 6-1 or 6-2. Is output to the other set via the signal lines 22-1 and 23-1 or the signal lines 22-2 and 23-2. Depending on the validity / invalidity of the arithmetic / control processing units 6-1 and 6-2, two sets of signal lines 22-1 and 23-1 or signal lines 22-2, which are connected to the input control circuit 7 in advance. Any one set of 23-2 is switched effectively.
[0027]
Among the arithmetic / control processing units 6-1 and 6-2, those in the valid state generate arithmetic / control signals based on the execution command signal and feedback signal input from the input control circuit 7, The control signal is output to the control circuit 8 through the signal lines 24-1 and 24-2.
[0028]
The output control circuit 8 performs processing of the calculation / control target 9 based on the calculation / control signals input from the calculation / control processing units 6-1 and 6-2 in the valid state. The calculation / control target 9 outputs a feedback signal corresponding to the result to the input control circuit 7. Note that either one of the signal lines 24-1 and 24-2 of the output control circuit 8 is switched to be valid in accordance with the valid / invalid state of the arithmetic / control processing units 6-1 and 6-2.
[0029]
By the way, as described later, by operating the fitness evaluation unit 2 during normal operation, the evaluation values of the calculation / control processing units 6-1 and 6-2 in the valid state are always obtained, It is desirable that the arithmetic / control processing units 6-1 and 6-2 start the circuit reconfiguration autonomously when it becomes impossible to adapt to the environment.
[0030]
Next, a case where the circuits of the arithmetic / control processing units 6-1 and 6-2 are reconfigured will be described. In this system, in order to obtain a circuit to be configured on the arithmetic / control processing units 6-1 and 6-2, that is, a circuit having high adaptability to the environment, a circuit simulation is performed by paying attention to chromosome data, and the optimum On the contrary, the circuits of the actual actual calculation / control processing units 6-1 and 6-2 are reconfigured from the chromosome data obtained from the simulation result.
[0031]
Specifically, as shown in the flowchart of FIG. 5, first, the circuit generation unit 1 generates a plurality of circuits to be configured on the arithmetic / control processing units 6-1 and 6-2, and a plurality of circuits corresponding to the respective circuits. Are set as an initial population of chromosome data (step S1). In this case, the circuit generation unit 1 changes the circuit to be generated with the function block level, the circuit configuration information bit level, the logic gate level, or the keyword level of the hardware description language as the minimum change unit. .
[0032]
However, as described above, since the chromosome data is described corresponding to the functional block level, the circuit configuration information bit level, the logic gate level, or the keyword level of the hardware description language, the circuit generation unit 1 actually holds in advance. The n pieces of chromosome data are directly generated by changing the bit sequence of the chromosome data indicating the circuit of the arithmetic / control processing units 6-1 and 6-2 in the valid state by appropriate random number generation processing. Is an initial population of chromosome data corresponding to n types of circuits.
[0033]
The n pieces of chromosome data generated by the circuit generation unit 1 are output to the fitness evaluation unit 2 and the evolution processing unit 3 via signal lines 10-1 to 10-n, respectively.
Next, the fitness evaluation unit 2 evaluates the fitness of the n types of circuits corresponding to the n chromosome data input from the circuit generation unit 1 to obtain n evaluation values (step S2).
[0034]
At this time, the fitness evaluation unit 2 is adapted to the environment of each circuit when the circuit indicated by the chromosome data input from the circuit generation unit 1 is configured on the arithmetic / control processing units 6-1 and 6-2. In other words, it is evaluated to what extent the circuit generated by the circuit generation unit 1 can execute processing suitable for the environment as the circuit of the arithmetic / control processing units 6-1 and 6-2.
[0035]
Therefore, the fitness evaluation unit 2 includes models corresponding to reconfigurable elements provided in the calculation / control processing units 6-1 and 6-2 (hereinafter referred to as element models) and models corresponding to the calculation / control target 9 ( Hereafter, the target model) is defined in advance, a circuit model corresponding to the chromosome data is created by each element model, a simulation is performed using this circuit model and the target model, and the simulation result is used as an evaluation value. Output.
[0036]
In order to execute this simulation, the fitness evaluation unit 2 executes the execution command signal input to the calculation / control device 5, and the calculation / control processing units 6-1 and 6-2 in the valid state based on the execution command signal. The calculation / control signal actually obtained by the calculation / control device 5 through the above process, the evaluation signal output from the calculation control target 9 and the environment change signal are input. The evaluation signal is included in the feedback signal, and is used to monitor the state of the calculation / control target 9. Similarly, the environment change signal is also included in the feedback signal, and corresponds to a disturbance caused by an environment change.
[0037]
The fitness evaluation unit 2 outputs the n evaluation values obtained by such a simulation to the evolutionary processing unit 3 through the signal lines 12-1 to 12-n together with the corresponding n chromosome data. .
[0038]
Furthermore, the fitness evaluation unit 2 outputs the chromosomal data from which the best evaluation value is obtained to the circuit generation unit 1 through the signal line 13 together with the maximum evaluation value, and the calculation / control processing unit 6-1 in the valid state. A signal indicating that a circuit adapted to the environment rather than the circuit 6-2, that is, an evolved circuit, is obtained is output to the reconstruction processing unit 4 via the signal line 14.
[0039]
In this fitness evaluation unit 2, the evaluation values of the calculation / control processing units 6-1 and 6-2 in the valid state are also obtained at the same time, and the maximum evaluation value obtained by the simulation is calculated and controlled in the effective state 6 Only when the evaluation value of the circuit of −1, 6-2 is exceeded, the above-described signals may be output to the circuit generation unit 1 and the reconstruction processing unit 4.
[0040]
Furthermore, by operating the fitness evaluation unit 2 during normal operation of the system, the evaluation values of the computation / control processing units 6-1 and 6-2 in the valid state are always obtained, and this evaluation value is appropriate. When the value falls below a certain reference value, it is determined that the arithmetic / control processing units 6-1 and 6-2 cannot cope with the environment, that is, the initial performance cannot be maintained, and the system automatically restarts the circuit. It is desirable to start the configuration process.
[0041]
On the other hand, the circuit generation unit 1 uses the chromosome data of the maximum evaluation value input from the fitness evaluation unit 2 as chromosome data to be candidates for the circuits of the next generation arithmetic / control processing units 6-1 and 6-2. (Step S3), and further sent from the fitness evaluation unit 2 together with the chromosome data to determine whether or not the circuit indicated by the chromosome data has sufficiently evolved. The obtained maximum evaluation value is compared with a preset reference value (step S4).
[0042]
If the maximum evaluation value is smaller than the reference value as a result of comparison in the circuit generation unit 1 (No in step S4), it is determined that the circuit has not sufficiently evolved. Are subjected to genetic processing as described below (step S5), and the fitness evaluation unit 2 sets a new chromosome data group for subsequent simulation (step S6).
[0043]
FIG. 6 is a diagram for specifically explaining the genetic processing by the evolutionary processing unit 3. Here, it is considered that chromosome data 41 to 44 having a total number of data n = 4 are input as chromosome data to be subjected to genetic processing as shown in block 61.
[0044]
The genetic processing in the evolution processing unit 3 is executed according to a genetic algorithm as described below. First, any chromosome data in the chromosome data 41 to 44 is selected. T Chromosome data selected and not selected T A selection process is performed to remove and enter. At this time, in order to keep the total number n = 4 of the chromosome data 41 to 44 in the initial state, the selected chromosome data T Chromosome data for the proliferated and proliferated portion T To be removed. For example, in the selection selection process from the block 61 to the block 62, the chromosome data 41 is selected and the chromosome data 44 is selected, and in the block 62, data having the same bit string as the chromosome data 41 is set as new chromosome data 44. ing.
[0045]
As reference values for selection and selection, the evaluation values of the chromosome data 41 to 44 are used. For example, the higher the evaluation value, the higher the probability of selection, and the lower the evaluation value, the easier it is to be deceived. The selection and selection of the chromosome data 41 to 44 is executed by the stochastic process.
[0046]
Next, a crossover process is performed in which arbitrary two bit strings are exchanged between two arbitrary chromosome data 41 to 44. For example, in the crossover process from the block 62 to the block 63, the bit string 45 and the bit string 46 are exchanged between the chromosome data 41 and the chromosome data 42, and the bit string 47 and the bit string are further exchanged between the chromosome data 43 and the chromosome data 44. 48 has been exchanged.
[0047]
Further, a mutation process for inverting an arbitrary bit string of arbitrary chromosome data 41 to 44 is performed. For example, in the mutation process from the block 63 to the block 64, the bit string 49 of the chromosome data 44 is inverted.
[0048]
The selection selection process, the crossover process, and the mutation process as described above are repeated until chromosome data 41 to 44 satisfying preset termination conditions are obtained, and finally obtained chromosome data 41 to 44 are used as the final generation, That is, the fitness evaluation unit 2 sets a new group of chromosome data for performing the next simulation.
[0049]
If the chromosome data bit string itself is changed in this way, the changed chromosome data may not make sense as a circuit of the arithmetic / control processing units 6-1 and 6-2. Therefore, it is necessary to include at least whether or not the chromosome data 41 to 44 make sense as a circuit of the arithmetic / control processing units 6-1 and 6-2 in the termination condition described above. The genetic processing is repeated until chromosome data 41 to 44 indicating circuits that can be simulated by the unit 2 are obtained. Further, the selection process, the crossover process, and the mutation process do not have to be repeated one by one as described above, and the order and number of each process can be arbitrarily determined.
[0050]
FIG. 7 shows a change in the circuit configuration of the arithmetic / control processing unit when chromosome data is changed by this genetic processing. A and B represent input signals, and C represents an output signal.
[0051]
For example, regarding the circuit 51 of the arithmetic / control processing unit 6-1 or 6-2 in which six functional blocks a to f are arranged, before the genetic processing is performed (before evolution), each functional block a to f is None of them are connected. At this time, by changing the chromosome data of the circuit 51 by genetic processing, the use states and connection states of the functional blocks a to f are changed as in the circuits 52 and 53. In this case, since the bit string itself of the chromosome data is changed, the entire circuit can be processed only by being connected to other functional blocks such as the functional blocks a and c of the circuit 52 and the functional block b of the circuit 53. In some cases, there is an unaffected part. Then, such genetic processing is repeated, and the use state and connection state of the last generation function blocks a to f are determined as in the circuits 54 and 55.
[0052]
Returning to the description, the evolutionary processing unit 3 outputs each chromosome data obtained by the above-described genetic processing to the circuit generation unit 1 via the signal lines 17-1 to 17-n. The circuit generation unit 1 sends the chromosome data input from the evolutionary processing unit 3 to the fitness evaluation unit 2 via the signal lines 10-1 to 10-n, and the fitness evaluation unit based on these new chromosome data In step 2, the simulation is continued.
[0053]
The processing of steps S2 to S6 as described above, that is, the evaluation value calculation of the circuit corresponding to each chromosome data in the fitness evaluation unit 2, the comparison between the maximum evaluation value and the reference value in the circuit generation unit 1, and the evolution processing unit 3 enables the genetic processing to the chromosome data in the circuit generator 1, fitness evaluation unit 2, and evolutionary processor 3 in parallel. When Repeat while letting.
[0054]
When the maximum evaluation value of the chromosome data obtained by the simulation of the fitness evaluation unit 2 becomes larger than the reference value set in the circuit generation unit 1 (Yes in step S4), the circuit indicated by the chromosome data As a result, the circuits of the arithmetic / control processing units 6-1 and 6-2 are actually reconfigured (step S7).
[0055]
At this time, the circuit is reconfigured for the invalid operation / control processing units 6-1 and 6-2, and after the reconfiguration is completed, the operation / control processing units 6-1 and 6-2 are enabled. By switching between / invalid each other, the operations of the reconfigured arithmetic / control processing units 6-1 and 6-2 are started instead of the arithmetic / control processing units 6-1 and 6-2 that have been in the valid state so far. (Step S8).
[0056]
In this case, first, the circuit generation unit 1 converts the chromosomal data whose maximum evaluation value is larger than the reference value into circuit configuration information according to the circuit configuration information bit format for actually changing the circuit configuration. The circuit configuration information is output to the reconfiguration processing unit 4 via the signal line 11.
[0057]
The reconfiguration processing unit 4 outputs the circuit configuration information input from the circuit generation unit 1 to the computation / control processing units 6-1 and 6-2 in an invalid state via the signal lines 18-1 and 18-1. In addition, a reconfiguration control signal required for circuit reconfiguration is generated, and signal lines 19-1 and 19-2 are connected to the computation / control processing units 6-1 and 6-2 in the invalid state. To output.
[0058]
The calculation / control processing units 6-1 and 6-2 in the invalid state are based on the circuit configuration information and the reconfiguration control information input from the reconfiguration processing unit 4, and the usage states and connection states of their own reconfigurable elements Change the circuit and reconfigure the circuit.
[0059]
When the reconfiguration of the circuits of the invalid operation / control processing units 6-1 and 6-2 is completed, the reconfiguration processing unit 4 puts the reconfigured operation / control processing units 6-1 and 6-2 into an effective state. At the same time, the calculation / control processing units 6-1 and 6-2 that have been in the valid state are switched to the invalid state. Further, the reconstruction processing unit 4 outputs the input control signal and the output control signal to the input control circuit 7 and the output control circuit 8 through the signal lines 20 and 21, respectively, and the signal lines 22-1 and 22 of the input control circuit 7 are output. -2 and signal lines 23-1 and 23-2, and signal lines 24-1 and 24-2 of the output control circuit 8 are switched between valid / invalid.
[0060]
As a result, the arithmetic / control processing units 6-1 and 6-2 whose circuits are reconfigured are replaced with the arithmetic / control processing units 6-1 and 6-2 that have been valid until then, and the arithmetic / control target 9. The processing for is started.
[0061]
As described above, in the system according to the present embodiment, the arithmetic / control processing units 6-1 and 6-2 that can reconfigure the circuit are provided in the arithmetic / control device 5, and the arithmetic / control device 5 is further provided. When it is necessary to adapt to the environment, the circuit generation unit 1 generates a circuit to be configured on the arithmetic / control processing units 6-1 and 6-2, and pays attention to chromosome data indicating the configuration of the circuit. The fitness evaluation unit 2 evaluates the fitness of the circuit with respect to the environment by performing a simulation when the circuit indicated by the chromosome data is configured on the arithmetic / control processing units 6-1 and 6-2. Based on this, the evolutionary processing unit 3 performs genetic processing on the chromosomal data to change and evolve the circuit generated by the circuit generation unit 1, and as a result, shows the configuration of the evolved circuit. Based on chromosome data Reconstructing the circuit of the arithmetic and control unit 6-1, 6-2 by the configuration processing unit 4.
[0062]
In this way, even when the computing / control device 5 in operation cannot be adapted to the environment or the initial performance cannot be maintained, the circuits of the computation / control processing units 6-1 and 6-2 are not affected. Reconfigured to adapt to the environment. In other words, since the arithmetic / control device 5 has an autonomous evolution function that autonomously changes the hardware configuration in response to a change in the environment, it takes time and labor to change the function of the system as in the past. There is no need. In addition, since the circuit configuration of the arithmetic / control processing units 6-1 and 6-2, that is, the hardware configuration of the arithmetic / control device 5 is directly changed, it is possible to cope with a large environmental change that cannot be dealt with by software change, and the execution speed. Can also be kept fast.
[0063]
The arithmetic / control processing units 6-1 and 6-2 are duplicated, and only one of them is enabled to perform processing on the arithmetic / control target 9, and the circuits of the arithmetic / control processing units 6-1 and 6-2 are performed. When reconfiguring, the operation of the computation / control processing units 6-1 and 6-2 in the valid state remains unchanged, and the circuit is reconfigured for the computation / control processing units 6-1 and 6-2 in the invalid state. Since the mutual valid / invalid are switched after the reconfiguration is completed, the processing of the arithmetic / control device 5 is performed for the reconfiguration of the circuits of the arithmetic / control processing units 6-1 and 6-2. There is no need to stop.
[0064]
Chromosome data is described by a bit string corresponding to the minimum unit of function change of the circuit of the arithmetic / control processing units 6-1 and 6-2. When the evolutionary processing unit 3 changes the circuit, the selection process Since the bit sequence of the chromosome data itself is changed by genetic processing such as crossover processing or mutation processing, simulation is performed on various circuits that can be realized in the arithmetic / control processing units 6-1 and 6-2. It is possible to respond flexibly to changes in the environment.
[0065]
Next, an example in which the above-described system is applied to an image recognition apparatus will be described with reference to FIG.
The image recognition apparatus includes an image recognition unit 71, a recognition rate evaluation unit 72, and a filter configuration change unit 73. The image recognition unit 71 includes a filtering unit 74 and a matching unit 75. Considering the relationship between this image recognition device and the system shown in FIG. 1, the image recognition unit 71 corresponds to the calculation / control device 5, and the filtering unit 74 corresponds to the calculation / control processing units 6-1 and 6-2. doing. The recognition rate evaluation unit 72 corresponds to the fitness evaluation unit 2, and the filter configuration change unit 73 corresponds to the circuit generation unit 1, the evolution processing unit 3, and the reconstruction processing unit 4. Further, the image signal corresponds to the calculation / control target 9, and calculation processing based on the image signal is performed. In this case, by providing a circuit composed of reconfigurable elements in the filtering unit 74, for example, the filter configuration such as the filter order and the band division width can be changed.
[0066]
When an image signal is input to the image recognition unit 71, a filtering process is performed on the image signal by the filtering unit 74 to extract features by performing, for example, edge enhancement, image sharpening, and noise removal, Based on the extracted features, the matching unit 75 performs matching with a predetermined recognition target to output a recognition result.
[0067]
The recognition result is input to the recognition rate evaluation unit, and is filtered by the recognition rate evaluation unit 72 and the filter configuration change unit 73, for example, when the recognition rate is lowered by changing characters, figures, or other recognition targets. The new filter configuration of the unit 74 is simulated, and the filter configuration of the filtering unit 74 is changed based on the result.
[0068]
By doing in this way, the structure of the filtering part 74 is changed according to the change of recognition object, and the filtering process with respect to an image signal can always be performed optimally, Therefore It becomes possible to maintain a high recognition rate. Furthermore, when the optimum filter configuration is not known in advance as in the case where the recognition target is unknown, the processing is started for the time being, and if the simulation is immediately performed and the filter configuration of the filtering unit 74 is changed, Therefore, the filter configuration is changed to an optimum one. That is, the image recognition apparatus learns an optimum filter configuration for an unknown recognition target.
[0069]
(Second Embodiment)
Figure 9 These are block diagrams which show the structure of the system concerning the 2nd Embodiment of this invention. In the following description, portions corresponding to those in FIG. 1 are denoted by the same reference numerals, and description will be made focusing on differences from the first embodiment.
[0070]
In the present embodiment, a plurality of arithmetic / control processing units are configured by combining multiplexing and parallelization. That is, the arithmetic / control device 5 is provided with n arithmetic / control processing units 6-1 to 6-n (multiplexing), and during normal operation, all these arithmetic / control processing units 6-1 to 6-1. 6-n is operated (parallelization). At this time, the output control circuit 8 outputs, for example, output signals 24-1 to 24-n of the arithmetic / control processing units 6-1 to 6-n. of The sum of weights is output as a calculation / control signal. As will be described later, in this system, it is necessary to temporarily stop a part of the arithmetic / control processing units 6-1 to 6-n for circuit reconfiguration. Configure to prevent errors.
[0071]
Here, as in the first embodiment, even if the same and the same number of reconfigurable elements are provided in each circuit of the arithmetic / control processing units 6-1 to 6-n, each circuit can be reconfigured differently. An element may be provided. In the latter case, the fitness evaluation unit 2 defines element models corresponding to all the reconfigurable elements provided in the circuits of the arithmetic processing units 6-1 to 6-n.
[0072]
In this system, when the circuit is reconfigured, the simulation is performed with all the arithmetic / control processing units 6-1 to 6-n being operated, and the arithmetic / control to reconfigure the circuit according to the simulation result. processing Part select. And the selected computation / control process Part Temporarily stop operation, and other computation / control processing Part is The selected computation / control process while still operating Part Other computation / control processing in operation after the circuit is reconfigured and the reconfiguration is complete Department and Resume operation to synchronize.
[0073]
In this way, the circuits of the plurality of arithmetic / control processing units 6-1 to 6-n can be reconfigured at the same time, and each circuit has a different configuration, that is, has a different function. Therefore, the hardware configuration of the arithmetic / control device 5 can be changed more flexibly than in the first embodiment, and it becomes possible to appropriately cope with changes in the environment. In addition, a sufficient effect can be obtained only by reconfiguring the necessary minimum arithmetic / control processing units 6-1 to 6-n.
[0074]
【The invention's effect】
As described above, according to the present invention, the adaptability of the circuit configured on the calculation / control unit with respect to the environment is evaluated, and the circuit of the calculation / control unit is reconfigured based on the evaluation result. The hardware configuration is changed autonomously according to environmental changes.
[0075]
At this time, a circuit to be configured on the arithmetic / control unit is generated, the adaptability to the environment when the circuit is configured on the arithmetic / control unit is evaluated, and the circuit is changed based on the evaluation result. The circuit that has evolved as a result of this process is reconfigured in the calculation / control means, so that it is possible to respond flexibly and appropriately to changes in the environment.
[0076]
Multiplexing calculation and control means, and reconfiguration processing means without resuming calculation and control means processing, the circuit is reconfigured, improving the fitness only for the environment while continuing the processing for the calculation and control target Can be made.
[0077]
The circuit generation unit generates a plurality of circuits, the fitness evaluation unit evaluates the plurality of circuits, and the evolutionary processing unit changes the plurality of circuits by a genetic algorithm based on the evaluation results of the plurality of circuits. Therefore, it is possible to analyze various circuits that can be realized.
[Brief description of the drawings]
FIG. 1 is a block diagram showing the configuration of a system according to a first embodiment of the present invention.
FIG. 2 is a diagram for explaining keywords of a description language of a hardware configuration in the embodiment;
FIG. 3 is a diagram for explaining keywords of a description language of a hardware configuration in the embodiment;
FIG. 4 is a diagram for explaining chromosome data in the embodiment
FIG. 5 is a flowchart for explaining circuit reconfiguration processing in the embodiment;
FIG. 6 is a diagram for explaining genetic processing in the embodiment;
FIG. 7 is a diagram showing an example of changing the circuit configuration by changing chromosome data in the embodiment;
FIG. 8 is a block diagram showing an example in which the embodiment is applied to an image recognition apparatus;
FIG. 9 is a block diagram showing a configuration of a system according to a second embodiment of the present invention.
FIG. 10 is a diagram showing an example of a conventional system
[Explanation of symbols]
1 ... Circuit generator
2 ... Fitness evaluation section
3 ... Evolutionary processing department
4 ... Reconfiguration processing unit
5 ... Calculation / control device
6-1 to 6-n. Calculation / control processing section
7. Input control device
8 ... Output control device
9 ... Calculation / control target

Claims (3)

Each of the circuits configured to be reconfigurable, and a plurality of calculation / control means for performing calculation and control of the calculation / control target simultaneously,
A circuit generating unit that generates a circuit to be configured on the arithmetic / control unit and outputs circuit configuration information indicating the configuration of the circuit;
Fitness evaluation means for evaluating the fitness of the circuit with respect to the environment when the circuit generated by the circuit generation means is configured on the calculation / control means;
Based on the evaluation result of the fitness evaluation means, evolution processing means for performing a process of changing and evolving the circuit generated by the circuit generation means,
Circuit configuration information indicating the circuit configuration evolved by the evolution processing means is received from the circuit generation means, and only the calculation / control means selected from the plurality of calculation / control means based on the circuit configuration information An autonomous evolution system comprising: a reconfiguration processing unit configured to reconfigure the circuit of the selected calculation / control unit after being temporarily stopped.   2. The circuit generation unit according to claim 1, wherein the circuit generation unit changes a circuit to be generated using any one of a function block level, a circuit configuration information bit level, a logic gate level, and a hardware description language keyword level as a minimum change unit. Autonomous evolution system described in 1. The circuit generation means describes each of the circuits by a plurality of chromosome information composed of bit strings corresponding to the minimum function change unit,
The evolutionary processing means, when changing a plurality of circuits by transfer algorithm heritage, select one of the plurality of chromosomes information, a first process to remove the chromosome information that has not been selected, the The second process for exchanging an arbitrary part of a bit string between a plurality of chromosome information and a third process for inverting an arbitrary part of the bit string of the plurality of chromosome information are performed in combination. Autonomous evolution system described in 1.

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