JPH10307649A - Computer system and its initializing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten the time needed for initializing processes of devices by advancing the initializing processes in parallel. SOLUTION: Commands for initialization are issued in order for the devices such as a KBC(keyboard controller) 17, an HDD(hard disk drive) 18, and a display controller 14. The KBC 17, HDD 18, and display controller 14 generate command end interruption signals after command processes for initialization. A next command is issued in order from a device having generated a command end interruption signal. Thus, the initializing processes of the respective devices are advanced according to the command end interruption signals from the devices to initialize the devices in parallel in consideration of wait times for the initialization of the respective devices.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a computer system and a method for initializing the same.

[0002]

2. Description of the Related Art Generally, an initialization process of a personal computer is performed by sequentially initializing a memory and various I / Os mounted on the computer. For example, in a notebook type personal computer, FIG.
As shown in (1), the initialization process is executed in the following procedure by the POST routine of the BIOS.

(1) Initialization of memory and chipset (step S11) (2) Keyboard controller (KBC) and internal /
Initialization of external keyboard (step S12) (3) Initialization of display controller and external CRT
(Step S12) (4) Initializing the hard disk (Step S14) (5) Initializing the optional device (Step S15) Here, in the initialization processing of each device such as the keyboard controller, the display controller, and the hard disk, , The POST routine issues a command to the device many times. It takes a certain time for the device that has received the command to complete the processing corresponding to the command. For this reason, PO
Each time a command is issued, the ST routine polls the device that issued the command to check whether the command processing has been completed. Then, after confirming the end of the command processing, the POST routine issues the next command to the device.

As described above, in the initialization processing of each device, the timing of issuing the next command is delayed by the time required for the command processing of the device. During this waiting time, the POST routine can perform initialization of another device.

However, conventionally, since the initialization processing of a plurality of devices is performed sequentially, the waiting time in the initialization processing of each device cannot be effectively used. Therefore, the time required to initialize the entire system is the sum of the time required to initialize each device mounted on the system (including the waiting time), and there is a problem that the initialization process of the computer takes much time. Was.

[0006] Japanese Patent Application Laid-Open No. 7-38591 discloses a technique for performing initialization of other devices 1 to 4 during a wait period necessary for performing an initialization operation of a token ring LAN adapter. I have. This Japanese Patent Laid-Open No. 7-
FIG. 8 shows an initialization processing operation by the method of No. 38591.

As can be seen from FIG. 8, the initialization processing of the devices 1 to 4 is executed during a wait period necessary to execute the initialization operations F1, F2, F3, F4, F5 of the token ring LAN adapter. You. As a result, the initialization processing can be performed in parallel, and the initialization processing time can be reduced.

However, in the method disclosed in Japanese Patent Laid-Open No. 7-38591, the initialization processing of the devices 1 to 4 is performed sequentially, so that the initialization processing can be performed in parallel only for two devices. Therefore, processing of three or more devices cannot be performed in parallel. Therefore, for example, it is not possible to perform an operation of performing the initialization processing of the device 2 during a wait period necessary for the initialization operation of the device 1.

As described above, the method disclosed in Japanese Patent Application Laid-Open No. 7-38591 assumes a system configuration in which the wait period required for the initialization operation of a specific device is significantly longer than that of another device. Even when applied to a system configuration such as a personal computer in which each of a plurality of devices requires a wait period for its initialization operation, a sufficient effect cannot be obtained.

[0010]

As described above, in the prior art, only the initialization processing of two devices, a specific device and the other device, can be performed in parallel. In the case of a system configuration requiring a wait period for the initialization operation, it has been difficult to sufficiently reduce the initialization time.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and allows initialization processing of a plurality of devices to proceed in parallel by considering the wait periods of the plurality of devices. It is an object of the present invention to provide a computer system capable of sufficiently reducing the time required for processing and an initialization method thereof.

[0012]

According to the present invention, there is provided a computer system having a plurality of devices and executing an initialization process of the devices when power is turned on. Means for issuing commands sequentially, and detecting the end of command processing for each of the devices by using command end interrupt signals from the plurality of devices. And a command issuing means for issuing the above command.

In this computer system, in order to execute initialization processing of each of a plurality of devices in parallel, a configuration is employed in which the end of command processing is detected for each device by using a command end interrupt signal from each device. Have been.

That is, first, commands for initialization are sequentially issued to a plurality of devices to be subjected to parallel initialization processing. Each device executes a command process for the initialization operation, and upon completion, generates the above-described command end interrupt signal. Then, the next command is issued in order from the device that has generated the command end interrupt signal. In this way, by proceeding the initialization processing of each device in accordance with the command end interrupt signal from each of the plurality of devices, in a state in which the waiting time for the initialization operation of each of the plurality of devices is considered, The initialization of the plurality of devices can be performed in parallel.

According to another aspect of the present invention, in a computer system having a plurality of devices and executing initialization processing at power-on, a transition from a current command processing to a next command processing is performed for each of the plurality of devices. Means for detecting the timing at which the next command processing can be performed for each device using the counter value of each of a plurality of counters for managing the time required until the next command processing has been detected. Command issuing means for issuing a next command for the initialization in order from the device, and means for resetting the value of a counter corresponding to the device to which the command is issued each time a command is issued by the command issuing means. It is characterized by having.

In this computer system, a counter value of a counter prepared for each device is used in place of the above-described interrupt signal, whereby the timing at which the transition to the next command processing can be detected for each device is detected. Then, the initialization process of each device proceeds in accordance with the operation. Also in this case, it is possible to execute the initialization of the plurality of devices in parallel while considering the waiting time for the initialization operation of each of the plurality of devices.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a configuration of a computer system according to an embodiment of the present invention.
The computer system is a portable personal computer of a notebook type or a laptop type, and includes a processor bus 1, a PCI bus 2, an ISA bus 3, a CPU 11, a host-PCI bridge device 12, a main memory 13 on a system board. , Display controller 14, video memory (VRAM) 1
5, a PCI-ISA bridge device 16, a keyboard controller (KBC) 17, a hard disk drive (HDD) 18, a BIOS-ROM 19, and the like.

The CPU 11 is, for example, a microprocessor “Pent” manufactured and sold by Intel Corporation in the United States.
ium "etc. This CPU 11
Processor bus 1 directly connected to the input / output pins of
It has a 4-bit data bus.

The main memory 13 is a memory device for storing an operating system, a device driver, an application program to be executed, processing data, and the like, and includes a plurality of DRAMs.
The main memory 13 is connected to the host-PCI bridge device 12 via a dedicated memory bus having a 32-bit or 64-bit data bus. The data bus of the processor bus 1 can be used as the data bus of the memory bus. In this case, the memory bus includes an address bus and various memory control signal lines.

The host-PCI bridge device 12 is a bridge LS that connects between the processor bus 1 and the PCI bus 2.
I, which functions as one of the bus masters of the PCI bus 2. The host-PCI bridge device 12 has a function of bidirectionally converting a bus cycle including data and addresses between the processor bus 1 and the PCI bus 2 and a function of controlling access to the main memory 13 via the memory bus. And so on.

The display controller 14 is one of the PCI devices, and includes an internal LCD 142 and an external CR.
T143 is controlled, and the display data written in the VRAM 15 is displayed on them.

The PCI-ISA bridge device 16 is a PC
This is a bridge LSI that connects the I bus 2 and the ISA bus 3, and includes an interrupt controller 161 and a system counter 162. The interrupt controller 161 receives a hardware interrupt request signal from each device on this system and
1 to issue an interrupt signal INTR. The system counter 162 is a counter serving as an operation reference of the entire system.

In the initialization processing of the present embodiment, the hardware interrupt request signal or the counter value of the system counter 162 is used to perform initialization processing of a plurality of devices in parallel. Details of this initialization processing will be described with reference to FIG.

Keyboard controller (KBC) 17
Controls the internal keyboard 171, the mouse 172, and the external keyboard. In the BIOS-ROM 19,
Contains POST routines for hardware initialization and testing, BIOS drivers for providing various functions for hardware access to operating systems and application programs, and VGA drivers for controlling the display controller 14. Have been.

The POST routine is a program that is executed first when the system is powered on, and tests and initializes the main memory 13 and each I / O device in the system. In this case, the initialization processing of these devices is executed in parallel in consideration of the waiting time required for the initialization operation of each of the devices. The management of the waiting time required for the initialization operation of each device and the switching of the device to be initialized are performed at the timing of generation of the above-described hardware interrupt request signal or the counter value prepared for each device and the counter of the system counter 162. It is controlled using the result of comparison with the value.

First, referring to FIGS. 2 and 3, description will be given of an initialization processing operation when initialization processing of a plurality of devices is performed in parallel using a hardware interrupt request signal.

FIG. 2 is a flowchart showing the initialization processing procedure executed by the POST routine, and FIG. 3 is a timing chart showing the progress of the initialization processing.
The POST routine includes a main routine and first and second routines.
This is composed of the following two interrupt processing routines. The first interrupt processing routine includes the KBC 17 and the internal /
The external keyboards 171 and 173 and the mouse 172 are initialized, and are activated in response to a hardware interrupt request signal from the KBC 17. The second interrupt processing routine is for initializing the HDD 18.
It is started in response to a hardware interrupt request signal from the HDD 18.

When the power of the computer system is turned on, the POST routine first initializes a conventional area of the main memory 13 (setting an interrupt vector for activating the first and second interrupt processing routines,
The setting of a work area and a stack area) and the initialization of a chip set (bridges 12, 16 and the like) are performed (step S101).

Next, the POST routine executes the KBC1
7, HDD 18, and display controller 14
Command (KB) to the KBC 17 and the HDD 18 in order to execute
C command 1 and HDD command 1) are sequentially issued (steps S102 and S103). Thereby, KBC17
The HDD 18 starts command processing as shown in FIG. 3 and generates a hardware interrupt request signal indicating the completion when the command processing ends.

The POST routine starts the initialization of the display controller 14 and the process of detecting an external CRT (step S104). When a hardware interrupt request signal is issued from the KBC 17 during the initialization processing of the display controller 14, the control is transferred from the currently executed main routine to the first interrupt processing routine by the software interrupt function of the CPU 11. .

Each time the first interrupt processing routine is activated, the first interrupt processing routine checks the status of the previously issued KBC command, and then executes the next command necessary for the subsequent remaining KBC initialization processing. Issue and return to the main routine (step S105).

Similarly, when a hardware interrupt request signal is issued from the HDD 18, the software interrupt function of the CPU 11 transfers the control from the currently executing routine to the second interrupt processing routine. Second
Interrupt processing routine checks the status of the previously issued HDD command each time it is started, issues the next command necessary for the subsequent remaining HDD initialization processing, and The process returns to the routine (Step S106).

As described above, the first and second interrupt processing routines correspond to the KBC 17 and the HDD 1 respectively.
8 is executed intermittently in accordance with the end timing of each command processing. Thereby, KBC17 and H
The initialization process of the display controller 14 can be performed during the waiting time required for the command processing operation of each of the DDs 18, and the initialization of the display controller 14, the KBC 17, and the HDD 18 can be performed in parallel. .

In the main routine, when the initialization processing of the display controller 14 is completed, the initialization processing for the extended memory area of the main memory 13 is started (step S107). Even during the initialization processing of the extended memory area, the first and second interrupt processing routines are executed each time a hardware interrupt signal is generated.

When the initialization of the extended memory area by the main routine and the initialization of the KBC and HDD by the first and second interrupt processing routines are completed, the POS
After executing the initialization of the optional device, the T routine boots the operating system (steps S109 and S110).

As described above, in this initialization processing method, the initialization processing of the display controller 14, the KBC 17 and the HDD 18 is advanced in accordance with the command end interrupt signal from the KBC 17 and the HDD 18, respectively. 14, the KBC 17 and the HDD 18 can be initialized in parallel.

The initialization processing of the display controller 14 may be executed by using an interrupt routine. In this case, while the initialization process of the extended memory area is being performed in the main routine,
Display controller 14, KBC17 and HD
The initialization of each of D18 will be executed in parallel.

Next, referring to FIGS. 4 and 5, a counter value prepared for each device and a system counter 162 will be described.
The initialization processing operation in the case where the initialization processing of a plurality of devices is performed in parallel using the result of comparison with the counter value of FIG.

FIG. 4 is a flowchart showing the initialization processing procedure executed by the POST routine, and FIG. 5 is a timing chart showing the progress of the initialization processing.
The POST routine includes a main routine and three subroutines A, B, and C. Subroutine A
Are the KBC 17 and the internal / external keyboard 171,1
It initializes 73 and the mouse 172, and is started in response to a subroutine call from the main routine. The subroutine B is for initializing the HDD 18, and is started in response to a subroutine call from the main routine. The subroutine C initializes the display controller 14 and detects an external CRT, and is started in response to a subroutine call from the main routine.

The main routine consists of KBC 17, HDD 1
8 and a software counter (KBC counter, HDD counter, display controller (D
By comparing the counter value of the (ISP) counter) with the counter value of the system counter 162 in order, a device that can shift to the next command processing is determined. And
Call the subroutine for that device.

The time required for the corresponding device to execute the current command processing, that is, the time during which the next command processing can be started is set in each software counter.
For setting the counter value for each software counter,
This is executed by a subroutine for initializing a device corresponding to the software counter. Until the subroutine is started, the counter value for each software counter is 0, that is, the command processing can be started at any time.

When the power of the computer system is turned on, the POST routine first initializes the main memory 13 and the chipset (bridges 12, 16 and the like), and then sets the KBC counter value and the HDD counter value. , And the DISP counter value are sequentially compared with the current counter value of the system counter 162 (system current value).
Processing for detecting for each device whether or not the next command processing can be started (steps S201, S202, S20
Start 3).

In this case, first, when the system current value is K
It is checked whether or not the value is equal to or greater than the BC counter value (step S201). If the system current value is equal to or greater than the KBC counter value, subroutine A is called, while if the system current value is smaller than the KBC counter value, H is set.
The process proceeds to the check of the DD counter value.

Immediately after the power is turned on, the value of the KBC counter is the initial value 0, so that the system current value is KB
It is larger than the C counter value. Therefore, the KBC initialization process (step S300) is executed by the subroutine A.

In the subroutine A, first, the status check of the command processing for the KBC command issued in the previous subroutine A is performed, and then the next command for KBC initialization is issued (step S3).
01, S302). Next, the KBC counter value is updated (step S303).

Here, "current system current value"
+ N "is set in the KBC counter. "N"
The processing corresponding to the command issued in S302 is performed by KBC1.
7 shows the minimum time (KBC interval value) until the end of 7 and the next command can be received. This time is predetermined for each command.

When the update of the KBC counter value is completed, the address to be called in the next KBC processing is set (step S304), and the process returns to the main routine.

In the main routine, it is checked whether or not the system current value is equal to or larger than the HDD counter value (step S202). If the system current value is equal to or larger than the HDD counter value, the subroutine B is called. According to the same procedure as the KBC initialization processing, the HDD initialization processing such as the status check of the previous command processing, the issuance of the next command, and the resetting of the HDD counter (step S400) is performed.

When returning from the subroutine B to the main routine, it is checked whether the system current value is equal to or greater than the DISP counter value (step S203). If the system current value is equal to or greater than the HDD counter value, the subroutine C is executed. The display controller initialization processing (step S500), such as the status check of the previous command processing, the issuance of the next command, and the resetting of the DISP counter, is performed.

By using the counter value of each device in this manner, the timing at which the next command processing can be performed is detected for each device, and the initialization process of each device is performed as shown in FIG. Can proceed.

In the example of FIG. 5, the first KBC initialization process (KBC process 1) and the first HDD initialization process (H
When the DD processing 1) and the first display initialization processing (DISP processing 1) are completed, the system current value is set to the KBC set in the first KBC initialization processing.
The case where the counter value (T2) has been exceeded and the second KBC initialization process (KBC process 2) is performed after T2 is shown.

The third KBC initialization process (KB
The C process 3) is performed after waiting for the KBC counter value (T3) set in the second KBC initialization process. Second display initialization processing (DI
During the period from the end of the SP process 2) to the start of the KBC process 3, the main routine continues to loop,
It goes into a waiting state.

In this waiting period, the above-described initialization processing of the extended memory area can be performed. In this case, the POST routine initializes the conventional area of the main memory 13 and sets the chip set (bridge 12,
16), the process proceeds to the process of FIG.

Here, the aforementioned KBC counter, HD
In addition to the D counter and the DISP counter, a memory counter is prepared for controlling the timing at which the subroutine C for initializing the extended memory area is executed.

When the system current value becomes equal to or greater than the memory counter value, subroutine C is executed, and a memory initialization process (step S600) is started. Each time the subroutine C is executed, for example, a memory check of 1 Mbyte (step S601), resetting of the memory counter (step S602), and setting for the next memory initialization process (step S603) are performed.

In the process of resetting the memory counter, “current system current value + 1” is set in the memory counter. The value “1” is set in step S
This is to ensure that the memory initialization process (step S600) is executed whenever the counter check of 204 is performed. This makes it possible to perform the memory initialization process during a period when the initialization process of another device cannot be performed.

Here, whether or not it is possible to shift to the next command processing is detected by comparing a counter prepared for each device with a system counter. However, the counter prepared for each device is defined as a down counter. If the time required for the command processing is set therein, it is possible to detect whether or not it is possible to shift to the next command processing on condition that the down counter value = 0. Further, a counter in the CPU 11 can be used as the system counter.

[0058]

As described above, according to the present invention, it is possible to proceed with the initialization processing of a plurality of devices in parallel by considering the wait period of each of the plurality of devices. Can be sufficiently reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an entire computer system according to an embodiment of the present invention.

FIG. 2 is an exemplary flowchart illustrating a first initialization processing procedure applied to the computer system of the embodiment.

FIG. 3 is an exemplary timing chart showing the progress of a first initialization process of the computer system according to the embodiment;

FIG. 4 is an exemplary flowchart illustrating the procedure of a second initialization process applied to the computer system of the embodiment.

FIG. 5 is an exemplary timing chart showing the progress of a second initialization process of the computer system according to the embodiment;

FIG. 6 is an exemplary flowchart illustrating the procedure of a third initialization process applied to the computer system of the embodiment.

FIG. 7 is a flowchart showing a procedure of a conventional initialization process of a computer system.

FIG. 8 is a timing chart showing the progress of a conventional parallel initialization process.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Processor bus 2 ... PCI bus 3 ... PCI bus 11 ... CPU 14 ... Display controller 17 ... Keyboard controller 18 ... HDD 19 ... BIOS ROM 161 ... Interrupt controller 162 ... System counter

Claims (8)

[Claims] 1. A computer system having a plurality of devices and executing initialization processing of the devices when a power is turned on, means for sequentially issuing a command for initialization to each of the plurality of devices, Command issuing means for detecting the end of command processing for each of the devices by using command end interrupt signals from the plurality of devices, and issuing the next command for initialization in order from the device for which command processing has been completed A computer system comprising: 2. A plurality of interrupt processing programs for performing initialization processing of each of the plurality of devices, the plurality of interrupt processing programs being executed by a CPU of the computer system in response to generation of a command end interrupt signal from a corresponding device. An interrupt processing program is prepared, and the next command issuance to the device that has completed the command processing is performed by an interrupt processing program executed in response to the generation of a command end interrupt signal from the device. The computer system according to claim 1, wherein 3. A plurality of interrupt processing programs corresponding to each of the plurality of devices, further comprising means for causing the CPU to start a memory initialization process of the computer system, and in parallel with the memory initialization process. 3. The computer system according to claim 2, wherein: 4. A computer system having a plurality of devices and performing initialization processing of the devices when power is turned on, wherein a time required for a transition from a current command processing to a next command processing for each of the plurality of devices. Means for detecting the timing at which transition to the next command processing can be performed for each device using the counter value of each of a plurality of counters for managing Command issuing means for issuing the next command for the initialization, and means for resetting the value of the counter corresponding to the device to which the command is issued each time a command is issued by the command issuing means. A computer system characterized by the above-mentioned. 5. A plurality of sub-programs for initializing each of the plurality of devices, and a main program for determining a sub-program to be executed by sequentially referring to counter values of the plurality of counters are provided. 5. The computer system according to claim 4, wherein issuing the next command to the device that has completed the command processing and resetting the counter value are executed by a sub-program started by the main program. 6. A memory initialization sub-program for executing a memory initialization of the computer system by dividing the memory into a plurality of times in units of a predetermined memory size, wherein the main program comprises a memory initialization sub-program. The computer system according to claim 5, wherein the sub-program is executed periodically. 7. An initialization method for initializing a computer system when the power of the computer system is turned on, and sequentially issues a command for the initialization to each of a plurality of devices provided in the computer system. Detecting the end of command processing for each device using command end interrupt signals from the plurality of devices, and issuing the next command for initialization in order from the device for which command processing has been completed. Characterized initialization method. 8. An initialization method for initializing a computer system when the power of the computer system is turned on, wherein the initialization is performed for each of a plurality of devices provided in the computer system from a current command processing to a next command processing transition. Using the counter values of a plurality of counters that manage the time required, the timing at which the transition to the next command process can be detected for each device is detected, and the next device for initialization is started in order from the device that can transition to the next command process. And resetting a counter value corresponding to the issued command to a counter corresponding to the device that issued the command.