JPH10306397A - Method for forming circuit by plating - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method especially for forming finely spaced circuit elements on a semiconductor substrate by plating. SOLUTION: A resist mask 13 is formed on the surface of a first electrode 12 by a common electrode formed on the surface of a semiconductor substrate 11. The substrate 11 is set in an electrolyte, and a DC power source 15 is connected between the substrate and a second electrode 14 opposed to the mask 13 so that the second electrode 14 is used as an anode. A plating layer is grown until a bridge layer 161 is formed on the mask 13 surface, the polarity of the DC power source is inverted when the growth is detected from a change in resistance value between the first electrode 12 and the second electrode 14 to eliminate the bridge layer 161, and the circuit-element part by the plating layer remaining in the opening of the mask 13 is left on the substrate 12.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a circuit network at a minute interval such as a planar inductor for a micro power supply on a semiconductor substrate by Cu plating.

[0002]

2. Description of the Related Art In forming a semiconductor integrated circuit device, it is necessary to form various circuit elements on a semiconductor substrate by plating of Cu or the like. For example, a micro-planar inductor is formed by Cu plating, and in the forming means, a mask having a pattern formed by an opening corresponding to the shape of the target inductor is provided on the surface of the semiconductor substrate, and the mask is formed. After growing a Cu plating layer corresponding to the opening pattern and removing the mask, Cu
The plated inductor remains.

However, when circuit elements are formed by Cu plating by such means, there is non-uniformity in the resist film thickness constituting a mask on which a circuit pattern is formed.
Further, the plating layer is not sufficiently uniform, so that a plating layer may be grown to a depth greater than the depth of the opening of the mask pattern. In such a case, the interconnection between adjacent circuit networks on the surface of the mask pattern may occur. A short circuit (bridging) occurs between the plating layers.

Here, the thickness of the plating growth layer is controlled by controlling the plating time. However, if it is intended to surely prevent the occurrence of bridging due to the above-mentioned problems, a sufficient thickness is required. Therefore, it is difficult to reliably form, for example, a planar inductor with a highly reliable Cu plating layer.

[0005]

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and a circuit network in which circuit elements such as, for example, inductors, in particular, circuit elements are formed at minute intervals on a semiconductor substrate is formed by a resist or the like. An object of the present invention is to provide a circuit forming method by plating that is configured by Cu plating using the configured mask pattern.

[0006]

According to a method of forming a circuit by plating according to the present invention, a mask having a circuit pattern formed on a surface of a first electrode on a substrate is formed and set in an electrolytic solution. A voltage of a predetermined polarity is applied between the second electrode and the first electrode facing the mask to grow a plating layer corresponding to the mask pattern. Then, a plating layer is grown until a bridge layer for short-circuiting circuit elements corresponding to the mask pattern is formed. Then, the polarity of the voltage applied between the first and second electrodes is reversed, and the grown plating layer is eluted into the electrolytic solution. In this plating layer elution step, the plating layer is formed on the mask pattern. Elute the bridge layer portion that short-circuits the circuit element.

That is, after a plating layer is formed until a film thickness equal to or greater than the depth of the opening of the mask pattern is formed, the polarity of the plating voltage is reversed to form a bridging portion formed on the surface of the mask. Is eluted in the electrolyte,
A target, for example, a planar inductor is formed with high precision and reliability. In particular, even when the thickness of the resist constituting the mask is nonuniform and the uniformity of the plating itself is insufficient, bridging is reliably prevented.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the accompanying drawings. FIG. 1 illustrates a process of forming a circuit network such as a planar inductor, for example, and is used as a common electrode on the surface of a semiconductor substrate 11 on which a circuit network is to be formed as shown in FIG. The layer of the first electrode 12 to be formed is formed. Then, a photoresist layer is formed on the surface of the layer of the first electrode 12, exposed and developed with a predetermined circuit pattern, and thereby a mask having an opening corresponding to the circuit pattern is formed.
Form 13.

The semiconductor substrate on which the mask 13 is formed as described above
Reference numeral 11 denotes an electrode provided in an electrolytic solution in a plating bath (not shown). In this state, a second electrode 14 serving as a counter electrode is set at a position facing the mask 13 of the semiconductor substrate 11. A DC power supply is provided between the second electrode 14 and the first electrode 12.
15 is connected to the second electrode 14 during plating.
Is set to be an anode.

As described above, when set in the electrolytic solution with the DC power supply 15 connected between the first electrode 12 and the second electrode 14, the first electrode corresponding to the opening of the mask 13 On the surface of 12, a plating layer 16 of Cu is grown.

In this state, if the uniformity of the plating itself is insufficient and the thickness of the resist constituting the mask is uneven as described above, the plating layer 16 grows to a sufficient thickness as a circuit element. It is difficult to reliably recognize whether or not it has been done.

Therefore, in this embodiment, this voltage application state is further continued, and the plating layer 16 is further grown. The thickness of the plating layer 16 is greater than the depth of the opening of the mask 13. Then, as shown in FIG. 3B, this plating layer is grown as shown by the arrow over the opening of the mask 13 so that adjacent openings on the surface of the mask 13 are short-circuited. The bridging layer 161 is formed. When the bridge layer 161 is formed in this manner, a normal circuit network cannot be formed on the semiconductor substrate 11 as it is.

Therefore, in this embodiment, as shown in FIG. 2C, a DC power supply 151 connected between the first electrode 12 and the second electrode 14 is a DC power supply 151 with the polarity inverted. . That is, the first electrode 12 is used as an anode and the second electrode 14
Is used as the cathode, the plated layer
The bridge layer 161, especially on the surface, of the 16 is eluted into the electrolyte. Then, the bridge layer 161 is eluted and eliminated, and the plating layer 16 in the opening of the mask 13 is left. For example, an inductor is formed on the semiconductor substrate 11 in a reliable shape. That is, a highly reliable circuit network is formed with high accuracy.

In the step of forming such a plating layer, it is necessary to reliably detect that the bridge layer 161 has been formed on the surface of the mask 13. Here, looking at the change in the plating time and the resistance value between the second electrode 14 and the first electrode 12,
As shown in FIG. That is, the second electrode 14 corresponds to the area of the conductive portion facing the second electrode 14.
The resistance between the first electrode 12 and the first electrode 12 decreases. Specifically, as the area of the bridge layer 161 on the surface of the mask 13 increases, the resistance between the second electrode 14 and the first electrode 12 decreases. Decrease in resistance value.

Therefore, by monitoring the resistance value between the second electrode 14 and the first electrode 12 and detecting a change in the resistance value indicated by A in FIG. The formation of the bridge layer 161 can be confirmed. At this point, the state shown in FIG. 1B is recognized, and the plating growth step is completed. Then, as the completion of the plating growth step is confirmed, the DC power supply 151 is inverted as shown in FIG.
Is connected between the second electrode 14 and the first electrode 12 to elute the plating layer.

The resistance value between the first electrode 12 and the second electrode 14 is monitored, and it is confirmed that the resistance value is sufficiently increased and stabilized. It is possible to determine the disappearance of the upper bridge layer 161 due to elution, and in this state, it is confirmed that a circuit network corresponding to the pattern of the mask 13 has been formed. Thereafter, the resist 13 is removed to complete the circuit network.

[0017]

As described above, according to the present invention, a Cu plating layer having a stabilized film thickness is formed in a state in which the occurrence of a bridge layer between circuit elements is reliably eliminated. The reliability of the network is reliably ensured. The state in which the bridge layer is formed on the mask surface is the first and second states.
By monitoring the resistance value between the electrodes of the DC power supply, it is possible to reliably recognize the timing, and accurately grasp the timing of the polarity inversion of the DC power supply, thereby simplifying the manufacturing process and ensuring reliability. .

[Brief description of the drawings]

FIGS. 1A to 1C are diagrams illustrating an example of one embodiment of the present invention, in which a plating layer and a plating solution are omitted, and a change state of a plating layer is sequentially shown.

FIG. 2 is a diagram showing a change in a resistance value between a first electrode and a second electrode in the above embodiment in relation to a plating time.

[Explanation of symbols]

11 ... semiconductor substrate, 12 ... first electrode, 13 ... mask, 14 ... second electrode, 15, 151 ... DC power supply, 16 ... plating layer, 161 ...
Bridge layer.

Claims (2)

[Claims] A mask forming step of forming a mask on which a circuit pattern is formed on a surface of a first electrode on a substrate; setting the substrate on which the mask is formed in an electrolytic solution;
A first plating layer forming step of applying a voltage of a predetermined polarity between a second electrode facing the mask and the first electrode to grow a plating layer corresponding to the mask pattern; A second plating layer forming step of growing a plating layer until a bridge layer for short-circuiting a circuit element corresponding to the mask pattern is formed on the mask surface; and the first and second plating steps. A plating layer eluting step of inverting the polarity of the voltage applied between the electrodes and eluting the grown plating layer into the electrolytic solution, wherein the plating layer elution step is performed on the mask pattern. A method for forming a circuit by plating, wherein a bridge layer portion for short-circuiting the circuit element is eluted. 2. The circuit forming method according to claim 1, wherein a resistance value between said substrate and said first electrode is observed to monitor generation of said bridge layer.