JPH10303875A - Bit synchronizing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten a time required for extraction of sampling clock performed for each burst signal inputted from plural counter devices. SOLUTION: A storage circuit 8 stores identification information concerning the latest optimum sampling clock, which is selected when the bit synchronism of burst data inputted from respective counter devices 3-1 to 3-N is established, and this information is read out and used for establishing the bit synchronism. It is ordinary for burst data from a certain counter device that there is no rapid and considerable phase fluctuation and at the time of burst data input, bit synchronizing operation can be always started from the clock of phase close to the optimum sampling clock so that time required for bit synchronization can be shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bit synchronization circuit, and more particularly to a bit synchronization circuit in burst signal transmission in which a transmission device and a plurality of game devices are coupled one-to-many by a coupler.

[0002]

2. Description of the Related Art Conventionally, this kind of bit synchronizing circuit has been used for the purpose of extracting an optimum sampling clock in a short time in a burst signal receiving circuit of a device for transmitting burst signals. For example, Japanese Patent Application Laid-Open
No. 43919 discloses that when an input signal is supplied, the input signal is compared with a clock from a generator of a multi-phase clock having the same phase difference selected via a multiplexer, and the input signal is sampled. Techniques for extracting the most suitable clock are described. This conventional bit synchronization circuit will be described with reference to FIG.

In FIG. 5, the conventional bit synchronization circuit is
A generator 101 for the multiphase clocks f1 to fn, a multiplexer 102 for selecting a target clock from the multiphase clock generator 101, and a phase comparator for comparing the phase difference between the output signal of the multiplexer 102 and the input signal f0. 1
03 and the output signal of the phase comparator 103 are input,
The multi-phase clock generator 101 includes a multiplexer control means 104 for transmitting a signal for controlling the multiplexer 102 by using this signal.
It is configured to obtain 1 to fn.

In such a configuration, when the input signal f0 is given, a clock most suitable for sampling the input signal f0 by the phase comparator 103 and the multiplexer 102, for example, the clock f1 is extracted from the output terminal Y of the multiplexer 102. To do.

[0005]

When a burst signal is received from each of a plurality of game devices, the input phase of the received burst signal with respect to the reference clock phase in the transmission device can be any phase. Therefore, the optimum sampling clock differs for each burst signal. Therefore, the conventional circuit described above requires time for re-extracting the sampling clock for each burst signal. In other words, in the above-mentioned conventional circuit, the optimum sampling clock for each burst signal to be input is
It is unknown until the burst signal is input, and there is a drawback that the sampling clock must be newly extracted every time the burst signal is input.

The present invention has been made to solve the above-mentioned drawbacks of the prior art, and an object thereof is to shorten the time required for extracting a sampling clock for each burst signal input from a plurality of player devices. To provide a bit synchronizing circuit capable of performing such operations.

[0007]

A bit synchronization circuit according to the present invention selects one of a plurality of types of synchronization clocks having mutually different phases and uses it for receiving data transmitted from a plurality of player devices. A circuit for storing identification information for specifying a clock when bit synchronization is established by a selected synchronization clock; and a plurality of types of the plurality of types according to the identification information stored in the storage means. And selecting means for selecting the synchronous clock.

Also, the storage means stores the identification information in association with each of the game devices. Further, the data is burst data, and the storage means stores the identification information in a non-signal section between the burst data. Then, the selection unit sets the synchronous clock specified by the identification information as an initial selection value.

In short, the bit synchronization circuit has a function of storing and reading the identification information about the latest optimum sampling clock selected when the bit synchronization of the burst data input from each player is established. It is doing. Since burst data from a certain game device usually does not have abrupt and large phase fluctuation, bit synchronization operation can always be started from a clock having a phase close to the optimum sampling clock when each burst data is input. Time can be reduced.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a bit synchronization circuit according to the present invention. In the figure, this bit synchronization circuit is provided in the transmission device 2.
The transmission device 2 is connected to the game devices 3-1 to 3-N via the coupler 1.
(N is an integer of 2 or more). In the figure, the main signal processing circuit 6 is a player device 3-1 to
3-N has a function of controlling bandwidth allocation of burst data and a function of controlling an input phase of each burst data with sufficient accuracy, and a control signal 4 at an appropriate timing.
00 and an initial setting signal 300 are output. It should be noted that a non-signal section is provided between each input burst data.

A burst signal receiving circuit 4 receives a burst signal from the terminal devices 3-1 to 3-N which are coupled one-to-many by the coupler 1, and outputs a burst electric signal data 500 by a digital PLL circuit 5.

The digital PLL circuit 5 inputs the reference clock 600 from the reference clock generation circuit 7 and performs bit synchronization operation, and outputs the data 100 and the clock 200 to the main signal processing circuit 6. At the same time, the PLL circuit 5 performs a write operation and a read operation of information regarding the selected clock with respect to the memory circuit 8, and the main signal processing circuit 6
The information read from the memory circuit 8 is initialized in its own circuit in accordance with the input of the initial setting signal from.

The storage circuit 8 writes information from the digital PLL circuit 5 according to a control signal 400 including an address signal, a write enable signal, and a read enable signal corresponding to an arbitrary game device input from the main signal processing circuit 6. Perform operation and read operation.

Next, the detailed structure of the digital PLL circuit 5 will be described. FIG. 2 is a block diagram showing a configuration example of the digital PLL circuit 5 in the embodiment of the present invention. In the figure, a multi-phase clock generation circuit 55 generates a multi-phase clock (a plurality of types of clocks having different phases) having the same phase interval using the reference clock 600 generated in the reference clock generation circuit 7. The clock selection circuit 54 selects a certain one-phase clock from the multiphase clocks input from the multiphase clock generation circuit 55 under the control of the clock selection circuit control circuit 53.

The phase comparison circuit 52 receives the data 500 input from the burst signal reception circuit 4 and the clock selection circuit 54.
The phase comparison with the clock selected in step 1 is performed, and the comparison result is output to the clock selection circuit control circuit 53.

The clock selection circuit control circuit 53 receives the phase comparison result from the phase comparison circuit 52 and outputs a control signal for controlling the selection of the clock selection circuit 54. Also,
The control circuit 53 writes and reads information of a clock control circuit control signal to and from the memory circuit 8, and
The read value is initialized in its own circuit in accordance with the initialization signal input from the main signal processing circuit 6.

The identification circuit 51 samples the data 500 input from the burst signal receiving circuit 4 with the clock 200 selected by the clock selecting circuit 54 and outputs the sampled data 100 to the main signal processing circuit 6. The clock selection circuit 54 outputs the clock 200 selected under the control of the control circuit 53 to the main signal processing circuit 6.

Next, the operation of the embodiment of the present invention will be described in detail with reference to the time chart of FIG.

In FIG. 3, signals equivalent to those shown in FIGS. 1 and 2 are denoted by the same reference numerals.
FIG. 3 shows data 500 received from the game device and a control signal 4 inputted from the main signal processing circuit 6 to the storage circuit 8.
00 and the main signal processing circuit 6 to the digital PLL circuit 5
The initial setting signal 300 input to and the data stored in the memory circuit 8 are shown.

In the figure, of the contents of the data 500, DATA which is the n-th data from the game device 3-J is shown.
It is assumed that (j, n) and DATA (k, m) that is the m-th data from the game device 3-k are shown. Note that t is a non-signal section.

The control signal 400 input from the main signal processing circuit 6 to the storage circuit 8 includes an address ADD, a write enable signal WE, and a read enable signal RE. Among the contents of the address ADD, ADDR (j) is the game device 3-J.
ADDR (k) is an address corresponding to the game device 3-K. It is assumed that the write enable signal WE and the read enable signal RE indicate “permitted” when both are in the low level state.

The initial setting signal 300 indicates "execution of initial setting" in the low level state.

It should be noted that, among the data stored in the storage circuit 8, the address ADDR (j) and the address AD
The data stored in DR (k) is shown. The content of the data stored in the address ADDR (j) is initially D
CLK (j, n-1), which is the final value of the output of the clock selection circuit control circuit 53 for ATA (j, n-1), and then the output of the clock selection circuit control circuit 53 for DATA (j, n). CLK (j, n) which is the final value
Shall be updated to. The address ADDR
The contents of the data stored in (k) are initially DATA
Clock selection circuit control circuit 53 for (k, m-1)
Is the final value of the output of CLK (k, m-1).

Referring to FIG. 2, a digital PLL circuit 5 which is inputting DATA (j, n), which is the n-th input data from the game apparatus 3-J, has a phase comparator 52 which outputs DATA (j, n). ) And the clock selection circuit 54 compares the phases of the clocks already selected. Then, according to the comparison result, the clock selection circuit control circuit 53 outputs a value corresponding to each phase of the multiphase clock to the clock selection circuit 54 and the storage circuit 8. The clock selection circuit 54 repeats the operation of selecting a new phase from the multi-phase clock. Thereby, the optimal sampling clock CLK (j, n)
Is extracted.

In the signalless period t after the input of DATA (j, n), the main signal processing circuit 6 puts the write processing signal WE output to the memory circuit 8 into the enable state. Thus, the storage circuit 8 stores the value CLK held by the clock selection circuit control circuit 53 at the address ADDR (j) corresponding to the game device 3-J input from the main signal processing circuit 6.
Write (j, n).

When the next input data is the m-th data DATA (k, m) from the game device 3-K, the main signal processing circuit 6 sets the address A corresponding to the game device 3-K.
DDR (k) is output to the storage circuit 8, and the read permission signal RE output to the storage circuit 8 is set to a permission state. As a result, the data stored at the address ADDR (k) of the storage circuit 8, which is (m-1) from the game device 3-K.
The final value CLK (k, m−1) of the output of the clock selection circuit control circuit 53 for the data
1) is output to the clock selection circuit control circuit 53.

Thereafter, when the main signal processing circuit 6 puts the initialization signal 300 output to the clock selection circuit control circuit 53 into the initialization execution state, the clock selection circuit control circuit 53.
Initializes the value CLK (k, m-1) in its own circuit. Further, the clock selection circuit 54 outputs the corresponding clock CLK.
(K, m-1) is selected and output to the phase comparison circuit 52, the discrimination circuit 51 and the main signal processing circuit 6.

Similarly, when the m-th data DATA (k, m) from the game device 3K is input, the digital PL
The L circuit 5 newly starts operation. In this case, the data D
Optimal sampling clock C for ATA (k, m)
LK (k, m) is extracted, and the value CL is stored in the address ADDR (k) of the storage circuit 8 under the control of the main signal control circuit 6.
Write K (k, m). After that, the same operation is repeated.

In short, in the present bit synchronization circuit, the main signal processing circuit 6 transmits the address signal and the write enable signal corresponding to the remote device to the storage circuit 8 at a predetermined timing before inputting the burst data from the remote device. A control signal including a read permission signal is output. Then, it outputs an initialization signal 300 to the clock selection circuit control circuit 53 of the digital PLL circuit 5. As a result, the information of the clock selection circuit control circuit 53 is written to the memory circuit 8 according to the control signal 400 and the initial setting signal 300, and the information written to the memory circuit 8 is read to the clock selection circuit control circuit 53. For this reason, the storage circuit 8 always stores the latest identification information about the optimum sampling clock in association with each playing device, and when burst data is input, this information can be read to perform the bit synchronization operation. is there.

[0031]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 4 is a block diagram showing a configuration example of the digital PLL circuit 5 in the embodiment of the present invention. The multi-phase clock generation circuit 55 uses the reference clock generated in the frequency z × f0 clock transmission circuit 7 to generate multi-phase clocks f0 × y having equal phase intervals. The multiplexer 54 selects a certain one-phase clock from the multi-phase clocks input from the multi-phase clock generation circuit 55 according to the control from the x-bit up / down counter 53. The flip-flop (F / F) 52 performs retiming of the clock selected by the multiplexer 54 with the data of the frequency f0 input from the burst signal receiving circuit 4, and outputs the retiming result to the x-bit up / down counter 53. The x-bit up / down counter 53 counts up or down according to the retiming result input from the F / F 52. This count value is output as a control signal for performing clock selection control in the multiplexer 54. Further, information of the control signal is written in and read from the semiconductor memory 8. Further, the read value is loaded into its own circuit according to the initial setting signal 300 input from the main signal processing circuit 6. The F / F 51 samples the data input from the burst signal receiving circuit 4 with the clock selected by the multiplexer 54, and outputs the sampled data to the main signal processing circuit 6.

The operation of the bit synchronization circuit using the digital PLL circuit 5 according to the present embodiment having such a configuration will be described.
It will be described with reference to FIG. 3 again.

Referring to the figure, in the digital PLL circuit 5 to which DATA (j, n) as the n-th input data from the game apparatus 3-J is input, the F / F 52 outputs DATA (j, n) by multiplexer 5
In step 4, retiming of the clock already selected is performed. According to this retiming result, the x-bit up / down counter 53 outputs the count value after counting up or down to the multiplexer 54 and the memory 8. The multiplexer 54 repeats the operation of selecting a new phase from the multi-phase clock. Thus, the optimal sampling clock CLK (j, n) is extracted. Heartless signal section t after input of DATA (j, n) is completed
In, the main signal processing circuit 6 sets the write enable signal WE output to the memory 8 to the enable state. As a result, the count value CL held by the x-bit up / down counter 53 is stored in the memory 8 at the address ADDR (j) corresponding to the game device 3-J input from the main signal processing circuit 6.
K (j, n) is written.

When the next input data is the m-th data DATA (k, m) from the playing device 3-K, the main signal processing circuit 6 causes the address A corresponding to the playing device 3-K.
DDR (k) is output to the memory 8 and the read enable signal RE output to the memory 8 is set to the enable state. Thus, the x-bit up / down counter 53 for the (m-1) -th data DATA (k, m-1) from the game device 3-K, which is the data held at the address ADDR (k) of the memory 8 Final count value CLK (k, m
-1) is output to the x-bit up / down counter 53.

Thereafter, the main signal processing circuit 6 outputs the initial value setting signal 30 output to the x-bit up / down counter 53.
When 0 is set to the initial setting execution state, the x-bit up / down counter 53 loads the value CLK (k, m-1) into its own circuit. As a result, the multiplexer 54 selects the corresponding clock CLK (k, m-1) to select the F / F52, F / F52.
Output to F51 and main signal processing circuit 6.

Similarly, when the m-th data DATA (k, m) is input from the game device 3-K, the digital P
The LL circuit 5 newly starts operation. In this case, DAT
Optimal sampling clock CLK for A (k, m)
(K, m) is extracted and the value CL is stored in the address ADDR (k) of the memory 8 under the control of the main signal control circuit 6.
Write K (k, m). Thereafter, the same operation is repeated.

As described above, this circuit has a function of storing and reading the latest optimum sampling clock information selected when the bit synchronization of the burst data input from each player is established. Have. Normally, there is no sharp and large phase fluctuation between burst data from a certain game device, so that when synchronizing each burst data, the bit synchronization operation can always be started from a clock having a phase close to the optimal sampling clock, which is necessary for bit synchronization. The time can be shortened.
In other words, the bit synchronization pattern can be shortened.

The present invention can further have the following aspects in connection with the description of the claims.

(6) The bit synchronization circuit according to claim 5, wherein the counter is initialized by the count value.

(7) The bit synchronization circuit according to any one of claims 1 to 6, wherein the storage means is a semiconductor memory.

[0042]

As described above, according to the present invention, the identification information on the latest optimum sampling clock selected when the bit synchronization of the burst data input from each game device is established is stored, and By reading and using it for establishing bit synchronization, there is an effect that the bit synchronization operation can always be started from a clock having a phase close to the optimum sampling clock when burst data is input, and the time required for bit synchronization can be shortened.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a bit synchronization circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram showing an internal configuration example of a digital PLL circuit in FIG.

FIG. 3 is a time chart illustrating an operation of the bit synchronization circuit of FIG. 1;

FIG. 4 is a block diagram showing a more detailed configuration of the digital PLL circuit in FIG. 1;

FIG. 5 is a block diagram showing a configuration of a conventional bit synchronization circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Coupler 2 Transmission device 3-1 to 3-N Target device 4 Burst signal receiving circuit 5 Digital PLL circuit 6 Main signal processing circuit 7 Reference clock generation circuit 8 Storage circuit 51 Identification circuit 52 Phase comparison circuit 53 Clock selection circuit control circuit 54 Clock selection circuit 55 Multi-phase clock generation circuit 101 Multi-phase clock generator 102 Multiplexer 103 Phase comparator 104 Multiplexer controller

Claims (5)

[Claims] 1. A bit synchronization circuit for selecting one of a plurality of types of synchronous clocks having different phases from each other and using the selected synchronous clocks for receiving data transmitted from a plurality of game apparatuses, respectively.
Storage means for storing identification information for specifying the clock when bit synchronization is established by the selected synchronization clock, and selecting the plurality of types of synchronization clocks according to the identification information stored in the storage means A bit synchronization circuit comprising: 2. The bit synchronization circuit according to claim 1, wherein the storage unit stores the identification information in association with each of the game devices. 3. The bit synchronization circuit according to claim 1, wherein said data is burst data, and said storage means stores said identification information in a no-signal section between said burst data. 4. The bit synchronization circuit according to claim 1, wherein the selection unit sets the synchronization clock specified by the identification information as an initial selection value. 5. The apparatus according to claim 1, wherein said selection means includes a multiplexer for inputting a multi-phase clock and outputting one of the clocks, and a counter for selectively controlling said multiplexer, wherein said identification information is a count value of said counter. 5. The bit synchronization circuit according to claim 1.