JPH10303465A - Face mounting semiconductor element - Google Patents

Face mounting semiconductor element

Info

Publication number
JPH10303465A
JPH10303465A JP9120140A JP12014097A JPH10303465A JP H10303465 A JPH10303465 A JP H10303465A JP 9120140 A JP9120140 A JP 9120140A JP 12014097 A JP12014097 A JP 12014097A JP H10303465 A JPH10303465 A JP H10303465A
Authority
JP
Japan
Prior art keywords
substrate
chip
mold
semiconductor
led
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9120140A
Other languages
Japanese (ja)
Other versions
JP3245378B2 (en
Inventor
Takeo Itou
多計夫 伊藤
Maki Kuriyama
真樹 栗山
Satoshi Hirama
聡 平間
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Stanley Electric Co Ltd
Original Assignee
Stanley Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Stanley Electric Co Ltd filed Critical Stanley Electric Co Ltd
Priority to JP12014097A priority Critical patent/JP3245378B2/en
Publication of JPH10303465A publication Critical patent/JPH10303465A/en
Application granted granted Critical
Publication of JP3245378B2 publication Critical patent/JP3245378B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Abstract

PROBLEM TO BE SOLVED: To provide a chip element which enables itself to be mounted at a face on, for example, a printed wiring board or the like without providing a mounting hole called chip mount, or surface mounting, or the like. SOLUTION: As a face mounting semiconductor element where a mold 24 covering a mounting board 41 mounted with an LED chip is thicker than the substrate 41 and covers the whole face of one side at least of the substrate 41, and the substrate 41 and a terminal are not protuberant to the periphery from the mold 24 when the mold is viewed from the direction of the normal of the substrate on the side where the chip is provided, a face mounting LED element 40 is obtained, which is downsized to an indispensable minimum size by enlarging the rate of the area Ac of the face of being placed on the chip substrate of the semiconductor chip 21 placed on the substrate 41 to the projected area As in the direction of the normal to the substrate of the said face mounting type of semiconductor element.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】 本発明は、チップマウン
ト、表面実装等と称されて、例えばプリント配線板など
の上に取付穴を設けることなく面で実装すること等を可
能としたチップ部品素子に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip component element called chip mount, surface mounting, etc., which can be mounted on a surface without providing mounting holes on a printed wiring board or the like. Things.

【0002】[0002]

【従来の技術】 従来の面実装型素子として特開平8−
330637号や特開平8−321634号等があり、
図15に示したようなチップ基板94に電極端子95が
形成され、該電極端子と電気的に接続したLEDチップ
91とモールド部93を一方の基板表面に有する面実装
型LED素子90が公知である。このLED素子90は
例えば、図9〜図14に示した工程説明図の順に沿って
製造される。
2. Description of the Related Art As a conventional surface mount device,
No. 330637 and JP-A-8-321634.
An electrode terminal 95 is formed on a chip substrate 94 as shown in FIG. 15, and a surface mount type LED element 90 having an LED chip 91 electrically connected to the electrode terminal and a molded portion 93 on one substrate surface is known. is there. The LED element 90 is manufactured, for example, in the order of the process explanatory diagrams shown in FIGS.

【0003】初めにガラスエポキシなどの絶縁性基板の
両面に銅箔81が貼着等されて形成された公知のプリン
ト回路基板などの母体基板80に適宜な間隔をあけて略
方形の貫通孔82を設けて図9に示すような断面形状と
する。
At first, a substantially rectangular through-hole 82 is formed at an appropriate interval on a base substrate 80 such as a known printed circuit board formed by attaching copper foil 81 to both surfaces of an insulating substrate such as glass epoxy. To form a cross section as shown in FIG.

【0004】次に母体基板80の両面に設けられている
銅箔81を電気的に接続するために、図10に示すよう
に貫通孔82の内面に銅などの無電界メッキ、電界メッ
キ、Niメッキ、金メッキを繰り返して行なうなどの手
段により表面が金で覆われた導電膜83を形成して貫通
孔82にて両面を電気的に接続する。次に母体基板80
の貫通孔間の銅箔81を所望の配線パターンとなるよう
にレジストを塗布しエッチング等の公知の手段により銅
箔の一部を除去することで、図11に示したような複数
のLEDチップを並列して搭載できる配線パターンを形
成して、母体基板80の一方の表面側にパッド部84と
配線部85を作成する。また、反対側の基板裏面の銅箔
81にも同様の手段により略長方形状の絶縁部86を形
成することで母体基板80が完成する。
Next, in order to electrically connect the copper foils 81 provided on both surfaces of the base substrate 80, electroless plating of copper or the like, electrolytic plating, A conductive film 83 whose surface is covered with gold is formed by a method such as repeated plating and gold plating, and both surfaces are electrically connected through a through hole 82. Next, the mother substrate 80
A resist is applied to the copper foil 81 between the through-holes so as to form a desired wiring pattern, and a part of the copper foil is removed by a known means such as etching to form a plurality of LED chips as shown in FIG. Are formed in parallel to form a pad portion 84 and a wiring portion 85 on one surface side of the mother substrate 80. A substantially rectangular insulating portion 86 is also formed on the copper foil 81 on the back surface of the opposite substrate by the same means, whereby the mother substrate 80 is completed.

【0005】そして、図12に示すように前記パッド部
84にLEDチップ91のP型若しくはN型チップ電極
を導電性接着剤などによりマウントし、LEDチップ9
1の他方の電極と配線部85とを金線などのワイヤー9
2をボンディングすることにより接続する。次にこのよ
うにして接続したLEDチップ91及びワイヤー92を
前記貫通孔82と平行な略台形柱形状の透明絶縁性樹脂
で覆ってモールド部93を形成する。次にこのモールド
部93を形成した母体基板80を図14に示す切断線D
に沿ってカッター等により切断することで、モールド部
が形成された母体基板はLEDチップ91を有する複数
の面実装型LED素子90に分割されるものとなる。
Then, as shown in FIG. 12, a P-type or N-type chip electrode of the LED chip 91 is mounted on the pad portion 84 with a conductive adhesive or the like, and the LED chip 9 is mounted.
The other electrode 1 and the wiring portion 85 are connected to a wire 9 such as a gold wire.
2 by bonding. Next, the LED chip 91 and the wire 92 connected in this manner are covered with a substantially trapezoidal column-shaped transparent insulating resin parallel to the through-hole 82 to form a molded portion 93. Next, the mother substrate 80 on which the molded portion 93 is formed is cut along a cutting line D shown in FIG.
By using a cutter or the like along the line, the mother substrate on which the mold portion is formed is divided into a plurality of surface-mounted LED elements 90 having LED chips 91.

【0006】このようにして製造した面実装型LED素
子90は略台形状のモールド部93と、モールド部より
側方に突出しLEDチップのチップ電極と接続された電
極端子95をチップ基板94の対峙する二辺に有する形
状となる。
The surface mount type LED element 90 manufactured in this manner has a substantially trapezoidal molded portion 93 and an electrode terminal 95 projecting laterally from the molded portion and connected to the chip electrode of the LED chip, facing the chip substrate 94. The shape has two sides.

【0007】これはモールド部を樹脂により覆う際に型
にセットして成形するため、LEDチップ91を搭載し
た母体基板80を図13に示すように上型96と下型9
7の間に挟むものとしてモールド部93を成形してい
る。この成形の際に、仮にモールド部が母体基板80の
貫通孔82の部分にまで到達するような型状の上型を用
いて成形した場合には、モールド部の樹脂が貫通孔82
を介して母体基板の裏面にまで回り込んで裏面の銅箔8
1の表面に付着するものとなり、面実装型LED素子9
0をプリント回路配線板等に取り付ける際に電気的な接
続がとれないという不都合が生じるものとなり、製造歩
留りが著しく低下する。特に面実装型LED素子90を
小型のものとした場合には母体基板80の裏面に露出し
ている銅箔の面積も小さいものであるので、母体基板裏
面側に樹脂が回り込まないようにすることは重要であ
る。そこで図13に示したように上型96と母体基板の
電極端子95が一定の大きさを有する型おさえ部98に
て面接触するものとしてモールド部93の樹脂が貫通孔
82を介して母体基板裏面に回り込むことを確実に防止
しているのである。
[0007] In this method, when the mold portion is covered with a resin, it is set in a mold and molded. Therefore, the mother substrate 80 on which the LED chip 91 is mounted is mounted on the upper mold 96 and the lower mold 9 as shown in FIG.
7, a molding part 93 is formed therebetween. In this molding, if the molding is performed using an upper mold having a mold portion that reaches the portion of the through hole 82 of the base substrate 80, the resin of the molding portion is
To the back surface of the mother board through the
1 is attached to the surface of the surface mount type LED element 9.
However, when 0 is attached to a printed circuit board or the like, there is a disadvantage that electrical connection cannot be made, and the production yield is significantly reduced. In particular, when the surface-mount type LED element 90 is made small, the area of the copper foil exposed on the back surface of the base substrate 80 is also small, so that the resin should not flow around the back surface of the base substrate. Is important. Therefore, as shown in FIG. 13, it is assumed that the upper mold 96 and the electrode terminal 95 of the mother board are in surface contact with each other at the mold holding section 98 having a certain size. It is surely prevented from going around the back.

【0008】[0008]

【発明が解決しようとする課題】モールド部により半導
体素子を覆った従来の面実装型素子は上記した理由によ
りモールド部の側方に型おさえ部が必要であるため、電
極端子95の部分がモールド部より突出したものとなる
ことが避けられなかった。現実に現在市販しているこの
種の面実装型LED素子の最小レベルのものの外形寸法
は、例えばスタンレー電気株式会社製のBR1111C
であるならば長さLs=1.6mm、幅Ws=0.8m
m、高さHs=0.7mm、他社のもので長さLs=
1.6mm、幅Ws=0.8mm、高さHs=0.8m
m(CL−190)であり、両者ともモールド部の両側
の電極端子の部分に夫々に0.2mmの型おさえ部を有
している。これらのLEDのように超小型といわれてい
るものであっても、電極端子95がモールド部93より
外方に突出しており、その突出寸法は素子長さLs方向
に夫々0.2mm、計0.4mmもの領域が突出してい
る。本出願人は外部に突出している電極端子95の寸法
をできる限り小さくしてモールド部を形成するように検
討したが、電極端子の型おさえ部98の寸法をモールド
部両側にて夫々0.1mmとすると製造時の位置合わせ
の精度や誤差等の関係から基板裏面に回り込むことが多
くなり、現実的には0.2mm程度の寸法が必要であ
り、従来のLED素子ではこれ以上に外部突出電極端子
の寸法を小さくすることは現実的には不可能であった。
In the conventional surface mount type device in which the semiconductor element is covered by the mold portion, a mold holding portion is required on the side of the mold portion for the above-described reason. It was inevitable that it would protrude from the part. The external dimensions of the minimum level of this type of surface mount type LED element currently commercially available are, for example, BR1111C manufactured by Stanley Electric Co., Ltd.
, The length Ls = 1.6 mm and the width Ws = 0.8 m
m, height Hs = 0.7 mm, length Ls =
1.6 mm, width Ws = 0.8 mm, height Hs = 0.8 m
m (CL-190), both of which have a 0.2 mm die holding portion at each of the electrode terminals on both sides of the molded portion. Even if these LEDs are said to be ultra-small, the electrode terminals 95 protrude outward from the mold part 93, and the protruding dimensions are 0.2 mm each in the element length Ls direction, ie, 0 mm in total. A region as large as 0.4 mm protrudes. The present applicant has studied to form the molded portion by minimizing the dimensions of the electrode terminals 95 protruding to the outside. However, the dimensions of the mold holding portions 98 of the electrode terminals were set to 0.1 mm on both sides of the molded portion. In this case, it often goes around the back surface of the substrate due to the positioning accuracy and error during manufacturing, and in reality, a dimension of about 0.2 mm is required. It has not been practically possible to reduce the dimensions of the terminals.

【0009】また、LEDチップ91と配線部85をワ
イヤ−92にて接続しているので、LEDチップ91の
上面に更にワイヤーの引き回しの高さ分を加えてこれら
を十分に保護する必要があり、モールド部の高さ方向に
ついても小型化を図ることが困難であった。また、ワイ
ヤーの他方側にて接続される配線部85もある程度の面
積が必要なため、ワイヤーボンディング方向のモールド
部の寸法についてもこれ以上の小型化を図ることは困難
であった。
Further, since the LED chip 91 and the wiring portion 85 are connected by the wire 92, it is necessary to further protect the upper surface of the LED chip 91 by adding a wiring height to the wire. Also, it has been difficult to reduce the size in the height direction of the mold section. Further, since the wiring portion 85 connected on the other side of the wire also needs a certain area, it is difficult to further reduce the size of the mold portion in the wire bonding direction.

【0010】更に、樹脂モールドする際の上型と母体基
板との位置合わせにズレが生じ易く、正確に位置合わせ
を行なったつもりであっても、基板裏面にモールド樹脂
が回り込んだり、完成した面実装型LEDの発光部の位
置ズレが生じる場合があり、歩留りを低下させる一因で
あった。
Further, misalignment is likely to occur between the upper mold and the mother substrate during resin molding, and even if the positioning is intended to be performed accurately, the molding resin may flow around the back surface of the substrate or may be completed. In some cases, the position of the light emitting portion of the surface-mounted LED may be displaced, which is one of the factors that lower the yield.

【0011】このような課題を解決する手段として本願
出願人による特開平9−45964号が発明されてい
る。かかる先願発明によれば、図16に示したように2
枚の電極板71、71間に所定間隔のピッチPを保って
配列しているLEDチップ91のチップ電極が電極板7
1と接合剤72により接合するようにして挟持し、この
隙間に透明樹脂73を注入硬化させ、然る後に隣接する
LEDチップ間にて切断、分離することで図17に示し
たような小型の面実装型LED素子70を得ることがで
きる。このLED素子70はワイヤーボンドも不要なの
でワイヤの引き回しの高さを取る必要もなく、また、モ
ールド部を形成する際の型おさえ部も不要なので前記し
た従来の面実装型LED素子90に比べて小型化するこ
とができる。
As means for solving such a problem, Japanese Patent Application Laid-Open No. 9-45964 has been invented by the present applicant. According to the prior invention, as shown in FIG.
The chip electrodes of the LED chips 91 arranged at a predetermined pitch P between the electrode plates 71, 71 are connected to the electrode plates 7.
1 and a bonding agent 72, and a transparent resin 73 is injected and hardened in this gap, and then cut and separated between adjacent LED chips to obtain a small-sized device as shown in FIG. The surface-mounted LED element 70 can be obtained. Since the LED element 70 does not require a wire bond, there is no need to take the height of the lead of the wire, and a die holding part when forming the mold part is also unnecessary. The size can be reduced.

【0012】しかしながら、この製造方法により製造し
たLED素子70は複数のLEDチップ91の両側面を
不透明な電極板にて挟持して製造するものであるため、
各LEDチップ91が均一に且つ確実に電極板71と接
合するものではないので、電極板の接合強度が弱く剥離
不良を起こし易いという問題があった。また、面実装型
LED素子70から放出される光は直方体の6面のうち
2面において遮光されるものとなっており、また、面実
装型LED素子70の透明樹脂73の表面は切断した面
であるため、その形状を曲線的にすることができずモー
ルド樹脂にレンズ作用を持たせることが困難であるとい
う問題もあった。
However, since the LED element 70 manufactured by this manufacturing method is manufactured by sandwiching both side surfaces of the plurality of LED chips 91 between opaque electrode plates,
Since each LED chip 91 is not uniformly and reliably bonded to the electrode plate 71, there is a problem that the bonding strength of the electrode plate is weak and peeling failure easily occurs. The light emitted from the surface-mounted LED element 70 is blocked on two of the six rectangular parallelepiped surfaces, and the surface of the transparent resin 73 of the surface-mounted LED element 70 is a cut surface. Therefore, there is also a problem that the shape cannot be made curved and it is difficult to give the mold resin a lens function.

【0012】そこで、本発明は第1にモールド部よりも
外側に突出した部分のない面実装型半導体素子を得るこ
とを第1の目的とする。第2には半導体チップに対して
所定割合以下の大きさに小型化した面実装型半導体素子
を得ることを目的とする。第3には上記面実装型半導体
素子を効率良く製造できる面実装型半導体素子用チップ
基板を提供することを目的とする。第4には前記チップ
基板を用いてモールド部よりも外側に突出した部分の少
ない面実装型半導体素子を得るための製造方法を提供す
る事を目的とする。
Accordingly, a first object of the present invention is to obtain a surface-mount type semiconductor device having no portion protruding outside the molded portion. A second object is to obtain a surface-mount type semiconductor element which is reduced in size to a predetermined ratio or less with respect to a semiconductor chip. A third object of the present invention is to provide a chip substrate for a surface-mount type semiconductor element which can efficiently manufacture the above-mentioned surface-mount type semiconductor element. Fourth, it is an object of the present invention to provide a manufacturing method for obtaining a surface mount type semiconductor element having a small portion protruding outside of a mold portion using the chip substrate.

【0013】[0013]

【発明の実施の形態】つぎに、本発明の実施形態に基づ
いて説明する。図6は本発明により得られる面実装型半
導体素子の一例であり、略直方体形状とした面実装型L
ED素子40の例である。実装基板41の対峙する二辺
42、43の側には電極端子44が夫々設けられてお
り、該基板41の一方の面上にはLEDチップ素子21
のチップ電極が導電性ペースト22により夫々の電極端
子44と接続され、このLEDチップを覆うモールド部
24が該実装基板41の表面全面を覆って設けられてい
る。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a description will be given based on an embodiment of the present invention. FIG. 6 shows an example of a surface-mount type semiconductor device obtained by the present invention.
This is an example of the ED element 40. An electrode terminal 44 is provided on each of two opposing sides 42 and 43 of the mounting board 41, and the LED chip element 21 is provided on one surface of the board 41.
The chip electrodes are connected to the respective electrode terminals 44 by the conductive paste 22, and the mold portion 24 covering the LED chips is provided to cover the entire surface of the mounting substrate 41.

【0014】この面実装型半導体素子40について、こ
の面実装型LED素子40の製造方法の工程順に図1〜
図5を参照して説明する。まず後で実装基板41となる
チップ基板20の製造工程から順に説明する。図1
(a)〜(h)に示したものは、図2に一部を破断して
示したチップ基板20の製造工程を断面図により示した
ものである。
FIGS. 1 to 3 show the steps of the method of manufacturing the surface-mount type LED element 40 in the surface-mount type semiconductor element 40.
This will be described with reference to FIG. First, the manufacturing process of the chip substrate 20 that will become the mounting substrate 41 will be described in order. FIG.
(A) to (h) are cross-sectional views showing a manufacturing process of the chip substrate 20, which is partially cut away in FIG.

【0015】なお、本発明の特徴を解り易くするため
に、前記した図面はいずれも図面横方向の寸法に対して
図面縦方向の寸法を誇張して示している。また、説明の
便宜上、図面上側の表面を上面、下側の表面を下面とし
て説明する。
[0015] To facilitate understanding of the features of the present invention, the above-mentioned drawings exaggerate the dimensions in the vertical direction with respect to the dimensions in the horizontal direction. Also, for convenience of explanation, the upper surface in the drawing is referred to as an upper surface, and the lower surface is referred to as a lower surface.

【0016】まず初めに絶縁性の材料、例えばポリイミ
ド系、ポリエステル系、エポキシ系等の絶縁樹脂材料フ
ィルムからなる基体1の下面全面に銅箔2を貼着し、上
面全面に剥離紙を設けた接着シート等の接着層3を設け
る(図1(a))。この基体をプレス等の手段により図
1(b’)に示すような形状に抜き落としてライン状の
貫通孔10を並列に形成し、残った基体上、即ち隣接す
る貫通孔10間の位置に後の工程でチップ素子が載置さ
れる。なお、(b)図は(b’)図のI−I断面図であ
る。貫通孔10を形成した基体の上面の接着層3、接着
シートならば剥離紙を剥がして接着層とする、を介して
銅箔等からなる導電板4を基体1に貼着し、引続いて銅
等の導電性物質を無電界メッキ等の手段により(c)図
に示したようにメッキ層5を形成する。これにより上
面、下面、絶縁性基体1の側面である貫通孔10の内面
の全てがメッキ層5により覆われるものとなり、基体上
面と下面が電気的に接続され、同時に基体1に形成した
貫通孔10が空間的に覆われるものとなる。よって、従
来のような絶縁性基体1の上面と下面が開口した状態の
貫通孔10を介して電気的に接続されるものとは異なっ
たチップ基板20が得られる。
First, a copper foil 2 was attached to the entire lower surface of a substrate 1 made of an insulating resin material film of an insulating material, for example, polyimide, polyester, epoxy or the like, and a release paper was provided on the entire upper surface. An adhesive layer 3 such as an adhesive sheet is provided (FIG. 1A). This base is pulled out into a shape as shown in FIG. 1 (b ') by means of a press or the like to form line-shaped through holes 10 in parallel, and on the remaining base, that is, at a position between adjacent through holes 10 A chip element is mounted in a later step. FIG. 2B is a cross-sectional view taken along the line II of FIG. A conductive plate 4 made of copper foil or the like is adhered to the base 1 through the adhesive layer 3 on the upper surface of the base having the through-holes 10 formed thereon or, in the case of an adhesive sheet, peeling off the release paper to form an adhesive layer. A plating layer 5 is formed on a conductive substance such as copper by means such as electroless plating as shown in FIG. As a result, all of the upper surface, the lower surface, and the inner surface of the through hole 10 which is the side surface of the insulating substrate 1 are covered with the plating layer 5, and the upper surface and the lower surface of the substrate are electrically connected. 10 will be spatially covered. Therefore, a chip substrate 20 different from the conventional one electrically connected through the through hole 10 in which the upper surface and the lower surface of the insulating substrate 1 are open can be obtained.

【0017】次に、後にカソード電極となる電極端子と
アノード電極となる電極端子とを電気的に分離等するた
めに電極端子となる導電性部分を所定の形状に形成する
エッチング工程を行なう。具体的には(d)図に示した
ように基体1上に位置するパターン溝11を形成するた
めにパターン溝11以外の上面にレジスト6を塗布し、
基体下面の貫通孔10と略平行に位置する離間部12以
外の部分にレジスト6を塗布する。その後に適宜手段に
よりエッチングすることにより絶縁部となるパターン溝
11及び離間部12を形成して(e)図に示したような
チップ基板とする。この説明では(a)〜(e)の工程
により(e)図に示したようなチップ基板を得るものと
したが、基体の上面に離間部12を下面にパターン溝1
1を形成し、下面においてチップ素子を搭載する構成と
しても構わないものであるし、また、貫通孔10を設け
た基体1に印刷や張り合わせの手法により導電板等の導
電部及びパターン溝等の絶縁部を形成するものとするこ
ともできる。
Next, an etching step of forming a conductive portion serving as an electrode terminal into a predetermined shape is performed in order to electrically separate an electrode terminal serving as a cathode electrode and an electrode terminal serving as an anode electrode later. Specifically, a resist 6 is applied to the upper surface other than the pattern grooves 11 to form the pattern grooves 11 located on the substrate 1 as shown in FIG.
A resist 6 is applied to a portion of the lower surface of the base other than the separation portion 12 located substantially parallel to the through hole 10. Thereafter, the pattern groove 11 and the separation portion 12 serving as insulating portions are formed by etching by an appropriate means to obtain a chip substrate as shown in FIG. In this description, it is assumed that the chip substrate as shown in FIG. 1E is obtained by the steps (a) to (e), but the separation portion 12 is provided on the upper surface of the base and the pattern groove 1 is provided on the lower surface.
1, a chip element may be mounted on the lower surface, or a conductive portion such as a conductive plate and a pattern groove may be formed on the substrate 1 provided with the through hole 10 by printing or laminating. An insulating portion may be formed.

【0018】次に図2及び(f)図に断面を示したよう
に、後の工程でチップ素子が搭載される部分及び後の工
程で半田層8が形成される部分以外の上面のメッキ層5
を覆うように絶縁層7、7’を所定の形状に形成し、こ
のチップ基板の上面及び下面を電界メッキ等の手段によ
り露出している導電性部分に半田層8、8’を形成して
(g)図に示すようなチップ基板20を作製する。
Next, as shown in the cross sections of FIGS. 2 and 2F, the plating layer on the upper surface other than the portion where the chip element is mounted in the later step and the portion where the solder layer 8 is formed in the later step 5
The insulating layers 7, 7 'are formed in a predetermined shape so as to cover the surface of the chip substrate, and the solder layers 8, 8' are formed on conductive portions where the upper and lower surfaces of the chip substrate are exposed by means such as electroplating. (G) A chip substrate 20 as shown in FIG.

【0019】この工程によりチップ基板は機能的には完
成するものであるが、(h)に示したようにチップ素子
20のカソード電極を判別するためのマーク9を絶縁性
の着色樹脂等により形成し、同時に下面の離間部12の
一部にも絶縁性のマーク9を形成することで図2に示し
たようなチップ基板20が完成する。なお、絶縁層7、
7’や基体1は完成した実装基板41の表面に露出する
部分もあるので、チップ基板に搭載するチップ素子21
がLED等の発光素子である場合には反射率の高い絶縁
材料によりこれらを形成する方が良く、白色系の絶縁材
料とすることが特に好ましい。
Although the chip substrate is functionally completed by this step, a mark 9 for identifying the cathode electrode of the chip element 20 is formed of an insulating colored resin or the like as shown in FIG. At the same time, the insulating mark 9 is also formed on a part of the separation portion 12 on the lower surface, thereby completing the chip substrate 20 as shown in FIG. The insulating layer 7,
Since there is a portion of the base 7 ′ and the base 1 exposed on the surface of the completed mounting substrate 41, the chip element 21 mounted on the chip substrate
Is a light emitting element such as an LED, it is better to form them with an insulating material having a high reflectivity, and it is particularly preferable to use a white insulating material.

【0020】次に、完成したチップ基板20の上にLE
D等の半導体チップであるチップ素子21をチップ基板
上面の絶縁層7の上に載置する。このときチップ素子の
PN接合面21aを挟んでチップ両端に対向して設けら
れているLEDチップ電極21bの夫々が貫通孔10
側、即ち半田層8側に位置しPN接合面21aがチップ
基板の法線方向となるように載置し、電極21bと半田
層8の夫々を銀ペースト等の導電性ペースト22により
接合して図3に示したようなチップ基板20を完成させ
る。
Next, LE on the completed chip substrate 20
A chip element 21 which is a semiconductor chip such as D is mounted on the insulating layer 7 on the upper surface of the chip substrate. At this time, each of the LED chip electrodes 21b provided opposite to both ends of the chip with the PN junction surface 21a of the chip element interposed therebetween is connected to the through hole 10
Side, that is, on the solder layer 8 side, the PN junction surface 21a is placed so as to be in the normal direction of the chip substrate, and each of the electrode 21b and the solder layer 8 is joined by a conductive paste 22 such as a silver paste. The chip substrate 20 as shown in FIG. 3 is completed.

【0021】次に、チップ素子21を透光性の絶縁樹脂
材料により覆う工程を実施する。この工程は例えば図4
に示したようなトランスファーモールド成形を用いるこ
とができる。所定の形状の型30の間に前記チップ基板
20をセットしてチップ基板上面にモールド樹脂23を
注入する。このときチップ基板20には貫通孔10が形
成されているものの導電板4等により覆われているの
で、従来のチップ基板と異なり貫通孔10により上面と
下面が空間的に繋がっていない。従って、注入した樹脂
23が貫通孔10を介してチップ基板20下面に回り込
むという問題が一切発生しないものとなる。
Next, a step of covering the chip element 21 with a translucent insulating resin material is performed. This step is performed, for example, in FIG.
Can be used. The chip substrate 20 is set between the molds 30 having a predetermined shape, and the mold resin 23 is injected into the upper surface of the chip substrate. At this time, although the through hole 10 is formed in the chip substrate 20 but is covered with the conductive plate 4 or the like, the upper surface and the lower surface are not spatially connected by the through hole 10 unlike the conventional chip substrate. Therefore, the problem that the injected resin 23 goes around the lower surface of the chip substrate 20 through the through hole 10 does not occur at all.

【0022】前記型30から取り出したチップ基板20
は図5に示すようにチップ基板の片側の面のみがモール
ド樹脂23により覆われるものとなり、基板の反対側の
面にモールド樹脂が回り込むことはない。これをダイサ
ーカット等の公知の方法でチップ素子21の間隙をカッ
トライン33に沿って切断する。貫通孔10の部分にて
切断すると貫通孔を覆っていた導電板4、メッキ層5等
を介して上面と下面が電気的に接続された電極端子44
となり、図6に示したような面実装型LED40が完成
する。
The chip substrate 20 taken out of the mold 30
As shown in FIG. 5, only one surface of the chip substrate is covered with the mold resin 23, and the mold resin does not wrap around to the opposite surface of the substrate. The gap between the chip elements 21 is cut along the cut line 33 by a known method such as dicer cutting. When cut at the portion of the through hole 10, the electrode terminal 44 whose upper surface and lower surface are electrically connected via the conductive plate 4, the plating layer 5, etc., which covered the through hole.
Thus, the surface-mounted LED 40 as shown in FIG. 6 is completed.

【0023】こうして絶縁性の基体1の対峙する二辺4
2、43に一対の電極端子44、44を有する実装基板
41と、該実装基板41の上面に載置され前記電極端子
44、44の夫々に導電性ペースト22を介して電気的
に接続された一対のチップ電極21bを有するチップ素
子21と、該チップ素子21及び前記実装基板41の上
面の全面を覆うモールド部24とからなる構成の面実装
型LED素子40が得られる。この面実装型LED素子
40をチップ素子21を設けた側の実装基板41の法線
方向から観視した場合には、前記実装基板がモールド部
24より外方に突出していないものとなっている。従っ
て、チップ素子21に対して相対的に必要最低限の大き
さのモールド部24と同程度の大きさの面実装型LED
素子が得られるものとなり、従来のものに比べて大幅な
小型化が図られる。なお、面実装型半導体素子を切断す
る工程等において電極端子44等の一部がモールド部2
4よりも外方に多少はみ出ることがある場合も考えられ
るが、このような場合であっても実質的に突出するもの
ではないので、本願発明に当然に含まれるものである。
In this manner, the two sides 4 of the insulating substrate 1 facing each other
A mounting substrate 41 having a pair of electrode terminals 44, 44 at 2 and 43, and electrically connected via the conductive paste 22 to the respective electrode terminals 44, 44 mounted on the upper surface of the mounting substrate 41. A surface-mounted LED element 40 having a configuration including a chip element 21 having a pair of chip electrodes 21b and a mold portion 24 covering the entire upper surface of the chip element 21 and the mounting substrate 41 is obtained. When the surface mounting type LED element 40 is viewed from the normal direction of the mounting substrate 41 on the side where the chip element 21 is provided, the mounting substrate does not protrude outward from the mold part 24. . Therefore, the surface mount type LED having the same size as the mold portion 24 having the minimum size relative to the chip element 21 is required.
An element can be obtained, and the size can be significantly reduced as compared with the conventional one. In the step of cutting the surface-mount type semiconductor element or the like, a part of the electrode
Although there may be a case in which it slightly protrudes outside the range of 4, it is naturally included in the present invention because even in such a case, it does not substantially protrude.

【0024】前述したようにチップ基板20の上面の殆
ど全面をモールド樹脂23により覆うものとした場合に
は、使用する材質等によってはモールドしたチップ基板
20が反る場合がある。そこで、モールド工程において
図7の断面図に示したようにチップ基板20の貫通孔1
0と平行な複数の溝を有する上型31とし、図8に示し
たような平行な複数列のモールド樹脂23にてチップ基
板がモールドされたものとし、これをカッター32で切
断すれば、チップ基板の反りを簡単に抑止しながら、略
台形状のモールド部を有する面実装型LED素子40を
容易に作成することができるものとなる。但し、この場
合にはチップ基板と上型31との位置合わせを正確に行
なわないと発光部位置が実装基板からずれたものになる
点は従来のものと同じである。
As described above, when almost the entire upper surface of the chip substrate 20 is covered with the molding resin 23, the molded chip substrate 20 may warp depending on the material used. Therefore, in the molding process, as shown in the cross-sectional view of FIG.
An upper die 31 having a plurality of grooves parallel to 0 is formed, and a chip substrate is molded with a plurality of parallel rows of molding resin 23 as shown in FIG. The surface-mounted LED element 40 having the substantially trapezoidal mold portion can be easily manufactured while easily suppressing the warpage of the substrate. However, in this case, if the position of the chip substrate and the upper die 31 are not accurately adjusted, the position of the light emitting unit will be shifted from the mounting substrate, which is the same as the conventional one.

【0025】次に本発明者による面実装型LED素子4
0の具体的な検討結果について説明する。厚さ0.06
mmのポリエステルフィルム製の基体1の一方の面に厚
さ0.02mmの銅箔2を貼着し、0.8mm幅のスト
ライプ状の複数の貫通孔10を0.8mm幅の基体1が
貫通孔間に残るように抜き落とし、他方の面全面に厚さ
0.02mmの銅箔を貼付した後に、銅の無電界メッキ
を行なうことで表面にメッキ層5を形成した。これによ
り基体1の上面及び下面が電気的に接続されていること
を確認した。また、断面を顕微鏡にて観察したところ基
体1の貫通孔内面にもメッキ層5が形成されていること
を確認した。続いて紫外線感光性レジスト6を塗布し、
マスクを用いて露光、現像を行なって所定パターンとな
るようにエッチングを施して隣接する貫通孔側の両方が
鋸歯状としたパターン溝11を基体上面に、貫通孔10
と略平行なストライプ状の離間部12を基体下面に形成
して絶縁部とした。なお、パターン溝11の基体上の最
もパターン溝が狭い部分の寸法を後に載置するLEDチ
ップ素子21の大きさと同程度として、この部分におい
てチップ素子21が良好に半田層8と接続できるように
している。続いて上記基体面に形成したパターン溝11
の最も間隔が狭い部分間に絶縁層7を、所定部分以外の
メッキ層5を覆うように絶縁層7’を基体1上面に同時
に形成した後、電界メッキにて露出しているメッキ層5
の上に半田層8、8’を形成した後に、マーク9を印刷
してチップ基板20を完成させた。
Next, the surface mount type LED element 4 of the present inventor
A specific study result of 0 will be described. 0.06 thickness
A copper foil 2 having a thickness of 0.02 mm is attached to one surface of a base 1 made of a polyester film having a thickness of 0.8 mm, and the base 1 having a width of 0.8 mm passes through a plurality of stripe-shaped through holes 10 having a width of 0.8 mm. After the copper foil having a thickness of 0.02 mm was adhered to the entire surface of the other surface, copper was electrolessly plated to form a plating layer 5 on the surface. This confirmed that the upper and lower surfaces of the base 1 were electrically connected. When the cross section was observed with a microscope, it was confirmed that the plating layer 5 was also formed on the inner surface of the through-hole of the base 1. Subsequently, an ultraviolet-sensitive resist 6 is applied,
Exposure and development are performed using a mask, and etching is performed so as to form a predetermined pattern. A pattern groove 11 in which both adjacent through-holes are saw-toothed is formed on the upper surface of the base, and the through-hole 10 is formed.
A striped spacing portion 12 substantially parallel to the above was formed on the lower surface of the base to form an insulating portion. The dimension of the portion of the pattern groove 11 where the pattern groove is narrowest on the substrate is set to be substantially the same as the size of the LED chip element 21 to be mounted later, so that the chip element 21 can be connected to the solder layer 8 well in this portion. ing. Then, the pattern groove 11 formed on the base surface
After the insulating layer 7 'is formed simultaneously on the upper surface of the substrate 1 so as to cover the plating layer 5 other than the predetermined portion, the insulating layer 7 is formed between the portions having the narrowest interval, and then the plating layer 5 exposed by the electrolytic plating is formed.
After forming the solder layers 8 and 8 ′ on the substrate, the mark 9 was printed to complete the chip substrate 20.

【0026】LEDチップ素子21はGaAs基板の上
にGaAlAs系化合物を成長させてGaAs基板と略
平行なPN接合面21aが形成され、GaAs基板底面
とこの底面と対向する最上面に一対のチップ電極21b
を有する0.3mm×0.3mm×0.3mmのLED
チップ21を多数個用いた。このLEDチップ素子21
をPN接合面21aが基体1と略直交し、対向するチッ
プ電極21bが隣接する貫通孔10と略平行方向になる
ようにチップ基板20の絶縁層7上に載置し、銀ペース
ト22により半田層8、8と一対のチップ電極21bの
夫々を接合した。
The LED chip element 21 is formed by growing a GaAlAs-based compound on a GaAs substrate to form a PN junction surface 21a substantially parallel to the GaAs substrate. A pair of chip electrodes are provided on the bottom surface of the GaAs substrate and on the uppermost surface opposed to the bottom surface. 21b
0.3mm × 0.3mm × 0.3mm LED with LED
Many chips 21 were used. This LED chip element 21
Is placed on the insulating layer 7 of the chip substrate 20 so that the PN junction surface 21a is substantially orthogonal to the base 1 and the opposing chip electrode 21b is in a direction substantially parallel to the adjacent through-hole 10. The layers 8, 8 and the pair of chip electrodes 21b were joined.

【0027】これを図4に示したような型にセットして
透明エポキシ樹脂によりモールドした後、切断して長さ
Ls=1.0mm、幅Ws=0.5mm、高さHs=
0.5mmの面実装型LED素子40を得た。この素子
はモールド部より外側に基板及び端子等が外部に突出し
ていず、モールド部24の大きさと面実装型素子40の
大きさが略等しい直方体形状の小型のものとなった。
This was set in a mold as shown in FIG. 4, molded with a transparent epoxy resin, cut, and cut into a length Ls = 1.0 mm, a width Ws = 0.5 mm, and a height Hs =
A 0.5 mm surface-mounted LED element 40 was obtained. This device had a rectangular parallelepiped small size in which the size of the mold portion 24 and the size of the surface mount device 40 were substantially the same, since the substrate, the terminals, and the like did not protrude outside the mold portion.

【0028】従来の電極端子部がモールド部より外方に
突出している面実装型LED素子の例として前記したス
タンレー電気株式会社製のBR1111Cと同じ形状の
面実装型素子を上記と同じ0.3mm×0.3mm×
0.3mmのLEDチップ91を用いて比較検討した場
合について説明する。
As an example of a conventional surface mount type LED device in which electrode terminal portions protrude outward from the mold portion, a surface mount type device having the same shape as BR1111C manufactured by Stanley Electric Co., Ltd. is used. × 0.3mm ×
A case where a comparative study is performed using the 0.3 mm LED chip 91 will be described.

【0029】図12に示したようにLEDチップ91の
チップ電極面の一方をチップ基板94に取付け、反対側
の電極をLEDチップ91の上面からワイヤーボンディ
ングにて電極端子95に接続するものとして基板に取り
付けた。これを図13に示したような型によりモールド
して図15に示すような面実装型LED素子90を得
た。この素子の大きさは長さLs=1.6mm、幅Ws
=0.8mm、高さHs=0.7mmで、型おさえ部を
モールド部のLs方向両側に夫々0.2mm有してい
た。
As shown in FIG. 12, one of the chip electrode surfaces of the LED chip 91 is attached to the chip substrate 94, and the other electrode is connected to the electrode terminal 95 by wire bonding from the upper surface of the LED chip 91. Attached to. This was molded with a mold as shown in FIG. 13 to obtain a surface-mounted LED element 90 as shown in FIG. The size of this element is length Ls = 1.6 mm and width Ws
= 0.8 mm, height Hs = 0.7 mm, and the mold holding portions had 0.2 mm on both sides of the mold portion in the Ls direction.

【0030】小型化を図るためモールド部93より外方
に突出する電極端子95の寸法を小さくするべくモール
ド工程における上型96と電極端子95との面接触部、
即ち型おさえ部98の寸法を0.2mmから0.1mm
に変更して長さLs=1.4mmの素子を得たが、歩留
りが低下した。また、型おさえ部98の寸法を0.1m
mより小さくする検討も行なったがモールド樹脂が裏面
に回り込むものとなって略全数が不良となり、これ以上
型おさえ部を小さくすることは現実的には不可能であっ
た。
In order to reduce the size of the electrode terminal 95 protruding outward from the mold portion 93 in order to reduce the size, a surface contact portion between the upper die 96 and the electrode terminal 95 in the molding process,
That is, the size of the mold holding portion 98 is set to 0.2 mm to 0.1 mm.
Was obtained, an element having a length Ls = 1.4 mm was obtained, but the yield was reduced. Also, the size of the mold holding section 98 is 0.1 m.
An attempt was made to make the mold resin smaller than m. However, almost all of the mold resin became defective because the mold resin wrapped around the back surface, and it was practically impossible to further reduce the mold holding portion.

【0031】そこで、LEDチップの大きさを同一とし
て本発明の面実装型素子についてもモールド部の大きさ
を種々に変えてどれ位小さくできるか検討した。LED
チップのチップ基板と接触する面の表面積をAc、面実
装型半導体素子を前記チップを設けた側の基板法線方向
から観視した際の該素子の投影面積をAsとすると、上
記した従来の面実装型LED素子ではAs/Ac=
(1.6〜1.4×0.7)/(0.3×0.3)=1
2.4〜10.8、本発明の先の実施例の場合にはAs
/Ac=(1.0×0.5)/(0.3×0.3)=
5.55となる。LEDチップの大きさを同一として面
実装型素子の大きさを変えてAs/Acについて各種検
討してみたが、従来の方法ではAs/Acが10.0以
下の面実装型素子とすると、前記した理由により実質的
には9.0以下の面実装型素子とすることができない。
しかし、本発明ならばAs/Acを優に9.0以下とす
ることができ、特にAs/Acが7.0以下という従来
の方法では到底得ることのできない小型の面実装型LE
D素子、チップ素子より一回り大きい程度のの印象しか
与えない非常に小型のものを得ることができる。
Therefore, it was examined how much the size of the mold part can be variously reduced for the surface mount type device of the present invention with the same size of the LED chip. LED
Assuming that the surface area of the surface of the chip in contact with the chip substrate is Ac and the projected area of the surface-mounted semiconductor element when viewed from the normal direction of the substrate on the side where the chip is provided is As, As / Ac =
(1.6-1.4 × 0.7) / (0.3 × 0.3) = 1
2.4 to 10.8, In the case of the previous embodiment of the present invention, As
/Ac=(1.0×0.5)/(0.3×0.3)=
It becomes 5.55. Various studies were conducted on As / Ac by changing the size of the surface-mounted element while keeping the size of the LED chip the same. However, in the conventional method, assuming that the surface-mounted element had As / Ac of 10.0 or less, For this reason, a surface-mount type device having a size of 9.0 or less cannot be obtained.
However, according to the present invention, As / Ac can be reduced to 9.0 or less, and in particular, a small surface-mount LE which cannot achieve As / Ac by 7.0 or less can not be obtained at all.
It is possible to obtain a very small device that gives an impression only slightly larger than the D device and the chip device.

【0032】また、先の実施例ではワイヤーボンディン
グを使用しないでLEDチップ電極21bと半田層8を
直接接続する構造としているので面実装型素子の長さ方
向及び高さ方向の寸法も小さいものとすることができ
る。従来ではLEDチップの対向する2面に電極を有し
ており、その2面がチップ基板の上下面に位置するよう
に載置してワイヤーボンディングする必要があったの
で、高さを小さくすることが不可能であったが、本願発
明ではワイヤーボンディングを不要とし、更にチップ素
子の厚み自体を小さくしたLEDチップ素子21として
より一層高さの低い素子とすることもできる。例えばL
EDチップ素子21のチップ基板に載置した際の厚みを
Dcとしたとき、従来の面実装型素子では載置するLE
DチップはGaAs基板ウエハーの厚さと略等しいDc
=0.3mm以下とすることは難しく、更にワイヤーボ
ンディングするための高さも必要である。本願発明では
GaAs基板ウエハーから切り出すLEDチップ素子の
寸法を小さくすれば、例えばDc=0.18mmのチッ
プ素子とすることもできるものとなり、また、ワイヤー
ボンディング接続する分の高さも不要である。従って面
実装型素子自体の高さも格段に小さくすることができ
る。
In the above embodiment, since the LED chip electrode 21b and the solder layer 8 are directly connected without using wire bonding, the dimension in the length direction and the height direction of the surface mount element is small. can do. Conventionally, the LED chip had electrodes on two opposing surfaces, and it was necessary to place the two surfaces on the upper and lower surfaces of the chip substrate for wire bonding. However, according to the present invention, the LED chip element 21 in which the wire bonding is unnecessary and the thickness of the chip element itself is reduced can be further reduced. For example, L
Assuming that the thickness of the ED chip element 21 when it is mounted on the chip substrate is Dc, the LE mounted on the conventional surface mount element is
D chip is Dc approximately equal to the thickness of the GaAs substrate wafer.
= 0.3 mm or less is difficult, and a height for wire bonding is also required. In the present invention, if the size of the LED chip element cut out from the GaAs substrate wafer is reduced, a chip element with Dc = 0.18 mm can be obtained, for example, and the height for wire bonding connection is not required. Therefore, the height of the surface mount element itself can be significantly reduced.

【0033】また、前記実施例のようにワイヤーボンデ
ィングを用いないで実装基板の一対の電極端子44,4
4の夫々に繋がっている半田層8、8にLEDチップ電
極21bを直接導電性ペースト22により接続する構成
とした場合には、従来のようにワイヤーボンディング接
続するために必要な金メッキ層をチップ素子基板に設け
る必要がなくなり、工程の簡略化とコストの低減を図る
ことも可能である。
Further, a pair of electrode terminals 44 and 4 of the mounting board are used without using wire bonding as in the above embodiment.
In the case where the LED chip electrode 21b is directly connected to the solder layers 8 and 8 connected to the respective elements 4 by the conductive paste 22, a gold plating layer necessary for wire bonding connection as in the related art is used for the chip element. It is not necessary to provide it on the substrate, so that the process can be simplified and the cost can be reduced.

【0034】今までの説明では実装基板41に設けるチ
ップ素子20として直方体形状のチップ素子の対向する
2面の全面にチップ電極21bを有するチップ素子21
の例で説明したが、サファイア等の絶縁性の材料の上に
PN接合面を形成し、一方のサファイア等の面上にP型
チップ電極及びN型チップ電極を有するチップ素子等を
用いる場合には上記した実施例の方法ではチップ素子を
接合できない。そのような場合には、片側の面上に形成
してあるP型及びN型チップ電極から半田層8にワイヤ
ーボンディングにより接続する手段等を用いる必要があ
る。この場合には、半田層8の代わりに金メッキ層を公
知の手段で形成したチップ基板を準備しておけば良い。
なお、このような場合には両端に一対のチップ電極を有
する前記した実施例のチップ素子を用いる場合に比べ
て、面実装素子の高さを前記した実施例ほど低いものと
することはできないが、チップ素子の直横の半田層8、
8と接続するものであるので面実装型LED素子40の
長さ及び幅については前述した実施例と同等に小型化す
ることができるものとなり、前記モールド部を前記チッ
プを設けた側の基板法線方向から観視した際に前記基板
及び端子が該モールド部より外周に突出していない小型
の面実装型素子が得られるものとなる。なお、チップ素
子としてLED(発光ダイオード)を例に説明したが本
願発明はLEDに限らず他の発光素子、受光素子等の半
導体素子であっても構わないものである。
In the above description, as the chip element 20 provided on the mounting substrate 41, a chip element 21 having chip electrodes 21b on the entire two opposing surfaces of a rectangular chip element is described.
However, when a PN junction surface is formed on an insulating material such as sapphire and a chip element or the like having a P-type chip electrode and an N-type chip electrode on one of the sapphire surfaces is used. In the method described above, the chip element cannot be joined by the method of the above embodiment. In such a case, it is necessary to use means for connecting the P-type and N-type chip electrodes formed on one surface to the solder layer 8 by wire bonding. In this case, a chip substrate having a gold plating layer formed by a known means instead of the solder layer 8 may be prepared.
In such a case, the height of the surface mount element cannot be made as low as that of the above-described embodiment as compared with the case of using the chip element of the above-described embodiment having a pair of chip electrodes at both ends. A solder layer 8 right next to the chip element,
8, the length and width of the surface-mounted LED element 40 can be reduced in size as in the above-described embodiment. When viewed from the line direction, a small surface-mounted element in which the substrate and the terminal do not protrude from the mold portion to the outer periphery can be obtained. Although an LED (light emitting diode) has been described as an example of the chip element, the present invention is not limited to the LED, and may be another light emitting element or a semiconductor element such as a light receiving element.

【0035】以上面実装型LED素子の実施例に沿って
説明したがこれに制限されるものではなく、モールドし
たチップ基板をカッター等で切断する位置を前述した位
置以外のものにして異なる形状の面実装型半導体素子を
得たり、チップ素子を載置する箇所を低くしその他の絶
縁層7’等を厚い所定形状のものとして略すり鉢状の反
射面を兼用する絶縁層7’等にする等の種々の当業者に
自明な変形も本願発明に含まれる。また、モールド部に
レンズ効果を有するカットを施して光の指向性もしくは
拡散性を高める等の処理を施したり、モールド部表面に
反射層を設ける等を施すこともできる。
Although the embodiment of the surface-mount type LED element has been described above, the present invention is not limited to this. A surface-mount type semiconductor element is obtained, or a place where a chip element is mounted is lowered, and other insulating layers 7 ′ and the like are formed to have a thick predetermined shape to form an insulating layer 7 ′ which also serves as a substantially mortar-shaped reflecting surface. Various modifications obvious to those skilled in the art are also included in the present invention. Further, a process such as enhancing the directivity or diffusivity of light by performing a cut having a lens effect on the mold portion, or providing a reflective layer on the surface of the mold portion may be performed.

【0036】[0036]

【発明の効果】以上に説明したように、本発明により前
記モールド部を前記チップを設けた側の基板法線方向か
ら観視した際に前記基板及び電極端子が該モールド部よ
り外周に突出していない小型の面実装型素子が得られる
ものとなる。LEDチップ素子を保護するのに最低限必
要なモールド部の大きさと同等以下の大きさの投影面積
の実装基板とすることができ、面実装型半導体素子の外
形寸法をLEDを保護するために最低限必要なモールド
部の大きさと殆ど同じ外形寸法の格別に小型化した面実
装型半導体素子とすることができる。また、面実装型半
導体素子を作成する際に複数の半導体素子を載置する1
枚の基体に従来に比べて高密度に載置することが可能と
なり、効率よく量産できるものとなり、総じてコストを
低減できるものである。
As described above, according to the present invention, when the mold portion is viewed from the normal direction of the substrate on which the chip is provided, the substrate and the electrode terminals project outward from the mold portion. Thus, a small and small surface-mounted element can be obtained. It is possible to use a mounting board with a projected area equal to or smaller than the minimum size of the mold part necessary to protect the LED chip element, and to reduce the external dimensions of the surface-mount type semiconductor element to protect the LED. It is possible to provide a particularly small-sized surface-mounted semiconductor element having an outer dimension almost the same as the size of the required mold part. Further, when a surface-mount type semiconductor device is produced, a plurality of semiconductor devices are mounted.
This makes it possible to place the substrates on a single substrate at a higher density than in the past, and to efficiently mass-produce the substrates, thereby reducing the cost as a whole.

【0037】また、モールド部より外方に突出する型お
さえ部がなくなったので従来の最大外形と同一外形の面
実装型素子とした場合にはLEDチップ素子の発光部の
領域が拡大し光学特性、特に指向性を向上すると共に、
マウンター等の自動実装機などでこの面実装型半導体素
子を取り扱う際に該素子を真空吸着してプリント配線板
の所定位置に実装する場合の取り扱い性が向上する。
Further, since there is no mold holding portion protruding outward from the molded portion, the area of the light emitting portion of the LED chip element is enlarged in the case of a surface mount type device having the same outer shape as the conventional maximum outer shape. , And especially improve directivity,
When handling the surface-mounted semiconductor device by an automatic mounting machine such as a mounter, the handleability is improved when the device is vacuum-adsorbed and mounted at a predetermined position on a printed wiring board.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明のチップ基板の製造工程を示す概略説明
図である。
FIG. 1 is a schematic explanatory view showing a manufacturing process of a chip substrate of the present invention.

【図2】本発明のチップ基板の一部を破断して説明する
斜視図である。
FIG. 2 is a perspective view illustrating a chip substrate according to the present invention with a part thereof cut away.

【図3】図2のチップ基板にLEDチップを接合した状
態を示す斜視図である。
FIG. 3 is a perspective view showing a state where an LED chip is bonded to the chip substrate of FIG. 2;

【図4】本発明の樹脂モールド工程を示す概略説明図で
ある。
FIG. 4 is a schematic explanatory view showing a resin molding step of the present invention.

【図5】図4でモールドしたチップ基板を切断する際の
状態を説明する概略断面斜視図である。
FIG. 5 is a schematic cross-sectional perspective view illustrating a state when the chip substrate molded in FIG. 4 is cut.

【図6】本発明の面実装型半導体素子の一例を示す斜視
図である。
FIG. 6 is a perspective view showing an example of the surface-mount type semiconductor device of the present invention.

【図7】本発明の別の樹脂モールド工程を示す概略説明
図である。
FIG. 7 is a schematic explanatory view showing another resin molding step of the present invention.

【図8】図7でモールドしたチップ基板を切断する際の
状態を説明する概略断面斜視図である。
FIG. 8 is a schematic cross-sectional perspective view illustrating a state when the chip substrate molded in FIG. 7 is cut.

【図9】従来の面実装型LEDの製造工程を説明するチ
ップ基板の概略断面図である。
FIG. 9 is a schematic cross-sectional view of a chip substrate for explaining a manufacturing process of a conventional surface mount LED.

【図10】従来の面実装型LEDの製造工程を説明する
チップ基板の概略断面図である。
FIG. 10 is a schematic cross-sectional view of a chip substrate for explaining a manufacturing process of a conventional surface mount LED.

【図11】従来の面実装型LEDの製造工程を説明する
チップ基板の概略平面図である。
FIG. 11 is a schematic plan view of a chip substrate for explaining a manufacturing process of a conventional surface mount LED.

【図12】従来の面実装型LEDの製造工程を説明する
チップ基板の概略断面図である。
FIG. 12 is a schematic cross-sectional view of a chip substrate for explaining a manufacturing process of a conventional surface mount LED.

【図13】従来の樹脂モールド工程を示す概略説明図で
ある。
FIG. 13 is a schematic explanatory view showing a conventional resin molding process.

【図14】図13でモールドしたチップ基板を切断する
際の状態を説明する概略平面図である。
FIG. 14 is a schematic plan view illustrating a state in which the chip substrate molded in FIG. 13 is cut.

【図15】従来の面実装型LEDの一例を示す斜視図で
ある。
FIG. 15 is a perspective view showing an example of a conventional surface mount LED.

【図16】従来の別の面実装型LEDの製造方法を示す
概略斜視図である。
FIG. 16 is a schematic perspective view showing a method for manufacturing another conventional surface-mounted LED.

【図17】従来の別の面実装型LEDを示す概略断面斜
視図である。
FIG. 17 is a schematic cross-sectional perspective view showing another conventional surface-mounted LED.

【符号の説明】[Explanation of symbols]

1 基体 2 銅箔 4 導電板 5 メッキ層 7、7’絶縁層 8、8’半田層 10 貫通孔 20 チップ基板 21 チップ素子 24 モールド部 40 面実装型LED素子 41 実装基板 42、43 辺 44 電極端子 90 面実装型LED素子 91 LEDチップ 92 ワイヤー 93 モールド部 94 チップ基板 95 電極端子 98 型おさえ部 DESCRIPTION OF SYMBOLS 1 Base | substrate 2 Copper foil 4 Conductive plate 5 Plating layer 7, 7 'insulating layer 8, 8' solder layer 10 Through-hole 20 Chip board 21 Chip element 24 Mold part 40 Surface mount type LED element 41 Mounting board 42, 43 side 44 Electrode Terminal 90 Surface mount type LED element 91 LED chip 92 Wire 93 Mold part 94 Chip substrate 95 Electrode terminal 98 Type holding part

───────────────────────────────────────────────────── フロントページの続き (72)発明者 平間 聡 神奈川県横浜市青葉区荏田西2−14−1 スタンレー電気株式会社横浜技術センター 内 ──────────────────────────────────────────────────の Continued on the front page (72) Inventor Satoshi Hirama 2-14-1 Edanishi, Aoba-ku, Yokohama-shi, Kanagawa Prefecture Stanley Electric Co., Ltd. Yokohama Technical Center

Claims (10)

【特許請求の範囲】[Claims] 【請求項1】 絶縁性の基体の対峙する二辺の側に設
けた一対の導電パターンによる端子部を有する基板と、
基板の一方の表面に設け前記端子部と接続する半導体チ
ップと、前記チップを覆うモールド部を有する面実装型
半導体素子において、前記モールド部は前記基板の厚さ
よりも厚く、且つ、前記基板の少なくとも一方の面の全
面を覆い、前記チップを設けた側の基板法線方向から前
記モールド部を観視した際に前記基板及び端子部が該モ
ールド部より外周に突出していないことを特徴とする面
実装型半導体素子。
A substrate having a pair of conductive pattern terminals provided on two opposite sides of an insulating substrate;
A semiconductor chip provided on one surface of the substrate and connected to the terminal portion, and a surface-mount type semiconductor device having a mold portion covering the chip, wherein the mold portion is thicker than the thickness of the substrate, and at least a portion of the substrate. A surface covering the entire surface of the one surface, wherein the substrate and the terminal portion do not protrude from the mold portion to the outer periphery when the mold portion is viewed from the normal direction of the substrate on which the chip is provided. Mounting type semiconductor element.
【請求項2】 前記面実装型半導体素子の基板法線方
向への投影面積をAs、前記基板に載置した半導体チッ
プのチップ基板に載置する面の面積をAcとしたとき、 As/Ac≦10.0 であることを特徴とする請求項1記載の面実装型半導体
素子。
2. As / Ac, where As is the projected area of the surface-mounted semiconductor element in the normal direction of the substrate, and Ac is the area of the surface of the semiconductor chip mounted on the substrate mounted on the chip substrate. The surface-mounted semiconductor device according to claim 1, wherein ≤ 10.0.
【請求項3】 前記面実装型半導体素子の長さをL
s、幅をWs、高さをHsとしたとき、 Ls≦1.5
mm Ws≦0.5mm、Hs≦0.5mmであることを特徴
とする請求項1又は2記載の面実装型半導体素子。
3. The length of the surface-mount type semiconductor device is L.
s, width Ws and height Hs, Ls ≦ 1.5
The surface-mounted semiconductor device according to claim 1, wherein mm Ws ≦ 0.5 mm and Hs ≦ 0.5 mm.
【請求項4】 前記半導体チップが受光素子であるこ
とを特徴とする請求項1から3のいずれか記載の面実装
型半導体素子。
4. The semiconductor device according to claim 1, wherein said semiconductor chip is a light receiving element.
【請求項5】 前記半導体チップが発光素子であるこ
とを特徴とする請求項1から3のいずれか記載の面実装
型半導体素子。
5. The surface-mounted semiconductor device according to claim 1, wherein said semiconductor chip is a light-emitting device.
【請求項6】 前記半導体チップがpn接合を有する
発光素子であり、pn接合面の端面が基体上面側に位置
するように設けられていることを特徴とする請求項1か
ら3のいずれか記載の面実装型半導体素子。
6. The semiconductor chip according to claim 1, wherein the semiconductor chip is a light-emitting element having a pn junction, and the semiconductor chip is provided such that an end face of the pn junction is located on an upper surface of the base. Surface mount type semiconductor device.
【請求項7】 前記基板表面には半田層が形成されて
おり、該半田層と前記半導体チップが導電性ペーストに
て接続されていることを特徴とする請求項1から6のい
ずれか記載の面実装型半導体素子。
7. The semiconductor device according to claim 1, wherein a solder layer is formed on the surface of the substrate, and the solder layer and the semiconductor chip are connected by a conductive paste. Surface mount type semiconductor device.
【請求項8】 複数の並列した貫通孔を有する絶縁性
基体と、前記基体の一方の面側で前記貫通孔を覆う導電
性の板材と、前記基体の他方の面側の基体表面及び前記
貫通孔内面を覆い該貫通孔部で前記導電性の板材と電気
的に接続する導電層とを有し、前記導電性板材は前記基
体上の位置で該板材の一部が除去されてパターン溝が形
成され、前記基体の他方の面に形成されている導電性層
には該基体の他方の面側で該導電性層の一部が除去され
て離間部が前記貫通孔と略平行に形成されていることを
特徴とする面実装型半導体素子を載置するチップ基板。
8. An insulating substrate having a plurality of parallel through holes, a conductive plate material covering the through holes on one surface side of the substrate, a substrate surface on the other surface side of the substrate, and the through hole. A conductive layer that covers an inner surface of the hole and is electrically connected to the conductive plate at the through-hole portion, and the conductive plate is partially removed at a position on the base to form a pattern groove. In the conductive layer formed on the other surface of the base, a part of the conductive layer is removed on the other surface side of the base, and a separated portion is formed substantially in parallel with the through hole. A chip substrate on which a surface-mount type semiconductor element is mounted.
【請求項9】 前記チップ基板を準備する工程と、前
記チップ基板の導電性板材に設けたパターン溝の部分に
絶縁層を介して複数の半導体チップを載置する工程と、
該半導体チップと前記導電性板材とを電気的に接続する
工程と、前記複数の半導体チップ及び該チップを設けた
側の表面を絶縁性の樹脂によりモールドする工程と、モ
ールドしたチップ基板を前記複数の半導体チップの間隙
で切断する工程とを有することを特徴とする面実装型半
導体素子の製造方法。
9. A step of preparing the chip substrate, and a step of mounting a plurality of semiconductor chips via an insulating layer in a portion of a pattern groove provided in a conductive plate material of the chip substrate;
A step of electrically connecting the semiconductor chip and the conductive plate material; a step of molding the plurality of semiconductor chips and a surface on the side where the chips are provided with an insulating resin; Cutting at a gap between the semiconductor chips.
【請求項10】 前記樹脂モールドは前記複数の半導
体チップを覆うように前記基板表面の略全面を絶縁性の
樹脂によりモールドすることを特徴とする請求項9記載
の面実装型半導体素子の製造方法。
10. The method according to claim 9, wherein the resin mold covers substantially the entire surface of the substrate with an insulating resin so as to cover the plurality of semiconductor chips. .
JP12014097A 1997-04-24 1997-04-24 Surface mount type semiconductor device Expired - Fee Related JP3245378B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12014097A JP3245378B2 (en) 1997-04-24 1997-04-24 Surface mount type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12014097A JP3245378B2 (en) 1997-04-24 1997-04-24 Surface mount type semiconductor device

Publications (2)

Publication Number Publication Date
JPH10303465A true JPH10303465A (en) 1998-11-13
JP3245378B2 JP3245378B2 (en) 2002-01-15

Family

ID=14778964

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12014097A Expired - Fee Related JP3245378B2 (en) 1997-04-24 1997-04-24 Surface mount type semiconductor device

Country Status (1)

Country Link
JP (1) JP3245378B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007201171A (en) * 2006-01-26 2007-08-09 Sony Corp Light source device and display device
JP2007243225A (en) * 2007-06-20 2007-09-20 Sony Corp Light source apparatus and display apparatus

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007201171A (en) * 2006-01-26 2007-08-09 Sony Corp Light source device and display device
JP2007243225A (en) * 2007-06-20 2007-09-20 Sony Corp Light source apparatus and display apparatus

Also Published As

Publication number Publication date
JP3245378B2 (en) 2002-01-15

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