JPH10302483A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize drastic time reduction with a simple device by installing both n+1 sets of sectors and registers; when the i-th sector is designated, exchanging the value of the register corresponding to this sector with the value of the register corresponding to the j-th sector; and designating the sector based on the value of the register after exchange. SOLUTION: The higher-level bits of the external address are compared with the value of each register 2a-2h to exchange the value of a specified sector with the registered value of the spare sector. The position of the spare sector is different between the case of the initial state or the first exchange and the case where it is previously exchanged one time or more, and the arrangement of sectors and the values of the registers are shown in the figure. Since the maximum value of the address space 1 which can be seen externally is 6FF, the value of the register 2h is not included in the external address and the spare sector becomes a sector of 700-7FF of the memory space 3. However, when exchange is already executed one time or more, the sector specified at the previous exchange becomes the spare sector. By this, drastic time reduction is realized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device (typically, a flash memory) which divides an address space into a plurality of areas (sectors) of the same size and performs an erase operation on a sector basis.

In recent years, for storing codes and BIOS (basis in
put output system) EPROM (electrically era
sable programmable read only memory) to flash memory, but with this, it is easy to rewrite on-board, and it can be used not only for OS and application programs but also for file storage. Various market requirements have emerged.

[0003]

2. Description of the Related Art FIG. 5 is a conceptual diagram of a conventional flash memory which can meet this kind of demand (however, a conceptual diagram of memory space and address designation).
This is a flash memory having an address space up to the FF and dividing the space into seven sectors (# 0 to # 6) of the same size. The address space viewed from the outside is 00 to 6FF as indicated by a vertical line 1 with an arrow on the left side of the figure.
When an arbitrary address is given, the upper 4 bits are compared with the values of the sector registers 2a to 2g of the address decoder, and the matching sector is designated.

For example, when an address 2 ** (* is an arbitrary value from 0 to F) is given, the upper 4 bits of the binary array are [0010], and the third uppermost sector register 2c Since the value matches the value, sector # 2 is designated. In the case of data write, data can be written after erasing the sector # 2.

[0005]

As described above, the configuration in which the erasing operation is performed in sector units is advantageous in that the time can be considerably shortened. There is a drawback that, as compared with a high-speed memory such as a RAM (random access memory), for example, the speed cannot be denied.

[0006] Therefore, an object of the present invention is to provide a useful technique capable of greatly reducing the time with a simple device.

[0007]

The invention according to claim 1 is
The address space is divided into n sectors of the same size, the upper bits of an external address signal are compared with the values of n registers provided for each sector, and one sector is designated. In the semiconductor memory device which performs read / write and required operations on the specified sector, the number of sectors and registers is n + 1, and when the specified sector is the i-th sector (i is 0 to n-1), Exchange means for exchanging the value of the register corresponding to the i-th sector with the value of the register corresponding to the j-th sector (j is i in the previous exchange, but n in the first exchange); The operation for designating the one sector is performed based on the value of the register after the exchange.

According to this, the n-th sector or the i-th sector at the time of the previous exchange unless it is the first exchange is always reserved as a spare sector. Therefore, if this spare sector is erased in the background,
Since the spare sector is always designated by an external address, there is no need to perform erasure, and the time is greatly reduced. Moreover, if the erasure of the spare sector after the replacement is performed as late as possible, the backup data of the addressed sector remains until the erasure, and recovery in the event of data loss becomes possible.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing one embodiment of a semiconductor memory device according to the present invention, and is an example of application to a flash memory in which an address space is divided into a plurality of sectors of the same size. In FIG. 1, reference numeral 1 schematically illustrates an externally visible address space (00 to 6FF), and reference numeral 3 schematically illustrates a physical storage space corresponding to the address space 1. The storage space 3 has n pieces of the same size (n in the figure).
= 7) (# 0 to # 6), and one sector (#R) of the same size is continuously added to the sectors exceeding the address space 1. Also, register 2 corresponding to all sectors (# 0 to #R)
a to 2h are provided in an address decoder (not shown), and in the initial state (immediately after power-on or immediately after reset), the illustrated values are stored in the registers 2a to 2h. That is, the register 2a corresponding to the sector # 0 has

[0000] is stored in the register 2b corresponding to the sector # 1, and [0001] is stored in the register 2c corresponding to the sector # 2.
Is [0010] in the register 2 corresponding to the sector # 3.
[0011] is stored in d, and [0111] is stored in the register 2h corresponding to the sector #R.

Here, the values stored in the registers 2a to 2h indicate the address range of each sector. For example,
Focusing on the sector # 2, the address range of the sector # 2 is 200 to 2FF, and [ 0010 , 0
000,0000] - [0010, 1111,111
1]. The value of the upper bit indicated by the underline in the binary notation is always unchanged within the address range of the sector # 2. That is, in the register 2c corresponding to the sector # 2, the value of the invariable part (underline part) of the binary notation is stored. Other registers 2a, 2b, 2d-2
h, the same applies to each sector # 1, # 2, # 4
The value of the invariable part in the binary notation of the address range of # 6 and #R is stored.

4 corresponds to the "exchange means" described in the first aspect of the invention. The specific configuration of the exchange means 4 is not particularly limited, but the point is that it has only the following functions. Upper bits of external address and each register 2a
A function to specify one sector by comparing the value with the value of ~ 2h. A function for exchanging the register value of the sector specified by the above with the register value of the spare sector. Here, the position of the spare sector differs between the initial state or the case of the first exchange and the case where one or more exchanges have already been performed. The sector arrangement and register values in the initial state or at the time of the first exchange are as shown in the figure, and the maximum value of the address space 1 seen from the outside is 6
Since it is an FF, the value of the register 2h is not included in the external address. Therefore, the spare sector in this case is a sector of 700 to 7FF in the storage space 3. However, if one or more exchanges have already been performed, The sector specified at the time of the previous exchange becomes a spare sector.

A description will be given of some specific examples of such a configuration. For example, at the time of the first replacement, as shown in FIG. 2, the upper bits of the binary notation are [0011].
When an external address is given, since the value matches the value of the register 2d (see FIG. 1), first, the exchange means 4
The exchange unit 4 specifies the sector of 00 to 3FF (sector # 3 in FIG. 1), and then exchanges the value of the register 2d with the value of the register 2h of the spare sector (sector #R in FIG. 1). FIG. 2 is a state diagram after the register values are exchanged in this manner. As can be understood from FIG. 2, the value [0111] of the register 2d exceeds the externally visible address space 1. Therefore, since 200 to 3FF of the storage space 3 after the exchange becomes invisible from the outside, this sector (200 to 2FF) becomes a new spare sector (#R) and the original spare sector (700 to 7F).
F) will be replaced with sector # 3.

FIG. 3 is a state diagram after the second replacement. For example, when an external address whose upper bit in binary notation is [0101] is given, it matches the value of the register 2f (see FIG. 2).
The exchange unit 4 specifies the sector of 0 to 5FF (sector # 5 in FIG. 2), and then exchanges the value of the register 2f with the value of the register 2d of the spare sector (sector #R in FIG. 2). As can be understood from FIG. 3, after the replacement, the value [0111] of the register 2f exceeds the address space 1 seen from the outside. Therefore, since 500 to 5FF of the storage space 3 after the exchange becomes invisible from outside,
This sector (500-5FF) is replaced with a new spare sector (#
R) and the original spare sector (300-3FF)
.., Which is also the sector specified during the previous exchange, will be replaced with sector # 5.

As described above, in the present embodiment, the sector designated and the spare sector can be exchanged by a simple device of manipulating the value of the register. Therefore, if the spare sector is erased in advance, the erasure of the sector specified by the address can be omitted, and the time can be greatly reduced. In addition, since the data of the addressed sector remains completely in the newly reserved sector due to the replacement, if erasing is performed as much as possible, backup data can be saved during that time, and unexpected data loss Can also be prepared.

[0015] Also, RA using the data of the spare sector is used.
It is also possible to perform a refresh operation like M.
The refresh operation is an example of an application that should be adopted by all means because it can improve the data retention performance of a flash memory in recent years, particularly when miniaturization and large scale are remarkable. FIG. 4 is a conceptual diagram of the refresh function of the present embodiment. Reference numeral 10 denotes a sector control circuit which manages each sector including the spare sector (# 1 to #R in FIG. 1) and registers 2a to 2g corresponding to these sectors and has the function of the exchange means 4. Is a main memory, and 20 is a refresh control circuit.
a, a power-on circuit 20b, a power supply voltage control circuit 20c,
Checksum storage unit 20d, refresh control unit 20
e, a verify control unit 20f and the like.

An example of the refresh operation in the configuration shown in FIG. 4 is as follows. First, when the power-on is detected by the power-on circuit 20b or when a predetermined time (for example, 168 hours) has elapsed since the power-on (e.g., every predetermined time), the timer 20a stores the checksum. Destruction of data in the main memory 12 is checked using the checksum data stored in advance in the unit 20d, and if there is an abnormality, a memory error is notified to the outside. In this case, external access to the main memory 12 is stopped.

If there is no memory error, start with sector #
From 0 (an arbitrary sector may be used, but starting from # 0 is easier and more reasonable), copy data to spare sector #R, write it back to # 0, and refresh data in sector # 0 . When # 0 is completed, the same operation is performed between # 1 and #R, and this operation is repeated until the last sector # 6. When copying and writing back, check the checksum and try to avoid bit errors. If an error occurs, the operation is re-executed. If the error is not resolved after the predetermined number of times, a memory error (refresh mode error) is notified to the outside.

The checksum at the time of copying and rewriting may be performed while slightly varying the power supply voltage by the power supply voltage control circuit 20c (of course, within an allowable value). For example, when a checksum value is acquired with a power supply voltage lowered by -0.5 V from a normal power supply voltage and a power supply voltage increased by +0.5 V, and compared with a previously stored checksum value, and both match. Indicates that the refresh is normal, and if none of them match, it is determined that the refresh is abnormal. If either one matches, the data of the sector in which the error is found is replaced with the spare sector by using the matched power supply voltage. Then, the sector information is exchanged.

With this configuration, the flash memory can have a refresh function similar to that of the RAM.
Since the data retention performance of a flash memory, which tends to be miniaturized and scaled up, can be remarkably improved, it is possible to obtain a special effect that it can be used not only for an OS or a BIOS but also for any important data retention device.

[0020]

According to the present invention, there is no need to perform erasure each time an address is specified, and a significant time reduction can be achieved.
In addition, a refresh function is also possible, and data storage performance can be greatly improved.

[Brief description of the drawings]

FIG. 1 is a basic conceptual diagram of one embodiment.

FIG. 2 is a conceptual diagram at the time of first replacement of an embodiment.

FIG. 3 is a conceptual diagram at the time of a second replacement in one embodiment.

FIG. 4 is a conceptual diagram of a refresh function according to one embodiment.

FIG. 5 is a basic conceptual diagram of a conventional example.

[Explanation of symbols]

 # 0 to #R: sector 1: address space 2a to 2h: register 4: exchange means

Claims (1)

[Claims] An address space is divided into n sectors of the same size, and one higher sector of an external address signal is compared with the value of n registers provided for each sector to designate one sector. In the semiconductor memory device for performing read / write and required operations on the specified sector, the number of the sectors and the number of registers are each n + 1, and the specified sector is the i-th sector (i is 0 to n− 1)
, The value of the register corresponding to the i-th sector and j
An exchange means for exchanging the register value corresponding to the sector (j is i at the time of the previous exchange, but n at the time of the first exchange), and the one sector is based on the register value after the exchange. A semiconductor memory device that performs the following operation.