JPH10301682A - Bus distributing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To unnecessitate to provide a termination resistance near a memory controller LSI, to provide a bus distribution in which an operation frequency does not fall so much by using bus distribution, to accelerate an electronic circuit device and to make the electronic circuit device inexpensive. SOLUTION: In bus distribution, termination voltages 7 and 8 are connected to both ends of bus distribution 3 which connects plural memory modules 2 through termination resistance 5 and 6, a branch wiring that connects a memory controller LSI1 is provided at the center of the distribution 3. Non-termination wiring connects from branch to the controller LSI1 through serial resistance 4 for reflection prevention near the branch, and the bus distribution does not need to provide termination resistance near the controller LSI1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a bus wiring device.

[0002]

2. Description of the Related Art The operating speed of electronic circuit devices has been increasing year by year, and research and development for realizing higher-speed electronic circuit devices are being actively conducted. When the speed of the electronic circuit device is increased, convenience such as processing that requires a very long time can be performed in a short time or processing that has been considered impossible can be performed. Increased speed of electronic circuit devices reduces processing costs and contributes to improvements in world functions and services. Also, in order to manufacture such an excellent device,
Industry will become even more active.

[0003] The operating speed of an electronic circuit device is determined by the operating frequency of each electronic circuit that is a component of the electronic circuit device. To increase the speed of an electronic circuit device, the operating frequency of each electronic circuit must be increased. Required.

A bus wiring is widely used in electronic circuit devices. This is because the bus wiring can drive a plurality of receivers with one driver, so that the number of drivers can be reduced, and the number of wirings between the driver and the receiver can be reduced, thereby facilitating the manufacture of driver LSIs and wiring boards. Because there is.

[0005] For these reasons, bus wiring is widely used in electronic circuit devices. To realize high-speed electronic circuit devices, not only electronic circuits but also individual electronic circuits are interconnected. It is required to increase the operating frequency of the bus wiring.

Various configurations of the bus wiring are realized depending on the interface specifications of the driver and the receiver and the termination form (Toshihiro Yamada, Yasuhiro Konishi (ULSI, Mitsubishi Electric Corp.)
Development Laboratory): Recent trends in high-speed I / O interface, IEICE IEICE ICD95-31 [1995-05]
)), But here, a high-speed SDRAM (Syncronus Dynamic
SSTL (St) used in Randam Access Memory
ub Series TerminationLogic interface (Japan Electronic Machinery Manufacturers Association standard: 3.3V stub series termination type logic (S
STL_3) Standard function specifications, Japan Electronic Machinery Manufacturers Association EIAJ ED-5
A description will be given taking a main memory bus of a computer using 512 (1996)) as an example.

FIG. 2 shows a main memory bus configuration of a computer using the SSTL interface according to the prior art. This configuration is based on Nikkei Electronics (input / output interface for 100MHz era-DRAM module is SSTL
, Nikkei Electronics No. 641 pp. 123, Nikkei BP (1995)). The memory controller LSI 1 and the memory module 2 are connected to a memory bus line 3 via a series resistor 3. Termination voltages 7 and 8 are connected to both ends of the memory bus wiring 3 via termination resistors 5 and 6, respectively. In this example, the terminating resistor 5
Is implemented near the memory controller LSI1 or
Alternatively, it must be built in an LSI.

Next, the operating frequency of the bus will be considered. Memory module number Nmm = 8, memory controller LSI
Assuming that the memory module and the memory module have standard specifications as an operation frequency of 100 MHz (megahertz), a signal output timing width to = 3.5 ns (nanosecond), a setup time ts = 2.5 ns, and a hold time th = 1. 5n
s, propagation delay time td0 per memory module
= 0.5 ns, signal propagation delay time difference Δtd = (Nm
m-1) .times.td0 = 7.times.0.4 = 2.8 ns, the condition under which the bus can operate is the logic level determination width tpw of the signal.
> Ts + th + to + Δtd = 10.3 ns. In this example, a bus operating frequency f = 70 MHz is realized.

[0009]

However, the memory controller LSI is generally an LSI having a large number of terminals because it is connected to both the CPU and the main memory. Therefore, it is often composed of a plurality of LSIs. If a new terminal for connecting a terminating resistor is newly provided for an LSI with a large number of terminals,
Expensive mounting technology is required. Furthermore, when a computer having a plurality of CPUs is realized, the number of terminals of the memory controller LSI further increases, so that more expensive mounting technology is required. In addition, it is considered that the incorporation of the terminating resistor requires an expensive process for manufacturing the memory controller LSI.

As shown in the conventional example, the operating frequency of the memory bus is lower than the operating frequency of the memory controller LSI or the memory module alone. In the conventional example, the operating frequency of the memory bus is 70 MHz, and the operating frequency of the memory controller LSI and the memory module is 100 MHz. Therefore, the operating frequency is reduced by 30% by using the bus wiring.

An object of the present invention is to provide a memory controller LS
To provide a bus wiring device that does not require a terminating resistor near I and further reduces the operating frequency due to the use of bus wiring, thereby realizing high-speed electronic circuit devices and low cost electronic circuit devices. It is in.

[0012]

According to the present invention, in a bus wiring device, a terminating voltage is connected via a terminating resistor to both ends of a bus line connecting a plurality of memory modules, and a memory controller LSI is connected to a center of the bus line. Is provided, and a series resistor for anti-reflection is provided near the branch,
By configuring the connection from the branch to the memory controller LSI with non-terminal wiring, the memory controller L
The present invention provides a bus wiring device that does not require a terminating resistor near the SI, reduces the number of memory modules through which signals pass, reduces the difference in signal propagation delay time, and operates at a higher frequency by using bus wiring. Can be reduced. As a result, an increase in the speed of the electronic circuit device and a reduction in the cost of the electronic circuit device are realized.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the technology according to the present invention will be described in detail using embodiments.

FIG. 1 shows a bus wiring device according to a first embodiment of the present invention. The memory module 2 is connected to the memory bus wiring 3 via the series resistor 4. Both ends of the memory bus wiring 3 are connected to terminating voltages 7 and 8 via terminating resistors 5 and 6, respectively. Memory controller LSI at the center of bus wiring
1 is provided, and a memory controller LSI is connected near the branch via a series resistor 4 for preventing reflection. These components are separated on the main board 9 and the memory module stack board 10. The memory controller LSI 1 and the wiring 11 for connecting the memory controller LSI are mounted on the main board 9, and the other components are mounted on the memory module stack board 10.

In this example, the terminating resistors 5 and 6 do not need to be mounted near the memory controller LSI1 and need not be built in the LSI. Terminating resistors 5 and 6 are
It is mounted on the memory module stack board 10.

Next, the bus operating frequency when the main memory bus of the same computer as the conventional example is used as the bus wiring according to the present invention is determined. That is, assuming that the number of memory modules is Nmm = 8, the memory controller LSI and the memory modules are assumed to have standard operating specifications of 100 MHz operating frequency, the signal output timing width to = 3.5 ns, the setup time ts = 2.5 ns, and the hold. Time th = 1.
5 ns, propagation delay time t per memory module
d0 = 0.5 ns, signal propagation delay time difference Δtd =
((Nmm−2) / 2) × td0 = 3 × 0.4 = 1.2n
Assuming that s, the condition under which the bus can operate is as follows: the logic level decision width of the signal tpw> ts + th + to + Δtd = 8.7n
It can operate at a frequency satisfying s. In this example, a bus operating frequency f = 78 MHz is realized. In the conventional example, the operating frequency is reduced by 30% by using the bus wiring. However, the operating frequency of the memory bus is 78 MHz, and the operating frequency of the memory controller LSI and the memory module is 100 MHz. The reduction of the operating frequency due to this can be suppressed to 22%.

FIG. 3 shows a bus wiring device according to a second embodiment of the present invention. The memory modules 2 and 2 ′ are connected with series resistors 4 and 4 ′.
Are connected to the memory bus lines 3 and 3 '.
Both ends of the memory bus wirings 3, 3 'are connected to the terminating resistors 5, 5',
The terminal voltages 7, 7 ', 8, 8' are connected via 6, 6 '. Memory controller LSI1 at the approximate center of bus wiring
Are provided, anti-reflection series resistors 4 and 4 'are connected near the branch, and a branch wiring 13 is provided from the branch wiring 12, and the anti-reflection series resistor 11 is provided near the branch. And a memory controller LSI.
These components are separated on the main board 9 and the memory module stack board 10. The memory controller LSI 1 and the wiring 11 for connecting the memory controller LSI are mounted on the main board 9, and the other components are mounted on the memory module stack board 10.

Also in this example, the terminating resistors 5, 5 ', 6, 6'
Need not be mounted near the memory controller LSI1 and need not be built in the LSI. The terminating resistors 5, 5 ', 6, 6' are mounted on the memory module stack board 10.

Next, the bus operating frequency when the main memory bus of the same computer as the conventional example is used as the bus wiring according to the present invention is determined. That is, assuming that the number of memory modules is Nmm = 8, the memory controller LSI and the memory modules are assumed to have standard operating specifications of 100 MHz operating frequency, the signal output timing width to = 3.5 ns, the setup time ts = 2.5 ns, and the hold. Time th = 1.
5 ns, propagation delay time t per memory module
d0 = 0.5 ns, signal propagation delay time difference Δtd =
((Nmm−4) / 4) × td0 = 1 × 0.4 = 0.4n
Assuming that s, the condition under which the bus can operate is as follows: the logic level decision width of the signal tpw> ts + th + to + Δtd = 7.9n
It can operate at a frequency satisfying s. In this example, a bus operating frequency f = 84 MHz is realized. In the conventional example, the operating frequency is reduced by 30% by using the bus wiring. However, the operating frequency of the memory bus is 84 MHz, and the operating frequencies of the memory controller LSI and the memory module are 100 MHz. The reduction of the operating frequency due to the above can be suppressed to 12%.

[0020]

According to the present invention, the terminating resistor does not need to be mounted near the memory controller LSI.
There is no need to build it into The operating frequency of the memory bus is increased from 70 MHz to 84 MHz, and the operating frequency is reduced by 30% to 12% due to the use of the bus wiring.
It is possible to reduce the maximum to 40% compared with the conventional bus wiring device.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a bus wiring according to a first embodiment of the present invention.

FIG. 2 is an explanatory diagram of a bus wiring according to the related art.

FIG. 3 is an explanatory diagram of a bus wiring according to a second embodiment of the present invention.

[Explanation of symbols]

1 ... Memory controller LSI, 2,2 '... Memory module, 3,3' ... Memory bus wiring, 4,4 '... Series resistance, 5,5', 6,6 '... Terminal resistance, 7,7', 8 ,
8 ': termination voltage, 9: main board, 10: memory module stack board, 11: memory controller LS
Wiring for I connection.

Claims (2)

[Claims] In a bus wiring device having a terminating means for driving a plurality of receivers with one driver, the plurality of receivers are connected by bus lines terminated at both ends, and a driver connection is provided at a substantially center of the bus lines. A bus wiring device, wherein a branch from the driver connection to the driver is connected by non-terminal wiring. 2. The bus according to claim 1, further comprising two or more pairs of bus wirings each of which terminates the plurality of receivers at both ends, providing a branch at a substantially center of the bus wiring, and interconnecting the branches.
A bus wiring device, wherein a branch for driver connection is provided at the approximate center of the mutual wiring, and a non-terminal wiring is connected from the branch for driver connection to the driver.