JPH10301256A - Mask for exposure and production of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it possible to form exposure patterns of nearly the same shape as the shape of mask patterns on a photoresist at the time of forming element forming regions by forming auxiliary light shielding regions having the width below the threshold resolution of an exposure system on the outer side of light shielding regions and in proximity to the light shielding regions. SOLUTION: The L-shaped auxiliary light shielding regions γ are so formed as to be adjacent to the four corners on the outer side of the four corners of the light shielding region α enclosed by a light transmissive region β. The width of the respective auxiliary light shielding regions γ is set at the value below the threshold resolution of the exposure system. The spacing between the respective auxiliary light shielding regions γ and the light shielding region α is similarly set at the value below the threshold resolution of the exposure system. The width of the auxiliary light shielding regions γis set at the value below the threshold resolution of the exposure system determined inclusive of the characteristics of the resist and the characteristics of a developer, etc., in such a manner and, therefore, the positive type photoresist right under the respective auxiliary light shielding regions γ are not sufficiently shielded of light and are exposed to some extent. These photoresists are melted and removed by a subsequent etching treatment.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an exposure mask for an exposure system used in a semiconductor integrated circuit manufacturing process, and more particularly to an exposure mask capable of forming a highly accurate exposure pattern on a photoresist. The present invention relates to an improvement and a method for manufacturing a semiconductor device using the exposure mask.

[0002]

2. Description of the Related Art In recent years, semiconductor elements have been steadily miniaturized.
The size of the element forming region surrounded by the element isolation region constituting the MOS transistor has been decreasing year by year similarly to the width of the gate electrode. These element formation regions and gates
The positive electrode and the g-line (λ = 436 nm
), A resist pattern using a reduction projection exposure apparatus (commonly called a stepper) using short-wavelength light such as i-line (λ = 365 nm).
The pattern is formed by etching the lower insulating film and the conductive film using the resist pattern as an etching mask.

There are many element isolation methods such as a LOCOS method, a field shield element isolation method, a trench isolation method, and a BOX element isolation method. A rectangular element formation region separated by a field oxide film by the LOCOS method. Is formed, and a MOS transistor is formed in this element formation region. In this case, first, using a positive resist, a reticle having a pattern as shown in FIG. 7 is used to set a field oxidation region that is not covered with an oxidation-resistant insulating film such as a silicon nitride film. You.

In this reticle, a rectangular light-shielding region that defines the shape of an element formation region to be formed is formed in the center portion, and a light-transmitting region is formed outside the light-shielding region. By using this reticle as an original, an unexposed positive resist mask is left only on the surface of the semiconductor substrate immediately below the light-shielding region, as shown in the cross-sectional view of FIG. 8, and the remaining resist mask is used. By performing the etching, a rectangular oxidation-resistant silicon nitride film is left just under the etching. By performing field oxidation using the remaining rectangular silicon nitride film as an oxidation-resistant mask, as shown in FIG. 9, the light-shielding region is formed only on the surface of the semiconductor substrate immediately below the light-shielding region of the reticle in FIG. A field oxide surface having a rectangular opening (element formation region) similar to the above is formed on the surface of the silicon substrate.

[0005]

However, the shape of the element formation region actually formed is not rectangular but is shown in FIG.
As shown in the example, the four corners have an elliptical shape curved in an arc shape. The reason will be described with reference to FIGS. Each line segment aa ', bb', c in FIG.
Considering the intensity distribution of transmitted light into the resist along −c ′, as shown in FIG.
It has a slope. Then, the closer to the four corners, the greater the combined light amount from both the X and Y directions, as shown as an example of the intensity distribution of the transmitted light along dd ′ in FIG. . As a result, as illustrated in FIG. 13, an arc shape gently curved about four corners is obtained.

After forming the field oxide film, as shown in the cross-sectional view of FIG. 14, an oxide film for forming a gate oxide film is formed on the entire surface of the silicon substrate, and then a gate electrode is formed. A conductive layer such as polysilicon or WSi (tungsten silicide). After a photoresist is formed on this conductor layer, exposure is performed using a photomask in which only the gate electrode formation region is a light-shielding region, leaving only the strip-shaped photoresist directly above the gate electrode formation region. By performing etching using the photoresist as a mask, a strip-shaped gate electrode and a gate oxide film layer immediately below the gate electrode are formed.

However, as described above, when performing exposure using a photomask in which only the formation region of the gate electrode is a light-shielding region, as shown in FIG. 14, the exposure is performed on the inclined surface of the field oxide film. Exposure light is reflected on the inclined surface of the conductor layer having a high reflectance, and is incident on a photomask for forming a gate electrode. Further, as is apparent from the plan view of FIG. 13, the inclined surface of the conductor layer is concavely curved on both the left and right sides and the four corners. Light concentrates on the central portion of the gate formation region.

For this reason, of the positive type photoresist covering the gate forming region immediately below the light-shielding region, the central portions on the left and right sides of the gate forming region are exposed, and as a result,
A gate electrode having a narrow central portion is formed. The tapered gate electrode causes a problem that the element characteristics such as the (threshold voltage) and the breakdown voltage of the MOS transistor are deteriorated.

Accordingly, an object of the present invention is to form an exposure pattern having substantially the same shape as a mask pattern when forming an element formation region in order to prevent the gate electrode from being thinned due to reflected light generated in a subsequent step as described above. An object of the present invention is to provide a high-performance exposure mask that can be formed on a photoresist and a method for manufacturing a high-performance semiconductor device using the exposure mask.

[0010]

An exposure mask according to the present invention for solving the above-mentioned problems of the prior art is an exposure mask of an exposure system for selectively exposing a photoresist, and includes a part of a light shielding area or An auxiliary light-shielding area having a width equal to or less than the limit resolution of the exposure system is formed outside the whole and close to the light-shielding area.

[0011]

According to a preferred embodiment of the present invention, the auxiliary light-shielding region is formed at a distance from the outer edge of the light-shielding region that is equal to or less than the limit resolution of the exposure system. According to another preferred embodiment of the present invention, the light shielding region has a rectangular shape, and the auxiliary light shielding region has an L shape. According to a further preferred embodiment of the present invention, the light-shielding region is a light-shielding region for forming an element formation region of a semiconductor integrated circuit in which element isolation is performed using the LOCOS method.

[0012]

FIG. 1 is a plan view showing a reticle according to an embodiment of the present invention. Outside the four corners of the light-shielding region α surrounded by the light-transmitting region β, an L-shaped auxiliary light-shielding region γ is formed adjacent to the four corners. The width of each auxiliary light shielding area γ is set to a value equal to or less than the limit resolution of the exposure system. Similarly, the interval between each of the auxiliary light-shielding regions γ and the light-shielding region α is set to a value equal to or less than the limit resolution of the exposure system.

Referring to FIG. 2, the spatial distribution of the exposure amount on the line AA 'which does not pass through the auxiliary light shielding area γ is as shown in FIG. The spatial distribution of FIG. 3 is the same as that illustrated in FIG. 11 in connection with the description of the conventional technique. On the other hand, the spatial distribution of the exposure amount viewed in a single direction on the line segment BB'CC'DD 'in FIG. In addition, it becomes steeper than that illustrated in FIG. And the line segment BB'C-
As illustrated in FIG. 5, the spatial distribution of the exposure amount by combining from all directions such as the X and Y directions on C′DD ′ is steeper than that illustrated in FIG. The wraparound of the exposure light beam downward is greatly suppressed.

As described above, the width of the auxiliary light-shielding region is set to a value equal to or less than the limit resolution of the exposure system determined including the characteristics of the resist and the characteristics of the developing solution.
For this reason, the positive photoresist immediately below each L-shaped auxiliary light-shielding region is not sufficiently shielded from light and is exposed to some extent,
It is melted away by a subsequent etching process. That is, the L at the four corners of the target rectangular photoresist
No letter-shaped photoresist is formed.

Further, as described above, the distance between the four corners of the rectangular light-shielding region and the L-shaped auxiliary light-shielding region immediately outside each of the four corners is equal to or less than the above-described limit resolution of this exposure system. Therefore, the amount of exposure light incident on the L-shaped light-transmitting region δ formed therebetween is significantly reduced as compared with a conventional mask having no auxiliary light-shielding region. As a result, the amount of exposure that goes immediately below the light-shielding region α through the four corners of the rectangular light-shielding region α is greatly reduced, and a rectangular unexposed region having sharpened four corners is formed in the photoresist.

FIG. 6 shows the shapes and dimensions of the auxiliary light shielding regions γ formed at the four corners of the light shielding region α. As an example, X1 = Y2 and X2 = Y2 are set. Also, X
Each of 1, X2, Y1, and Y2 is set to a value equal to or less than the limit resolution of the exposure system.

As an example, i-line (λ = 365 n
m), and assuming that a reduced projection exposure apparatus with NA = 0.55 is used, such an exposure apparatus, a resist,
The critical resolution that can be obtained in consideration of various conditions such as the developer is 0.
55 μm. In this case, X1 = X2 = Y1 = Y2 = 0.
By using a reticle set to 3 μm, a rectangular unexposed area having sharp four corners can be formed in the photoresist.

As a result, as described with reference to FIGS. 7 to 14, when a MOS transistor is formed in an element formation region surrounded by a field oxide film, the central portion of the gate electrode may be narrowed. A problem-free MOS transistor having good characteristics can be manufactured.

The case where the distance between the light-shielding region α and the auxiliary light-shielding region γ, that is, the width of the narrow light-transmitting region δ formed therebetween is set to a value equal to or less than the limit resolution of this exposure system has been exemplified. . However, for the purpose of the present invention, it is only necessary to reduce the amount of exposure light rays incident on the light-transmitting region δ. Therefore, the width of the light-transmitting region δ is set to a value slightly larger than the limit resolution of the exposure system. Can also. Also, when the four corners of the rectangular unexposed area of the photoresist can be allowed to be slightly rounded, the width of the light transmitting area δ should be set to a value slightly larger than the limit resolution of the exposure system. Can be.

Further, the configuration in which the shape of the auxiliary light-shielding region is L-shaped has been exemplified, but the shape of the auxiliary light-shielding region may be any other appropriate shape such as a combination of two rectangles.

Furthermore, the configuration in which the auxiliary light-shielding regions are formed only at the four corners of the rectangular light-shielding region has been exemplified.
It can also be formed continuously outside the entire circumference.

Although the case where a positive resist is used as the photoresist has been described as an example, it goes without saying that the present invention can be similarly applied to the case where a negative resist is used.

Further, the exposure mask of the present invention has been described by taking, as an example, a case where a problem in forming a MOS transistor in a region where elements are separated by the LOCOS method is solved. However, the exposure mask of the present invention can be applied to a method of manufacturing a product having a fine structure, such as any semiconductor integrated circuit, which requires the manufacture of a photoresist having an accurate shape with sharp corners.

Further, the present invention has been described by taking as an example the case where a light beam is used for exposure, but in addition to the light beam, an electron beam, an X-ray,
An ion beam or the like can also be used.

[0025]

As described in detail above, the exposure mask of the present invention has a structure in which an auxiliary light-shielding region having a width smaller than the limit resolution of this exposure system is formed outside the four corners of the light-shielding region. The amount of exposure incident on the light-transmitting regions at the four corners surrounded by the two light-shielding regions at the four corners decreases, and accordingly, the amount of exposure that goes directly below the light-shielding region through the light-transmitting regions decreases. As a result, it is possible to form photoresists at four sharp corners, and effectively solve problems such as thinning of a gate electrode when a MOS transistor is formed in an element formation region separated by a field oxide film.

[Brief description of the drawings]

FIG. 1 is a plan view showing an example of an exposure mask according to one embodiment of the present invention.

FIG. 2 is a conceptual diagram for explaining a state of a spatial distribution of an exposure amount immediately below an exposure mask of the embodiment.

FIG. 3 is a conceptual diagram for explaining a state of a spatial distribution of an exposure amount immediately below an exposure mask of the embodiment.

FIG. 4 is a conceptual diagram for explaining a state of a spatial distribution of an exposure amount immediately below an exposure mask of the embodiment.

FIG. 5 is a conceptual diagram for explaining a state of a spatial distribution of an exposure amount immediately below an exposure mask of the embodiment.

FIG. 6 is a partial plan view for explaining the shape and size of an auxiliary light-shielding region and the distance between the auxiliary light-shielding region and the light-shielding region in the exposure mask of the embodiment.

FIG. 7 is a plan view showing an example of a conventional exposure mask.

8 is a cross-sectional view illustrating a shape of a photoresist formed using the exposure mask of FIG.

9 is a cross-sectional view showing the structure of a silicon nitride film formed by using the photoresist of FIG. 8 and a field oxide film formed by using the silicon nitride film.

FIG. 10 is a conceptual diagram for explaining a state of a spatial distribution of an exposure amount immediately below the conventional exposure mask.

FIG. 11 is a conceptual diagram for explaining a state of a spatial distribution of an exposure amount immediately below the conventional exposure mask.

FIG. 12 is a conceptual diagram for explaining a state of a spatial distribution of an exposure amount immediately below the conventional exposure mask.

13A and 13B, an element formation region surrounded by a field oxide film is formed using the above-described conventional exposure mask, and an MO is formed in this region.
FIG. 4 is a plan view for describing a problem when forming a gate electrode of an S transistor.

[0024] FIG. 14 illustrates a case where an element formation region surrounded by a field oxide film is formed using the above-described conventional exposure mask, and an MO is formed in this region.
FIG. 4 is a cross-sectional view for describing a problem when forming a gate electrode of an S transistor.

[Explanation of symbols]

α light-shielding area β light-transmitting area γ auxiliary light-shielding area δ light-transmitting area surrounded by the light-shielding area and the auxiliary light-shielding area

Claims (6)

[Claims] An exposure mask for an exposure system for selectively exposing a photoresist, wherein the width of the exposure mask is less than or equal to a limit resolution of the exposure system, outside a part or all of the light-shielding area and in close proximity to the light-shielding area. An exposure mask, wherein an auxiliary light-shielding region having: 2. The exposure mask according to claim 1, wherein the auxiliary light-shielding region is formed at a distance from an outer edge of the light-shielding region that is equal to or less than a limit resolution of the exposure system. 3. The exposure mask according to claim 1, wherein the auxiliary light-shielding region is formed only at a corner of the light-shielding region. 4. The light-shielding region according to claim 1, wherein the light-shielding region has a rectangular shape, the auxiliary light-shielding region has an L-shape, and the L-shaped auxiliary light-shielding region is provided only at four corners of the light-shielding region. An exposure mask, which is formed. 5. A field oxide film is formed by forming a rectangular oxidation-resistant insulating film on a silicon substrate using a photolithography technique and performing field oxidation using the oxidation-resistant insulating film as an oxidation-resistant mask. In a method of manufacturing a semiconductor device in which an enclosed rectangular element formation region is formed and a MOS transistor is formed in the element formation region, an exposure mask used in the photolithography method may be used to define the element formation region. A method for manufacturing a semiconductor device, wherein an auxiliary light-shielding region having a width equal to or less than a limit resolution of the exposure system is formed outside the rectangular light-shielding region including at least four corners. 6. The method according to claim 5, wherein the auxiliary light-shielding region is formed at a distance from an outer edge of the light-shielding region that is equal to or less than a limit resolution of the exposure system.