JPH07106227A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To facilitate the arrangement design of the patterns of a phase-shifting mask, which is used in a matching exposure using a step-and-repeater, and to shorten a mask-making period. CONSTITUTION:In a process of performing a multiple exposure, phase shifter parts 111 of a necessary fine line width and a light-shielding part 101 are previously held arranged in a first photomask and in a second photomask, first light-shielding parts 102a are respectively arranged at the positions of desired fine patterns formed by the fist photomask, whereby the desire fine patterns formed by the first photomask are selectively exposed. Moreover, the selected desired fine patterns formed by the first photomask are connected to each other by end edge patterns, which are formed at second light-shielding parts 102b of the second photomask.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a resist pattern.

[0002]

2. Description of the Related Art Recently, in a method of manufacturing a semiconductor device,
In particular, there is a strong demand for miniaturization of the resist pattern dimension line width by the lithography technique. As a method of improving this miniaturization and the reduction of the process margin accompanying this,
In particular, in order to miniaturize the resist pattern dimension line width in the step-and-repeater, a method of forming a resist pattern using a phase shift mask is being studied.

As a method of forming a resist pattern using this conventional phase shift mask, a GaAs Schottky barrier gate type field effect transistor (hereinafter referred to as GaAs M
A method of forming a gate electrode pattern of an amplifying element in a microwave and millimeter wave band of an ESFET) is disclosed in Japanese Patent Laid-Open No. 4-33.
No. 7732.

The gate electrode pattern forming method described in this document will be described below with reference to the drawings.

18 to 20 are plan views showing a plane pattern in a conventional gate electrode pattern forming method, and FIG. 18 is a plan view showing a photomask.
19 and 20 are plan views showing a plane pattern on a semiconductor substrate. Further, FIG. 21 is a plan view showing a normal photomask (all light shielding parts are made of a Cr layer) for forming the gate electrode patterns shown in FIGS. In the following description, the fine pattern of the plane pattern becomes the gate finger portion 141 in the gate electrode pattern as shown in FIG. 20, and the portion (edge pattern) connecting the fine patterns is the gate pad portion. 142. Further, a gate finger end portion 143 is formed on the side opposite to the gate pad portion 142.

The phase shift mask disclosed in Japanese Unexamined Patent Publication No. 4-337732 is called an edge transmissive type, and is used in the case of forming an isolated fine line width in the gate finger portion 141 as shown in FIG. The phase shift exposure method is suitable for. This mask has a phase shifter layer (having a phase angle of 180 ° with respect to the exposure wavelength) at a portion corresponding to the gate finger portion 141 of a normal photomask (FIG. 21).
The phase shifter 111 shown in FIG. 18 is formed by performing the first exposure by the step-and-repeater using the first photomask (FIG. 18) in which the phase shifter 111 part is formed with the film thickness such that the phase shifter 111 of FIG. The first unexposed portion 122a is formed at the contour position of the portion (FIG. 19). This unexposed portion 122a becomes a resist opening pattern having an opening line width of about 0.2 μm when a negative resist is used.

At this time, in the first unexposed portion 122a shown in FIG. 19, a pattern (called an unnecessary line) 122b not shown in the ordinary photomask shown in FIG. 21 is generated. In the method disclosed in Japanese Patent Laid-Open No. 4-337732, in order to expose only this unnecessary line, the first
Second exposure, and then the second light shielding unit 102 shown in FIG.
The second exposure is performed using the second photomask having the second photomask, and as shown in FIG. 20, a plane pattern having the third unexposed portion 123 at the same position as the unexposed portion 121 formed by the first and second exposures. Is getting This plane pattern has the same shape as that of an ordinary photomask (FIG. 21).

[0008]

In the prior art method of forming a resist pattern using a phase shift mask, it is practical to simply arrange the phase shifter formed on the photomask and erase the unnecessary lines generated. It has become an issue to be realized.

In the prior art method using multiple exposure described in the above-mentioned Japanese Patent Laid-Open No. 4-337732,
It is necessary to create a first photomask having the individual phase shifter portions 111 arranged corresponding to the gate finger portions 141 of FIG. 20 and a second photomask having the second light shielding portion 102, respectively. Is complicated to create.

Further, in the first photomask and the second photomask disclosed in Japanese Patent Laid-Open No. 4-337732, it is necessary to create a pattern for each product having a different pattern shape. This not only complicates the pattern formation of the photomask, but also requires that the first photomask, the phase shift mask, be prepared for each product. , The manufacturing time is longer than that of a normal photomask, and the period for manufacturing the photomask is increased. There is also a problem.

An object of the present invention is to provide a method of manufacturing a semiconductor device which facilitates pattern layout design in a phase shift mask and shortens the mask making period.

[0012]

To achieve the above object, a method of manufacturing a semiconductor device according to the present invention comprises a fine pattern forming step and a fine pattern selecting step, and a fine pattern having a fine line width and a wide pattern. A method of manufacturing a semiconductor device, comprising: forming a plane pattern, which is a combination of a plurality of edge patterns, on a resist of a substrate by multiple exposure, comprising a first photomask for multiple exposure and a second photomask. The first photomask is used in the fine pattern forming step, and has a phase shifter section and a light shielding section,
The phase shifter portion shapes the exposure light into a shape of a fine pattern having a fine line width formed on the resist, and a plurality of phase shifter portions are arranged in parallel corresponding to the pitch of the fine pattern to be formed. Is formed into a shape of an unexposed region having an area to be secured on at least one side of the fine pattern on the resist, and is arranged so as to be connected to the phase shifter portion. The second light-shielding portion is used in the selection step, has two light-shielding portions, and the first light-shielding portion is shaped to cover the fine pattern of the plane pattern to shield light. Is shaped according to the shape of the edge pattern of the plane pattern. In the fine pattern forming step, the resist of the substrate is irradiated with the exposure light through the first photomask, Is a step of forming a plurality of fine patterns having a fine line width in parallel on the strike and securing an unexposed region connected to the fine patterns. The fine pattern selecting step is performed on the resist of the substrate that has undergone the fine pattern forming step. Of the specific fine pattern to be used with the first light-shielding portion of the second photomask, and a part of the unexposed region secured on the resist of the substrate is covered with the second photomask of the second photomask. This is a step of performing exposure by covering with a light-shielding portion, leaving the region shielded by the second photomask as the plane pattern, and erasing the resist pattern in the other regions.

The phase shifter portion of the first photomask includes an edge transmission type structure which forms a fine pattern having a fine line width at the contour position.

Further, the phase shifter portions of the first photomask are made to have different lengths, and the phase shifter portions are used to form fine patterns having different fine line widths on the resist of the substrate. .

[0015]

It is noted that fine patterns having a fine line width are regularly arranged regardless of the type of product, and the fine pattern is formed by the first photomask in a required number or more to obtain the first pattern. We are trying to standardize photomasks.

On the other hand, the second photomask is patterned according to the pattern of the product, and the second photomask is used to shape the exposure pattern of the first photomask into the required pattern. As a result, when the product pattern is changed, only the second photomask is changed.

[0017]

EXAMPLE Next, an example of the present invention will be described. GaAs ME
The gate electrode pattern formation of the SFET will be described as an example with reference to the drawings.

(Embodiment 1) FIG. 1 is a plan view showing a photomask in a gate electrode forming method in Embodiment 1 of the present invention, and FIGS. 2 and 3 are plan views showing a resist pattern of a semiconductor substrate. . Also, FIGS. 4 and 5 are sectional views taken along the line AA ′ of FIG. 1 for explaining the gate electrode pattern forming step.
It is a line sectional view.

In the following description of each embodiment, the fine pattern is the gate finger portion 141 in the gate electrode pattern, and the edge pattern connecting the fine pattern is the gate pad portion 142. Further, the dimensions of the plane pattern in the present invention are all described with values on the semiconductor substrate (when the reduction ratio is 5 times, the dimension on each photomask is 5 times the value of each description).

The method of manufacturing a semiconductor device according to the present invention includes a fine pattern forming step and a fine pattern selecting step, and a fine pattern having a fine line width (gate finger portion 141) and a wide pattern as shown in FIG. A plane pattern composed of a combination with the edge pattern (gate pad portion 142) is formed on the resist of the substrate by multiple exposure.

As shown in FIG. 1, the present invention is provided with a first photomask for multi-exposure (shaded portion by solid line) and a second photomask (shaded portion by broken line).

The first photomask is used in a fine pattern forming step and has a phase shifter portion 111 and a light shielding portion 101, and the phase shifter portion 111 includes
The exposure light is shaped into a shape of a fine pattern 141 having a fine line width, and a plurality of light rays are arranged in parallel corresponding to the pitch of the fine pattern 141 to be formed.
Is shaped into an unexposed region having an area to be secured on at least one side of the fine pattern on the resist and is arranged so as to be connected to the phase shifter portion 111.

The second photomask, which is used in the fine pattern selection step, has two light-shielding portions, and the first light-shielding portion 102a covers the fine pattern 141 of the plane pattern. The second light shielding portion 102b is shaped so as to shield light, and is shaped according to the shape of the edge pattern 142 of the plane pattern.

In the step of forming a fine pattern, the resist of the substrate is irradiated with exposure light through the first photomask to form a plurality of fine patterns having a fine line width in parallel on the resist of the substrate, and the fine pattern is formed. This is a step of securing the connected unexposed area. The fine pattern selection process is
A specific fine pattern to be used on the resist of the substrate that has undergone the fine pattern formation process is covered with the first light-shielding portion of the second photomask, and a part of the unexposed region secured on the resist of the substrate. Is covered with the second light-shielding portion of the second photomask for exposure, the region shielded by the second photomask is left as the plane pattern, and the resist pattern in the other regions is erased.

Further, the phase shifter portion 111 of the first photomask has an edge transmission type structure for forming a fine pattern having a fine line width at the contour position thereof.

In the step of forming a gate electrode pattern in this embodiment, first, an operating layer (not shown) and a contact layer (not shown) are grown on a GaAs substrate by a molecular beam epitaxial method, and an alignment mark for a step and repeater is grown. (Not shown) is formed, and the contact layer is further selectively etched by wet etching to a width of 1.3 μm and a depth of about 100 nm.
A dielectric film 2 (SiO ₂ film of about 500 nm by LP-CVD method) is deposited on top, and a photoresist film 3 (chemically amplified i-line negative resist; THMR-iN100 (film thickness of about 500 nm), Tokyo Ohka Company) is formed by an ordinary spin coating method (FIG. 4A).

Next, a step-and-repeater (i-line (wavelength 365 nm) stepper; NSR-) using an alignment couque is used by using a first photomask having a light-shielding portion 101 and a phase shifter portion 111 called an edge transmission type. 1
775i7A, Nikon Corporation).

The plane pattern formed by the first exposure using this first photomask is the solid line portion of FIG. 2 and its cross section is FIG. 4B, and the unexposed region 121a by the light shielding portion 101 is shown. Then, an unexposed portion (corresponding to a fine pattern) 121a having a different length by the phase shifter portion 111 is formed on the photoresist film 3.

Next, using a second photomask having two light shielding portions 102a and 102b, a step and repeater (i-line (wavelength 365n
m) Stepper; NSR-1775i7A, Nikon Corporation)
Second exposure is performed.

The plane pattern formed by the second exposure using the second photomask is the broken line portion of FIG. 2, and the unexposed portion covered with the first light shielding portion 102a as shown in FIG. (Fine pattern to be used) 121b and the second
Unexposed part (edge pattern) covered with the light shielding part 102b of
122a remains unexposed, and the other patterns are exposed by exposure light to be exposed, and the plane pattern has a shape of a portion where a shaded portion by a solid line and a shaded portion by a broken line in FIG. It will be formed on the photoresist film 3 in the shape shown in FIG.

The unexposed portion 12 after the second exposure is performed.
3 denotes the first unexposed portions 121a, 121 due to the first exposure.
1b and the second unexposed portions 122, 122 due to the second exposure
It becomes a part where a and 122b overlap. Therefore, the unexposed portion 123 (FIG. 4C) in the photoresist film 3 has a plane pattern as shown in FIG.

Next, a post-exposure bake called PEB is carried out, and an ordinary alkaline developer (NMD-3 (concentration 2.38) is used.
%), Developed by Tokyo Ohka Co., Ltd. (about 60 seconds),
A resist opening 131 is formed in a part of the unexposed portion 123 (FIG. 4D). In this embodiment, the unexposed portion 123 becomes the resist opening portion 131 by using a (chemical amplification type) negative resist for the photoresist film 3.

Further, using the photoresist film 3 as a mask, the portion of the dielectric film 2 exposed under the opening is selectively removed by etching to remove the photoresist film 3 (FIG. 5 (e)). A dielectric film 4 is deposited on the entire surface of the semiconductor substrate 1 from above (FIG. 5F), a photoresist pattern is formed by a normal photolithography technique (not shown), and the dielectric film 4 is used as a mask. The photoresist film is selectively removed, and the dielectric film 2 is removed.
Are removed to form a desired gate electrode pattern (see FIG. 5).
(G)).

In the pattern arrangement of this embodiment described above, the distance between the gate finger portions 141 shown in FIG. 3 is 20 μm.
The phase shifter portions 111 of the first photomask shown in FIG. 1 are also periodically arranged at intervals of 20 μm (each phase shifter portion is arranged at a width of 5 μm and an interval of 5 μm). . In this embodiment, the edge transmission type phase shift method using the first photomask is used.
Since the unexposed portion 121b is formed in the contour portion of the phase shifter portion 111 by the exposure of, the gate finger portion 141
The fine line width pattern of the unexposed portion 121b (FIG. 2) formed as is at 5 μm intervals (the line width of this fine dimension pattern is about 0.2 μm in terms of the resist opening dimension).

Further, the light shielding portion 1 that covers the gate finger portion 141 of the second photomask used during the second exposure.
02a has a width of about 2 μm and is arranged at intervals of 20 μm (FIG. 1). Therefore, the unexposed portion of the gate finger portion 141 is arranged such that the fine line width pattern of the first unexposed portion 121b shown in FIG. 2 is selected every 20 μm cycle (FIG. 3).

Further, the gate pad portion 142 shown in FIG.
An area corresponding to the gate finger end portion 143 is the light shielding portion 101 of the first photomask used in the first exposure.
And the light-shielding portions 102a and 102b formed on the second photomask used during the second exposure.

With the above pattern arrangement, a desired fine line width pattern as the gate finger portion 141 formed by the first photomask can be selectively exposed by the second photomask. Further, the selected fine line width pattern can be connected by the gate pad portion 142 at the time of exposure by the second photomask.

(Embodiment 2) Next, with respect to Embodiment 2 of the present invention, referring to the drawings, a method of forming a plane pattern shape different from that of Embodiment 1 using the first photomask used in Embodiment 1 will be described. And explain. FIG. 6 is a plan view of a photomask in the gate electrode forming method according to the second embodiment of the present invention, and FIGS. 7 and 8 are plan views of a semiconductor substrate. The steps of forming the gate electrode in Example 2 are the same as those in Example 1.

In the first photomask used in the first embodiment (FIG. 1), the phase shifter portions 111 forming the gate finger portions 141 have a width of 5 μm and an interval of 5 μm and different lengths (eg, Effective length of 150 μm and 7
5 μm), two types are periodically arranged for 20 μm, and in the first embodiment, an example in which the phase shifter unit 111 of 150 μm is selectively exposed is shown, but in the second embodiment, a pattern of 75 μm is selectively exposed.

In order to selectively expose this 75 μm pattern using the present invention, the unexposed portions 122a, 122 of FIG.
2b may be moved to the right by two fine line width patterns (10 μm) relative to the unexposed areas 121a and 121b, and exposed as shown in FIG.

The unexposed portions 122a and 122b shown in FIG.
Is moved to the right by two fine line width patterns (10 μm) relative to the unexposed portions 121a and 121b, as shown in FIG. 7, the pattern is moved to the right by 10 μm. There is a method of forming the second photomask thus prepared and performing the second exposure using the second photomask.

In still another method, the same first and second photomasks as those in the first embodiment are used (the positional relationship is also the same as in FIG. 1), and the reference function is used by using the aligning function of the step and repeater. The alignment mark (not shown) on the semiconductor substrate to be exposed is given an offset value in advance for exposure, the exposure position is moved with respect to the alignment mark (not shown), and unexposed with the positional relationship shown in FIG. Part 12
2a, 122b and the unexposed portions 121a, 121b are available.

In this method, the first exposure using the first photomask or the second exposure using the second photomask is performed.
If one of the exposure positions of the first exposure is moved, the positional relationship shown in FIG. 7 is obtained, but normally, in order to make the exposure position the same for the preceding and subsequent steps, the first photomask is used. In the exposure, the exposure was carried out by moving to the left by 10 μm, and FIG.
By obtaining the unexposed portions 122a and 122b and the unexposed portions 121a and 121b having the positional relationship of, a plane pattern different from that of the first embodiment (FIG. 3) shown in FIG. 8 is obtained.

(Embodiment 3) Next, referring to the drawings, a method of forming a plane pattern shape different from that of Embodiment 1 by using the first photomask used in Embodiment 1 of Embodiment 3 of the present invention. And explain. FIG. 9 is a plan view of a photomask in the method of forming a gate electrode according to the third embodiment of the present invention, and FIGS. 10 and 11 are plan views of a semiconductor substrate. The gate electrode forming process in the third embodiment is the same as that in the first embodiment.

In the third embodiment, the gate pad portion 142 is changed from the first embodiment (FIG. 1) as shown in FIG.
By performing the second exposure using the photomask of
An unexposed portion 123 (FIG. 11) having a plane pattern different from that of the first embodiment (FIG. 3) is obtained.

This is because the gate pad portion 142 of the first photomask is used as a light-shielding portion (FIG. 9), and the gate pad portion 142 is not exposed by the first exposure using the first photomask. Next (FIG. 10), the gate pad portion 142 is formed in the second exposure using the second photomask.
It is possible to pattern

(Embodiment 4) Next, regarding Embodiment 4 of the present invention, a photomask different from the first photomask used in Embodiment 1 is used to form a plane pattern shape different from that in the first embodiment. A method for doing so will be described with reference to the drawings. FIG. 12 is a top view of a photomask used in the gate electrode forming method according to the fourth embodiment of the present invention.
4 is a top view of the semiconductor substrate. The steps of forming the gate electrode in Example 4 are the same as those in Example 1.

Although the gate finger portions 141 of the photomask used in the first embodiment are all formed with the phase shifter portion 111 by using the edge transmission type phase shift method (FIG. 1), the embodiment is shown. 4, the edge transmission type phase shifter portion 111a (width is 5 μm), the transmission type phase shifter portion 111b (width is 0.3 μm) and the normal light shielding portion 111c (width is 0.6 μm) shown in FIG. 10/5 / 5μ
An example will be described in which 20 m intervals are provided at m intervals. In this example, the unexposed portions 121b, 121c,
The fine line width of 121d is 0.
Corresponding to 2, 0.3 and 0.6 μm.

Also in this embodiment, the first exposure is performed using this first photomask, the second exposure is performed using the second photomask shown in FIG. 12, and the result is shown in FIG. The unexposed portion 123 is obtained.

As described above, in the fourth embodiment, the gate finger portion 1 of the first photomask in which the fine line width patterns having different exposure methods and resist opening dimension widths are used for the first exposure.
By arranging in the portion corresponding to 41, the same first
It is possible to form a planar pattern having the gate finger portions 141 having different resist opening dimension widths from the photomask of FIG.

(Fifth Embodiment) In the first, second, third and fourth embodiments described above, the formation of the gate electrode pattern of each GaAs MESFET has been described. And explain.
FIG. 15 is a plan view of a first photomask for showing formation of the entire plane pattern of a gate electrode in Example 5 of the present invention, and FIGS. 16 and 17 are plan views of a semiconductor substrate. The steps of forming the gate electrode in Example 5 are the same as those in Example 1.

In the fifth embodiment, the first photomask has the phase shifter portion (111) forming the gate finger portion 141 and the gate pad portion 142 and the light shielding portion (101) in the vertical direction as shown in FIG. The gate finger end portions 143 and the gate pad portions 1 at the same time.
42). Although not shown, the portion corresponding to the gate finger portion 141 has the above-described first and second embodiments.
A plurality of phase shifter portions forming the fine dimension patterns shown by 2, 3 and 4 are arranged in parallel.

The first photomask shown in FIG. 15 is used for the first exposure, and the second photomask (not shown) is used.
Is used for the second exposure to perform selective exposure of the gate finger portion 141 and exposure of the gate pad portion 142 and the gate finger end portion 143 to form an unexposed portion 123 having a plane pattern as shown in FIG. The same resist opening pattern can be formed.

As described in the above-described embodiment, the plane shown in FIG. 16 is obtained by changing the gate finger portion 141 and the gate pad portion 142 selected in the second photomask used for this second exposure. By changing the unexposed portion 123 of the pattern, a different resist opening pattern can be formed.

In the process of processing the conductor film 4 in the process described in the first embodiment, the photoresist of the wiring pattern 151 is patterned to leave the conductor film 4 as shown in FIG. It is also possible to connect the wiring pattern 151 shown in FIG.

[0056]

As described above, according to the present invention, the first photomask in which the fine pattern is arranged is used.
Exposure, and then a second exposure with a second photomask is performed, a fine dimension pattern is selected by the second exposure, and the edge pattern is exposed, thereby connecting the selected fine dimension patterns. A plane pattern can be formed, and a plurality of product patterns can be created by commonly using one first photomask which is a phase shift mask.

The second photomask, which requires pattern formation and mask production for each individual product, can be formed by a normal photomask without using a fine line width pattern, and can be used for erasing unnecessary lines. Since it is not necessary to design a pattern, when the resist pattern formation using the phase shift mask is put into practical use, there is an effect that the pattern layout design can be facilitated and the mask creation period can be shortened.

[Brief description of drawings]

FIG. 1 is a plan view showing a photomask according to a first embodiment of the present invention.

FIG. 2 is a plan view showing a resist pattern of a semiconductor substrate in Example 1.

FIG. 3 is a plan view showing a plane pattern formed on a semiconductor substrate in Example 1.

FIG. 4 is a cross-sectional view showing the first embodiment of the present invention in the order of steps.

5A to 5C are cross-sectional views showing the first embodiment of the present invention in the order of steps.

FIG. 6 is a plan view showing a photomask according to a second embodiment of the present invention.

FIG. 7 is a plan view showing a resist pattern of a semiconductor substrate in Example 2.

FIG. 8 is a plan view showing a plane pattern formed on a semiconductor substrate according to a second embodiment.

FIG. 9 is a plan view showing a photomask according to a third embodiment of the present invention.

FIG. 10 is a plan view showing a resist pattern on a semiconductor substrate in Example 3.

FIG. 11 is a plan view showing a plane pattern formed on a semiconductor substrate in Example 3;

FIG. 12 is a plan view showing a photomask according to a fourth embodiment of the present invention.

FIG. 13 is a plan view showing a resist pattern on a semiconductor substrate in Example 4.

FIG. 14 is a plan view showing a plane pattern formed on a semiconductor substrate in Example 4.

FIG. 15 is a plan view showing a first photomask in Example 5 of the present invention.

FIG. 16 is a plan view showing a resist pattern on a semiconductor substrate in Example 5.

FIG. 17 is a plan view showing a plane pattern formed on a semiconductor substrate in Example 5.

FIG. 18 is a plan view showing a photomask in the related art.

FIG. 19 is a plan view showing a resist pattern of a semiconductor substrate according to a conventional technique.

FIG. 20 is a plan view showing a plane pattern formed on a semiconductor substrate according to a conventional technique.

FIG. 21 is a plan view showing a pattern of a normal photomask in a conventional technique.

[Explanation of symbols]

 1 Semiconductor Substrate 2 Dielectric Film 3 Photoresist Film 4 Dielectric Film 101 Light Shielding Part 102a First Light Shielding Part 102b Second Light Shielding Part 111 Phase Shifter Part 121a Unexposed Areas 122a, 122b Unexposed Part 123 Unexposed Part 131 Resist Opening part 141 Gate finger part 142 Gate pad part 143 Gate finger end part 151 Wiring pattern

Claims (3)

[Claims] 1. A fine pattern forming step and a fine pattern selecting step, wherein a plane pattern consisting of a combination of a fine pattern having a fine line width and a wide edge pattern is formed on a resist of a substrate by multiple exposure. A method of manufacturing a semiconductor device, comprising: a first photomask and a second photomask for multiple exposure, wherein the first photomask is used in a fine pattern forming step, and is a phase shifter. The phase shifter section shapes the exposure light into a shape of a fine pattern having a fine line width formed on the resist, and the phase shifter section is arranged in parallel according to the pitch of the fine pattern to be formed. A plurality of light-shielding parts are arranged in a shape of an unexposed region having an area to be secured on at least one side of the fine pattern on the resist and are connected to the phase shifter part. The second photomask is used in the fine pattern selecting step and has two light shielding portions, and the first light shielding portion covers the fine pattern of the plane pattern to shield light. The second light-shielding portion is shaped according to the shape of the edge pattern of the plane pattern, and the fine pattern forming step is performed on the resist of the substrate by the first shape. A step of irradiating exposure light through a photomask to form a plurality of fine patterns having a fine line width in parallel on the resist of the substrate and securing an unexposed region connected to the fine pattern. Covers a specific fine pattern to be used on the resist of the substrate that has undergone the fine pattern formation process with the first light shielding portion of the second photomask and secures it on the resist of the substrate. Was exposed portions of the unexposed area was covered with a second light-shielding portion of the second photomask, the second
2. A method for manufacturing a semiconductor device, which comprises the step of leaving the area shielded by the photomask as the planar pattern and eliminating the resist pattern in the other areas. 2. The phase shifter portion of the first photomask includes an edge-transmissive structure that forms a fine pattern having a fine line width at the contour position thereof. A method for manufacturing a semiconductor device as described above. 3. The phase shifter portion of the first photomask is made to have different lengths, and the phase shifter portion is used to form a fine pattern of a fine line width having a different length on a resist of a substrate. The method for manufacturing a semiconductor device according to claim 1 or 2.