JPH10294361A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH10294361A JPH10294361A JP10057497A JP10057497A JPH10294361A JP H10294361 A JPH10294361 A JP H10294361A JP 10057497 A JP10057497 A JP 10057497A JP 10057497 A JP10057497 A JP 10057497A JP H10294361 A JPH10294361 A JP H10294361A
- Authority
- JP
- Japan
- Prior art keywords
- film
- substrate
- semiconductor substrate
- oxide film
- thermosetting resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Mechanical Treatment Of Semiconductor (AREA)
- Element Separation (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体装置の製造
方法に関し、特に基板表面を平坦化するのに適した半導
体装置の製造方法に関する。The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device suitable for flattening a substrate surface.
【０００２】[0002]
【従来の技術】シャロートレンチにより素子分離を行う
技術が注目されている。図６（Ａ）及び６（Ｂ）は、共
に、従来のシャロートレンチ素子分離構造の作製方法を
示す基板断面図である。2. Description of the Related Art Attention has been paid to a technique for isolating elements by using shallow trenches. 6A and 6B are cross-sectional views of a substrate showing a method for manufacturing a conventional shallow trench element isolation structure.
【０００３】図６（Ａ）に示すように、シリコン基板５
０の表面にシャロートレンチ５０ａが形成されている。
シャロートレンチ５０ａの形成されていない凸部の頂上
には、ＳｉＮ膜５１が形成されている。この基板表面上
に、ＴＥＯＳ膜等のＳｉＯ2膜５２を堆積する。ＳｉＯ
2 膜５２の表面上に、レジスト膜を塗布し、シャロート
レンチ５０ａを形成したときのマスクと逆パターンのマ
スクを用いて露光する。レジスト膜を現像し、シャロー
トレンチ５０ａに対応する領域にレジストパターン５３
を残す。[0003] As shown in FIG.
The shallow trench 50a is formed on the surface of the "0".
An SiN film 51 is formed on the top of the projection where the shallow trench 50a is not formed. An SiO 2 film 52 such as a TEOS film is deposited on the surface of the substrate. SiO
A resist film is applied on the surface of the second film 52, and exposure is performed using a mask having a pattern opposite to the mask used when the shallow trench 50a is formed. The resist film is developed, and a resist pattern 53 is formed in a region corresponding to the shallow trench 50a.
Leave.
【０００４】レジストパターン５３をマスクとしてＳｉ
Ｏ2 膜５２をエッチングし、その後レジストパターン５
３を剥離する。ＳｉＯ2 膜５２を化学機械研磨し、表面
を平坦化する。[0004] Si using the resist pattern 53 as a mask
The O 2 film 52 is etched, and then the resist pattern 5
3 is peeled off. The SiO 2 film 52 is subjected to chemical mechanical polishing to planarize the surface.
【０００５】図６（Ｂ）に示す従来例の場合には、Ｓｉ
Ｏ2 膜５２を堆積した後、その表面上にポリシリコン膜
５５を堆積する。ポリシリコン膜５５を化学機械研磨
し、凸部上のポリシリコン膜５５ａを除去する。残った
ポリシリコン膜５５をマスクとして凸部のＳｉＯ2 膜５
２をエッチングする。ＳｉＯ2 膜５２のエッチング後、
ポリシリコン膜５５をエッチング除去する。その後の工
程は、図６（Ａ）の場合と同様である。[0005] In the case of the conventional example shown in FIG.
After depositing the O 2 film 52, a polysilicon film 55 is deposited on its surface. The polysilicon film 55 is subjected to chemical mechanical polishing to remove the polysilicon film 55a on the projection. Using the remaining polysilicon film 55 as a mask, the projected SiO 2 film 5
2 is etched. After the etching of the SiO 2 film 52,
The polysilicon film 55 is removed by etching. Subsequent steps are the same as those in the case of FIG.
【０００６】[0006]
【発明が解決しようとする課題】図６（Ａ）に示す従来
例の場合、図の左側の凸部のように孤立した微細パター
ンの上に堆積するＳｉＯ2 膜５２の厚さは、右側の凸部
のように比較的大きなパターンの上に堆積する厚さより
も薄い。このため、ＳｉＯ2 膜５２をエッチングする
と、孤立した微細パターンの凸部上面が露出してしまう
場合がある。In the case of the conventional example shown in FIG. 6A, the thickness of the SiO 2 film 52 deposited on the isolated fine pattern like the convex part on the left side of the figure is the same as that on the right side. It is thinner than the thickness deposited on a relatively large pattern such as a protrusion. Therefore, when the SiO 2 film 52 is etched, the upper surface of the convex portion of the isolated fine pattern may be exposed.
【０００７】図６（Ｂ）に示す従来例の場合には、ポリ
シリコン膜５５を研磨除去するとき、図の左側の孤立し
た微細な凸部に大きな圧力が加わり、この領域のポリシ
リコン膜５５及びＳｉＯ2 膜５２が余分に研磨される場
合がある。In the case of the conventional example shown in FIG. 6B, when the polysilicon film 55 is polished and removed, a large pressure is applied to the isolated fine protrusion on the left side of the figure, and the polysilicon film 55 in this region is removed. In some cases, the SiO 2 film 52 may be excessively polished.
【０００８】本発明の目的は、半導体基板表面に孤立し
た微細なパターンがある場合にも、安定して表面を平坦
化することができる方法を提供することである。An object of the present invention is to provide a method capable of stably flattening the surface even when there is an isolated fine pattern on the surface of the semiconductor substrate.
【０００９】[0009]
【課題を解決するための手段】本発明の一観点による
と、表面に凹凸を有する半導体基板を準備する工程と、
前記半導体基板の表面の凹部内に熱硬化性樹脂からなる
埋込材を配置する工程と、前記埋込材を加熱して硬化さ
せる工程と、前記硬化した埋込材と前記半導体基板の表
面の凸部とを同時に研磨し、表面を平坦化する工程とを
有する半導体装置の製造方法が提供される。According to one aspect of the present invention, there is provided a step of preparing a semiconductor substrate having an uneven surface.
Arranging an embedding material made of a thermosetting resin in a concave portion on the surface of the semiconductor substrate, heating and curing the embedding material, and curing the embedding material and the surface of the semiconductor substrate; Simultaneously polishing the projections and flattening the surface.
【００１０】埋込材を硬化させることにより、半導体基
板の凸部とほぼ同程度の研磨速度にすることができる。
埋込材と基板の凸部の研磨速度がほぼ同程度になると、
基板の表面の全領域においてほぼ研磨速度が同程度にな
り、基板表面の凹凸模様に依らず容易に平坦化すること
が可能になる。[0010] By hardening the embedding material, the polishing rate can be made substantially the same as that of the convex portion of the semiconductor substrate.
When the polishing rate of the embedding material and the convex part of the substrate become almost the same,
The polishing rate is almost the same in all regions of the substrate surface, and the substrate can be easily flattened regardless of the unevenness of the substrate surface.
【００１１】本明細書において、研磨は、ラッピング、
ポリシング、化学機械研磨を含むものとする。In this specification, polishing is wrapping,
Polishing and chemical mechanical polishing shall be included.
【００１２】[0012]
【発明の実施の形態】図１及び図２を参照して、本発明
の第１の実施例による半導体装置の製造方法を、素子分
離用のシャロートレンチ構造を形成する場合を例にとっ
て説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method of manufacturing a semiconductor device according to a first embodiment of the present invention will be described with reference to FIGS. 1 and 2 by taking as an example a case where a shallow trench structure for element isolation is formed.
【００１３】図１（Ａ）に示すように、シリコン基板１
の表面上に、温度８００℃のドライ酸化により、厚さ約
５ｎｍのパッド酸化膜２を形成する。パッド酸化膜２の
上に、化学気相堆積（ＣＶＤ）により厚さ約１１５ｎｍ
のＳｉＮ膜３を形成する。ＳｉＮ膜３の上に、シリコン
基板１の表面の活性領域に対応したレジストパターン４
を形成する。As shown in FIG. 1A, a silicon substrate 1
A pad oxide film 2 having a thickness of about 5 nm is formed by dry oxidation at a temperature of 800.degree. On the pad oxide film 2, a thickness of about 115 nm is formed by chemical vapor deposition (CVD).
Is formed. A resist pattern 4 corresponding to the active region on the surface of the silicon substrate 1 is formed on the SiN film 3.
To form
【００１４】図１（Ｂ）に示すように、レジストパター
ン４をマスクとしてＳｉＮ膜３及びパッド酸化膜２をエ
ッチングする。さらに、シリコン基板１をエッチング
し、深さ約０．３μｍのシャロートレンチ５を形成す
る。シリコン基板１のエッチングは、ＨＢｒ系ガスを用
いたドライエッチングにより行う。その後、レジストパ
ターン４を除去する。As shown in FIG. 1B, the SiN film 3 and the pad oxide film 2 are etched using the resist pattern 4 as a mask. Further, the silicon substrate 1 is etched to form a shallow trench 5 having a depth of about 0.3 μm. The etching of the silicon substrate 1 is performed by dry etching using an HBr-based gas. After that, the resist pattern 4 is removed.
【００１５】レジストパターン４の除去後、シャロート
レンチ５の内面に、温度９００℃のドライ酸化により厚
さ約１０ｎｍのスルー酸化膜６を形成する。スルー酸化
膜６は、シリコン基板１のエッチング時のダメージ除去
及びシャロートレンチ５の側壁保護を目的とする。素子
特性に問題を生じない場合には、スルー酸化膜６の形成
を省略してもよい。After the removal of the resist pattern 4, a through oxide film 6 having a thickness of about 10 nm is formed on the inner surface of the shallow trench 5 by dry oxidation at a temperature of 900.degree. The through oxide film 6 is intended to remove damage during etching of the silicon substrate 1 and to protect the side wall of the shallow trench 5. If there is no problem in device characteristics, the formation of the through oxide film 6 may be omitted.
【００１６】図１（Ｃ）に示すように、基板表面上に、
厚さ約６００ｎｍの埋込酸化膜７を堆積する。埋込酸化
膜７は、例えば原料ガスとしてＯ3 とＴＥＯＳを用いた
常圧ＣＶＤにより形成される。幅の狭いシャロートレン
チが形成された領域では、埋込酸化膜７の表面はほぼ平
坦になるが、比較的広いシャロートレンチが形成された
領域では、埋め込む酸化膜７の表面にシャロートレンチ
のパターンに対応した凹部８が形成される。As shown in FIG. 1C, on the substrate surface,
A buried oxide film 7 having a thickness of about 600 nm is deposited. The buried oxide film 7 is formed by, for example, normal pressure CVD using O 3 and TEOS as source gases. In the region where the narrow shallow trench is formed, the surface of the buried oxide film 7 is almost flat, but in the region where the relatively wide shallow trench is formed, the surface of the buried oxide film 7 has a pattern of the shallow trench. A corresponding recess 8 is formed.
【００１７】埋込酸化膜７の緻密化のため、Ｏ2 雰囲気
中で温度を１０００℃とし、約３０分間の熱処理を行
う。なお、埋込酸化膜７を高密度プラズマＣＶＤ（ＨＤ
ＰＣＶＤ）等のように十分緻密な膜を形成できる方法で
堆積した場合には、緻密化のための熱処理を省略しても
よい。In order to densify the buried oxide film 7, a heat treatment is performed in an O 2 atmosphere at a temperature of 1000 ° C. for about 30 minutes. The buried oxide film 7 is formed by high-density plasma CVD (HD
In the case where deposition is performed by a method capable of forming a sufficiently dense film such as PCVD), a heat treatment for densification may be omitted.
【００１８】図２（Ａ）に示すように、埋込酸化膜７の
上に、ノボラック系のレジスト膜９を回転塗布する。本
実施例では、レジスト膜９としてシプレイ社製のポジレ
ジストＭＰ−１３００を用いた。レジスト膜９は、シャ
ロートレンチ５の深さ、パッド酸化膜２の厚さ、及びＳ
ｉＮ膜３の厚さの合計よりもやや厚くなるように形成す
る。本実施例の場合には、レジスト膜９の厚さを０．５
〜０．６μｍとした。レジスト膜９の塗布後、大気中
で、温度１５０℃の熱処理を約２０分間行う。As shown in FIG. 2A, a novolak-based resist film 9 is spin-coated on the buried oxide film 7. In the present embodiment, a positive resist MP-1300 manufactured by Shipley Co., Ltd. was used as the resist film 9. The resist film 9 has a depth of the shallow trench 5, a thickness of the pad oxide film 2,
The iN film 3 is formed to be slightly thicker than the total thickness. In the case of this embodiment, the thickness of the resist film 9 is set to 0.5
０．６0.6 μm. After the application of the resist film 9, a heat treatment at a temperature of 150 ° C. is performed in the air for about 20 minutes.
【００１９】図２（Ｂ）に示すように、レジスト膜９を
化学機械研磨する。本実施例で用いた研磨材はキャボッ
ト社製のＳＣ−１１２、研磨布はロデール社製のＩＣ−
１０００／ＳＵＢＡ４００の２層研磨布である。また、
研磨時の基板回転数を８０ｒｐｍ、定盤回転数を８０ｒ
ｐｍ、研磨圧力を２３０ｇ／ｃｍ2 とした。As shown in FIG. 2B, the resist film 9 is subjected to chemical mechanical polishing. The abrasive used in this example was SC-112 manufactured by Cabot Corporation, and the polishing cloth was IC-112 manufactured by Rodale.
It is a two-layer polishing cloth of 1000 / SUBA400. Also,
The substrate rotation speed during polishing is 80 rpm, and the platen rotation speed is 80 r.
pm and a polishing pressure of 230 g / cm 2 .
【００２０】この研磨により、レジスト膜９の凸部が除
去され、埋込酸化膜７の表面に形成されている凹部８内
にレジスト膜９からなる埋込材９ａが残る。大気中で、
温度２２０℃の熱処理を２０分間行う。この熱処理によ
り、埋込材９ａが硬化する。By this polishing, the convex portions of the resist film 9 are removed, and the burying material 9a made of the resist film 9 remains in the concave portions 8 formed on the surface of the buried oxide film 7. In the atmosphere,
A heat treatment at a temperature of 220 ° C. is performed for 20 minutes. By this heat treatment, the embedding material 9a is hardened.
【００２１】図２（Ｃ）に示すように、埋込酸化膜７と
埋込材９ａとを同時に研磨し、ＳｉＮ膜３が露出した時
点で研磨を停止する。研磨材、研磨布、研磨圧力は、図
２（Ｂ）の工程で行ったレジスト膜９の研磨と同様であ
る。シャロートレンチ５内にのみ、埋込酸化膜７ａが残
る。As shown in FIG. 2C, the buried oxide film 7 and the burying material 9a are simultaneously polished, and the polishing is stopped when the SiN film 3 is exposed. The abrasive, the polishing cloth, and the polishing pressure are the same as in the polishing of the resist film 9 performed in the step of FIG. The buried oxide film 7a remains only in the shallow trench 5.
【００２２】ＳｉＮ膜３とパッド酸化膜２を除去し、活
性領域にシリコン基板１の表面を露出させる。その後、
活性領域内に所望の半導体素子を形成する。活性領域に
露出したシリコン基板１の表面と埋込酸化膜７ａの表面
との間に、ＳｉＮ膜３とパッド酸化膜２の合計の厚さ分
程度の段差が生ずるが、この程度の段差は、その後の処
理において問題にはならない。The SiN film 3 and the pad oxide film 2 are removed, and the surface of the silicon substrate 1 is exposed in the active region. afterwards,
A desired semiconductor device is formed in the active region. Between the surface of the silicon substrate 1 exposed to the active region and the surface of the buried oxide film 7a, there is a step of about the total thickness of the SiN film 3 and the pad oxide film 2, but this step is It does not matter in subsequent processing.
【００２３】図２（Ｂ）の工程で、凹部８内に埋込材９
ａが埋め込まれ、ほぼ平坦な表面が得られている。ま
た、図２（Ｃ）の研磨の前に、埋込材９ａを熱処理して
硬化させている。埋込材９ａの研磨速度と埋込酸化膜７
の研磨速度とが等しいかまたは近似している場合には、
図２（Ｃ）の研磨工程にける研磨速度が、基板の表面の
全域でほぼ等しくなるため、基板表面の凹凸模様に依ら
ず平坦な表面を得ることが可能になる。In the step of FIG. 2B, the embedding material 9 is
a is buried, and a substantially flat surface is obtained. Before the polishing in FIG. 2C, the embedding material 9a is cured by heat treatment. Polishing rate of embedded material 9a and embedded oxide film 7
If the polishing rate is equal or close to
Since the polishing rate in the polishing step of FIG. 2C is substantially equal over the entire surface of the substrate, a flat surface can be obtained regardless of the unevenness of the substrate surface.
【００２４】図４は、レジスト膜の熱処理温度と研磨速
度との関係を示す。図４（Ａ）及び４（Ｂ）ともに、横
軸は熱処理温度を単位℃で表し、縦軸は研磨速度を単位
ｎｍ／分で表す。図４（Ｂ）は図４（Ａ）の縦軸のスケ
ールを拡大したものである。図中の記号○及び●は、そ
れぞれ研磨圧力を７０ｇ／ｃｍ2 及び２３０ｇ／ｃｍ 2
とした場合を示す。なお、用いたレジスト材料、研磨材
及び研磨布は、上述の実施例の場合と同様である。FIG. 4 shows the heat treatment temperature and polishing speed of the resist film.
Shows the relationship with degrees. 4 (A) and 4 (B) are both horizontal.
The axis is the heat treatment temperature in units of ° C, and the vertical axis is the polishing rate.
Expressed in nm / min. FIG. 4B is a scale of the vertical axis of FIG.
It is an expansion of the rules. The symbols ○ and ● in the figure are
Each polishing pressure is 70g / cmTwoAnd 230 g / cm Two
Is shown. In addition, used resist material, abrasive material
The polishing cloth is the same as in the above embodiment.
【００２５】図４（Ａ）に示すように、熱処理温度を高
くすると、レジスト膜が硬化して研磨速度が遅くなる。
研磨圧力２３０ｇ／ｃｍ2 の条件で大きな研磨速度を得
たい場合には、熱処理温度を１７０℃以下にすることが
好ましい。従って、図２（Ａ）におけるレジスト膜９の
熱処理温度を１７０℃以下とすることが好ましい。熱処
理温度が２００℃を超えると、研磨速度が非常に遅くな
る。これは、高温の熱処理により、レジスト膜が変質す
るためと考えられる。As shown in FIG. 4A, when the heat treatment temperature is increased, the resist film is hardened and the polishing rate is reduced.
To obtain a high polishing rate under the condition of a polishing pressure of 230 g / cm 2 , the heat treatment temperature is preferably set to 170 ° C. or lower. Therefore, it is preferable that the heat treatment temperature of the resist film 9 in FIG. When the heat treatment temperature exceeds 200 ° C., the polishing rate becomes very slow. This is presumably because the high-temperature heat treatment deteriorates the resist film.
【００２６】図５は、レジスト膜の光透過特性を示す。
横軸は波数を単位ｃｍ-1で表し、縦軸は透過率を任意目
盛りで表す。図中の太線は熱処理温度を２６０℃とした
場合を示し、細線は１２０℃とした場合を示す。FIG. 5 shows the light transmission characteristics of the resist film.
The horizontal axis represents the wave number in cm −1 , and the vertical axis represents the transmittance on an arbitrary scale. The thick line in the figure shows the case where the heat treatment temperature was set to 260 ° C, and the thin line shows the case where the heat treatment temperature was set to 120 ° C.
【００２７】熱処理温度を１２０℃とした場合には、波
数１５００ｃｍ-1近傍にベンゼン環骨格振動による鋭い
吸収ａ、１６００ｃｍ-1近傍にベンゼン環骨格振動もし
くはＮ−Ｈ変角振動による吸収ｂ、波数３０００〜２３
００ｃｍ-1にアミン塩のＮ−Ｈ+ 伸縮振動によるブロー
ドな吸収ｃ、波数３５００〜３３００ｃｍ-1にＯ−Ｈ伸
縮振動及びＮ−Ｈ伸縮振動によるブロードな吸収ｄが見
られる。The heat treatment when the set to 120 ° C. temperature, wave number 1500 cm -1 sharp absorption a by a benzene ring skeleton vibration in the vicinity, the absorption by the benzene ring skeleton vibration or N-H deformation vibration near 1600 cm -1 b, wavenumber 3000-23
00cm -1 to amine salts N-H + stretching vibration by broad absorption c, O-H stretching vibration and N-H stretching broad absorption d by the vibration is observed at a wavenumber 3500~3300cm -1.
【００２８】これに対し、熱処理温度を２６０℃とした
場合には、波数１５００ｃｍ-1近傍のベンゼン環骨格振
動による鋭い吸収が小さくなり、波数３０００〜２３０
０ｃｍ-1及び波数３５００〜３３００ｃｍ-1の吸収率が
減少している。このことから、２６０℃で熱処理するこ
とによりＮ−Ｈ基がアミン塩からアミンに変化し、ベン
ゼン環が消失し緻密なネットワークに変化していると考
えられる。この変質により、レジスト膜の研磨速度が遅
くなるものと考えられる。On the other hand, when the heat treatment temperature is 260 ° C., the sharp absorption due to the benzene ring skeleton vibration near the wave number of 1500 cm −1 is small, and the wave number is 3000 to 230.
Absorption rate of 0 cm -1 and a wavenumber 3500～3300Cm -1 is reduced. From this, it is considered that the heat treatment at 260 ° C. changes the NH group from an amine salt to an amine, loses the benzene ring, and changes to a dense network. It is considered that the polishing speed of the resist film is decreased due to the alteration.
【００２９】図４（Ｂ）に、ＳｉＯ2 の研磨速度約８０
ｎｍ／分を細い破線で示す。レジスト膜の熱処理温度を
約２２０℃とすると、研磨速度がＳｉＯ2 のそれとほぼ
等しくなることがわかる。従って、図２（Ｂ）に示す熱
処理工程の温度を２２０℃とすることにより、埋込材９
ａとその周囲の埋込酸化膜７との研磨速度がほぼ等しく
なり、平坦化し易くなる。FIG. 4B shows that the polishing rate of SiO 2 is about 80.
nm / min is indicated by a thin dashed line. When the heat treatment temperature of the resist film is set to about 220 ° C., the polishing rate becomes almost equal to that of SiO 2 . Therefore, by setting the temperature of the heat treatment step shown in FIG.
The polishing rate of a and the buried oxide film 7 therearound are substantially equal to each other, and it is easy to flatten.
【００３０】次に、図３を参照して、第２の実施例によ
る半導体装置の製造方法を説明する。上述の第１の実施
例と同様の工程により、図２（Ａ）に示すレジスト膜９
の塗布及び熱処理までを実行する。Next, a method of manufacturing a semiconductor device according to the second embodiment will be described with reference to FIG. By the same process as in the first embodiment, the resist film 9 shown in FIG.
Until the application and heat treatment.
【００３１】図３に示すように、レジスト膜９を露光、
現像することによりパターニングし、埋込酸化膜７の表
面に形成された凹部８内にレジスト膜９からなる埋込材
９ｂを残す。大気中で、温度２２０℃の熱処理を約２０
分間行い、埋込材９ｂを硬化させる。As shown in FIG. 3, the resist film 9 is exposed,
By patterning by development, an embedding material 9b made of a resist film 9 is left in a concave portion 8 formed on the surface of the embedding oxide film 7. In air, heat treatment at a temperature of 220 ° C for about 20
This is performed for minutes, and the embedding material 9b is cured.
【００３２】埋込材９ｂと埋込酸化膜７とを、ＳｉＮ膜
３が露出するまで研磨する。この研磨により、第１の実
施例の場合と同様に、図２（Ｃ）に示すように表面を平
坦化することができる。この場合も、埋込材９ｂがその
周囲の埋込酸化膜７と同程度の研磨速度になっているた
め、第１の実施例の場合と同様に、容易に平坦な面を得
ることができる。The burying material 9b and the buried oxide film 7 are polished until the SiN film 3 is exposed. By this polishing, the surface can be flattened as shown in FIG. 2C, as in the case of the first embodiment. Also in this case, since the embedding material 9b has the same polishing rate as that of the surrounding embedding oxide film 7, a flat surface can be easily obtained as in the case of the first embodiment. .
【００３３】図３の状態で、埋込材９ｂの上面と埋込酸
化膜７の上面との高さを揃えるために、図２（Ａ）に示
すレジスト膜９の厚さを凹部８の深さと同程度にするこ
とが好ましい。すなわち、シャロートレンチ５の深さ、
パッド酸化膜２の厚さ、及びＳｉＮ膜３の厚さの合計と
ほぼ等しい厚さとすることが好ましい。In the state of FIG. 3, in order to make the upper surface of the burying material 9b and the upper surface of the buried oxide film 7 uniform, the thickness of the resist film 9 shown in FIG. It is preferable to make the same. That is, the depth of the shallow trench 5,
It is preferable that the thickness be substantially equal to the sum of the thickness of the pad oxide film 2 and the thickness of the SiN film 3.
【００３４】上記実施例では、シャロートレンチ構造を
形成する場合を例に説明したが、上記実施例は、一般に
表面に凹凸を有する半導体基板の平坦化に適用可能であ
る。In the above embodiment, the case where the shallow trench structure is formed has been described as an example. However, the above embodiment can be generally applied to flattening of a semiconductor substrate having an uneven surface.
【００３５】上記第１の実施例では、凹部を埋め込む埋
込材としてノボラック系のレジストを用いたが、レジス
ト以外の熱硬化性樹脂を用いてもよい。また、第２の実
施例の場合には、熱硬化性のその他のフォトレジスト、
例えば水銀のｉ線用レジスト、化学増幅型レジスト等を
用いてもよい。In the first embodiment, a novolak-based resist is used as an embedding material for embedding the recess, but a thermosetting resin other than the resist may be used. Further, in the case of the second embodiment, other thermosetting photoresists,
For example, a resist for i-line of mercury, a chemically amplified resist, or the like may be used.
【００３６】以上実施例に沿って本発明を説明したが、
本発明はこれらに制限されるものではない。例えば、種
々の変更、改良、組み合わせ等が可能なことは当業者に
自明であろう。The present invention has been described in connection with the preferred embodiments.
The present invention is not limited to these. For example, it will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.
【００３７】[0037]
【発明の効果】以上説明したように、本発明によれば、
表面に凹凸を有する半導体基板の凹部を熱硬化性樹脂で
埋込み、この樹脂を硬化させて基板表面材料とほぼ同程
度の研磨速度にする。硬化した樹脂と半導体表面とを同
時に研磨することにより、表面を平坦化することができ
る。As described above, according to the present invention,
A concave portion of a semiconductor substrate having irregularities on its surface is embedded with a thermosetting resin, and the resin is cured to a polishing rate substantially equal to that of the substrate surface material. By polishing the cured resin and the semiconductor surface simultaneously, the surface can be flattened.
【図１】本発明の第１の実施例による半導体装置の製造
方法を説明するための基板断面図である。FIG. 1 is a sectional view of a substrate for describing a method of manufacturing a semiconductor device according to a first embodiment of the present invention.
【図２】本発明の第１の実施例による半導体装置の製造
方法を説明するための基板断面図である。FIG. 2 is a sectional view of a substrate for explaining a method of manufacturing the semiconductor device according to the first embodiment of the present invention.
【図３】本発明の第２の実施例による半導体装置の製造
方法を説明するための基板断面図である。FIG. 3 is a sectional view of a substrate for explaining a method of manufacturing a semiconductor device according to a second embodiment of the present invention.
【図４】レジスト膜の熱処理温度と研磨速度との関係を
示すグラフである。FIG. 4 is a graph showing a relationship between a heat treatment temperature of a resist film and a polishing rate.
【図５】レジスト膜を、１２０℃と２６０℃の２つの温
度で熱処理した後の光透過特性を比較して示すグラフで
ある。FIG. 5 is a graph showing a comparison of light transmission characteristics after heat treatment of a resist film at two temperatures of 120 ° C. and 260 ° C.
【図６】従来例によるシャロートレンチ構造の形成方法
を説明するための基板断面図である。FIG. 6 is a sectional view of a substrate for explaining a method of forming a shallow trench structure according to a conventional example.
１ シリコン基板 ２ パッド酸化膜 ３ ＳｉＮ膜 ４ レジストパターン ５ シャロートレンチ ６ スルー酸化膜 ７、７ａ 埋込酸化膜 ８ 凹部 ９ レジスト膜 ９ａ、９ｂ 埋込材 Reference Signs List 1 silicon substrate 2 pad oxide film 3 SiN film 4 resist pattern 5 shallow trench 6 through oxide film 7, 7a buried oxide film 8 concave portion 9 resist film 9a, 9b burying material
Claims (5)
る工程と、 前記半導体基板の表面の凹部内に熱硬化性樹脂からなる
埋込材を配置する工程と、 前記埋込材を加熱して硬化させる工程と、 前記硬化した埋込材と前記半導体基板の表面の凸部とを
同時に研磨し、表面を平坦化する工程とを有する半導体
装置の製造方法。A step of preparing a semiconductor substrate having irregularities on the surface; a step of arranging an embedding material made of a thermosetting resin in a concave portion of the surface of the semiconductor substrate; and heating the embedding material. A method of manufacturing a semiconductor device, comprising: a step of curing; and a step of polishing the cured embedding material and a convex portion on a surface of the semiconductor substrate at the same time to flatten the surface.
程と、 前記熱硬化性樹脂膜を研磨して、前記半導体基板の表面
の凸部上の熱硬化性樹脂膜の少なくとも一部を除去し、
凹部内に熱硬化性樹脂からなる前記埋込材を残す工程と
を含む請求項１に記載の半導体装置の製造方法。2. The step of arranging the embedding material, the step of applying a thermosetting resin film on the surface of the semiconductor substrate; and the step of polishing the thermosetting resin film to form a surface of the semiconductor substrate. Remove at least a part of the thermosetting resin film on the convex portion,
Leaving the embedding material made of a thermosetting resin in the concave portion.
後、前記凸部上の熱硬化性樹脂膜を除去する工程の前
に、さらに、前記熱硬化性樹脂膜を、前記硬化させる工
程における加熱温度よりも低い温度で熱処理する工程を
含む請求項２に記載の半導体装置の製造方法。3. The step of curing the thermosetting resin film after the step of applying the thermosetting resin film and before the step of removing the thermosetting resin film on the projections. 3. The method of manufacturing a semiconductor device according to claim 2, further comprising a step of performing a heat treatment at a temperature lower than a heating temperature in the step (a).
り、 前記埋込材を配置する工程が、 前記半導体基板の表面上にフォトレジスト膜を塗布する
工程と、 前記フォトレジスト膜を部分的に露光して前記半導体基
板の表面の凸部上のフォトレジスト膜を現像除去し、凹
部内にフォトレジストからなる前記埋込材を残す工程と
を有する請求項１に記載の半導体装置の製造方法。4. The method according to claim 1, wherein the thermosetting resin is a photoresist, the step of disposing the embedding material includes a step of applying a photoresist film on a surface of the semiconductor substrate, and a step of partially applying the photoresist film. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of exposing and developing the photoresist film on the convex portion on the surface of the semiconductor substrate to leave the embedded material of the photoresist in the concave portion.
形成する工程と、 表面にシャロートレンチを形成した半導体基板の該表面
上に、絶縁膜を堆積する工程とを含む請求項１〜４のい
ずれかに記載の半導体装置の製造方法。5. The step of preparing the semiconductor substrate, comprising the steps of: forming a shallow trench for element isolation on the surface of the semiconductor substrate; and forming an insulating film on the surface of the semiconductor substrate having the shallow trench formed on the surface. The method for manufacturing a semiconductor device according to claim 1, further comprising: depositing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10057497A JPH10294361A (en) | 1997-04-17 | 1997-04-17 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10057497A JPH10294361A (en) | 1997-04-17 | 1997-04-17 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH10294361A true JPH10294361A (en) | 1998-11-04 |
Family
ID=14277679
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10057497A Withdrawn JPH10294361A (en) | 1997-04-17 | 1997-04-17 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH10294361A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1071121A1 (en) * | 1999-07-19 | 2001-01-24 | International Business Machines Corporation | Process for the formation of a collar oxide in a trench in a semiconductor substrate |
| KR20010058498A (en) * | 1999-12-30 | 2001-07-06 | 박종섭 | Method of forming trench type isolation layer in semiconductor device |
| JP2003059874A (en) * | 2001-08-10 | 2003-02-28 | Hitachi Chem Co Ltd | Method of polishing board |
| KR20040038145A (en) * | 2002-10-31 | 2004-05-08 | 주식회사 하이닉스반도체 | Method for forming isolation layer of semiconductor device |
| JP2010058196A (en) * | 2008-09-02 | 2010-03-18 | Nikon Corp | Method and apparatus for polishing |
| JP2010192919A (en) * | 2001-05-24 | 2010-09-02 | Internatl Business Mach Corp <Ibm> | Method for protecting semiconductor shallow trench isolation (sti) oxide from etching |
| JP2013062544A (en) * | 2004-10-06 | 2013-04-04 | Commissariat A L'energie Atomique & Aux Energies Alternatives | Method for manufacturing mixed stacked structures having various insulating zones and/or electrically conductive zones vertically localized |
-
1997
- 1997-04-17 JP JP10057497A patent/JPH10294361A/en not_active Withdrawn
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1071121A1 (en) * | 1999-07-19 | 2001-01-24 | International Business Machines Corporation | Process for the formation of a collar oxide in a trench in a semiconductor substrate |
| KR20010058498A (en) * | 1999-12-30 | 2001-07-06 | 박종섭 | Method of forming trench type isolation layer in semiconductor device |
| JP2010192919A (en) * | 2001-05-24 | 2010-09-02 | Internatl Business Mach Corp <Ibm> | Method for protecting semiconductor shallow trench isolation (sti) oxide from etching |
| JP2003059874A (en) * | 2001-08-10 | 2003-02-28 | Hitachi Chem Co Ltd | Method of polishing board |
| KR20040038145A (en) * | 2002-10-31 | 2004-05-08 | 주식회사 하이닉스반도체 | Method for forming isolation layer of semiconductor device |
| JP2013062544A (en) * | 2004-10-06 | 2013-04-04 | Commissariat A L'energie Atomique & Aux Energies Alternatives | Method for manufacturing mixed stacked structures having various insulating zones and/or electrically conductive zones vertically localized |
| JP2010058196A (en) * | 2008-09-02 | 2010-03-18 | Nikon Corp | Method and apparatus for polishing |
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