JPH10293630A - Or circuit and peripheral equipment power supply disconnection system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the occurrence of data damage and data loss on the side of peripheral equipment without reducing a disconnecting speed even when urgent disconnection of internal power supply is executed by taking a logical sum of a power supply disconnection instruction signal and a signal which shows that data is now processed when internal power supply of a central processing unit is disconnected. SOLUTION: Internal power supply of a central processing unit 10 is shifted to a disconnection state, a central processing unit power supply interlock controlling part 13 outputs a 'power supply disconnection instruction signal' to a power supply disconnection signal line 20. The 'power supply disconnection instruction signal' is inputted to a logic circuit 1 which continues to operate even when the internal power supply of the unit 10 is in a disconnected state, and a logical sum is taken from it with a signal line 21 which shows that data is now processed. Here, if 'a signal which shows that data is now processed' is outputted to the line 21 which shows that data is now processed, the 'signal which shows that data is now processed' is outputted to a logical signal line 22. As a result, even though the internal power supply of the unit 10 is shifted to a disconnected state, power is continuously supplied to peripheral equipment 11 which now processes data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing system, and more particularly to a system for powering off peripheral devices using a power supply interlocking device.

[0002]

2. Description of the Related Art In a conventional information processing system, one of power-off methods from a central processing unit to peripheral devices is as follows.
As shown in FIG. 5, a power control signal 51 is sent from the central processing unit 10 to the peripheral device 11, and in accordance with the content (or change) of the power control signal 51, the built-in power supply 18 ( There is a method in which the peripheral device 11 itself disconnects a power supply or the like. In the case of this method, the peripheral device 11 from which the built-in power supply 18 is disconnected is provided with an analyzing unit 15 for analyzing a power control signal 51 sent from the central processing unit 10, and receiving an instruction from the analyzing unit 15. The peripheral device 11
And a cutting section 16 for cutting off the built-in power supply 18.
In this method, in order to cause the peripheral device 11 to maintain the power-off state, the central processing unit 10 generally works on the peripheral device 11 to maintain the power-off state even after the central processing unit 10 is powered off. It was a target.

Now, in order to solve the above problem, for example,
The following two power control methods have been proposed. In the first method, as shown in FIG. 6, one power switch 36 for controlling the power of the entire information processing system is provided, and the power switch 3 is provided.
6, the power supply from the power supply device 19 to various devices such as the central processing unit 10 and the peripheral device 11 is immediately stopped.

In a second system, the central processing unit itself performs a disconnection operation of the power switch of the first system. As shown in FIG. 7, an analysis unit 15 and a power supply disconnection unit 1 are provided.
6 or a multi-tap connected under the control of the power supply device and having the analysis unit 15 and the cutting unit 16 to supply power to the peripheral device 11. In the present invention, a power supply device or a multi-tap having the analysis unit 15 and the cutting unit 16 is particularly referred to as a “power supply interlocking device”, and FIG.

[0005] Regardless of which of the above two methods is adopted, it is necessary to take measures to prevent accidental disconnection of power supply during operation of the peripheral device. The reason is that, for example, if the power is turned off by mistake during data transfer to the magnetic file device, the recorded contents of the magnetic file device may be destroyed to an unrecoverable level.
Similarly, if the power is turned off by mistake while printing the print wait data stored in the printer's internal buffer, the print wait data will be lost, and after the power is restored, the data must be retransmitted from the central processing unit. Is caused.

As a countermeasure in the case of the above-mentioned first method, for example, a countermeasure as disclosed in Japanese Patent Application Laid-Open No. 13608/1988 is proposed. That is, as shown in FIG.
The data transfer request signal 52 output from the controller 39 and input to the microcomputer 37 is used as a “signal indicating that data is being processed”, and the data transfer request signal 52 and the ON / OFF signal generated by the power switch 36 are used.
By inputting the AND value with the OFF signal to the relay switch 41 via the NAND circuit 40, the power switch 3
In the event of an erroneous operation of the central processing unit 6,
Power supply to various devices such as the peripheral processing device 11 and the like is not interrupted immediately.

As a countermeasure in the case of the above-mentioned second method, as shown in FIG. 9, a peripheral device power supply interlocking control unit 14 is added to the peripheral device 11, and a monitoring control unit 42 is added to the central processing unit 10. By doing that. When the peripheral device 11 is performing data processing, the peripheral device power supply interlocking control unit 14 outputs a “signal indicating that data processing is in progress” to the signal line 21 that indicates that data processing is in progress. The signal shown was transmitted to the central processing unit 10. On the other hand, the monitoring control unit 42 constantly monitors the “signal indicating that data processing is being performed”, waits for the completion of data processing in the peripheral device 11, and then sends the subordinate peripheral device ( Power supply disconnection was instructed to peripheral device 11).

[0008] In recent computer systems, it has become common for the central processing unit itself to perform "emergency disconnection" of a power supply built in the central processing unit. Especially U
In the case of a UNIX-based computer system, this function is also available from the application level. For example, when an application program issues a shutdown command, the OS (UNIX) performs the closing process of the OS itself at a high speed and completes the process. Later, the central processing unit performed an emergency disconnection of the power supply incorporated therein. Here, the closing process of the OS itself includes the emergency saving of data during or managed by the OS, and as a result, at the next startup,
The OS can resume the work from the interruption point in the OS operation or immediately before. On the other hand, the hardware of the central processing unit performs its own shutdown processing with the highest priority, and therefore shuts off its own internal power supply regardless of the processing status of the peripheral device. As a result, power supply to the peripheral device may be accidentally cut off during operation of the peripheral device.

Of course, even if the OS closing process is performed at a high speed, if the hardware level of the conventional peripheral device is the same,
Since the data processing operation in the peripheral device was almost completed within the time of the closing process of S, this problem did not become apparent. However, recent peripheral devices have a huge buffer (may be a large-capacity memory or a hard disk) inside the peripheral device in order to speed up data transfer.
Peripheral devices that perform bulk transfer of a large amount of data are increasing, and this problem is starting to appear.

As one of measures for solving this problem, as shown in, for example, JP-A-6-102971 (see FIG. 8), a peripheral control device 43 is provided between the central processing unit 10 and the peripheral device 11. There is a method for preventing the adverse effect of the shutdown of the central processing unit 10 from being propagated to the peripheral device 11 by providing the peripheral device 11. However, in this method, the peripheral control device 43
This method requires a special device to be installed, and this system is not general except for a large computer system.

[0011]

A problem in a computer system for controlling the power supply of peripheral devices using a conventional power supply interlocking device is that a process such as a shutdown which is often seen in recent UNIX-based computer systems causes a problem. When the power supply built in the central processing unit is "emergency cut off" by the central processing unit itself, data destruction or loss may occur on the peripheral device side. The reason is,
The shutdown process is a process in which the OS (UNIX) performs a closing process of the OS itself at a high speed, and after the completion, performs an emergency disconnection of a power supply built in the central processing unit. However, the shutdown process is performed with the highest priority. This is because the internal power supply of the central processing unit is cut off irrespective of the processing status of the peripheral unit, and the power supply to the peripheral unit may be cut off accidentally during the operation of the peripheral unit.

It is an object of the present invention to provide a computer system which uses a power supply interlocking device to power off peripheral devices from a central processing unit. An object of the present invention is to suppress the occurrence of data destruction and data loss on the peripheral device side without lowering the speed and at a low cost.

[0013]

According to the present invention, the CPU operates continuously even when the internal power supply of the central processing unit is turned off, and when the internal power supply of the central processing unit is turned off. Taking a logical sum of a power-off instruction signal continuously issued from the central processing unit to the peripheral device and a signal indicating that data processing is being performed issued from the peripheral device, and linking the logically summed signal to the power supply An OR circuit characterized by being input to the device is obtained.

Further, according to the present invention, there is provided a peripheral device power-off system, wherein the OR circuit is built in the central processing unit.

Further, according to the present invention, there is provided a peripheral device power-off system, wherein the OR circuit is built in the power supply interlocking device.

[0016]

The logical OR circuit which operates continuously even when the internal power supply of the central processing unit is in the cut-off state is such that when the internal power supply of the central processing unit is in the cut-off state, the central processing unit continuously emits to the peripheral devices. By taking the logical OR of the "power-off instruction signal" and the "signal indicating that data processing is in progress" issued when the peripheral device is processing data, and giving this as a power control signal to the power interlocking device, the data in the peripheral device is processed. This prevents a power interlocking device from accidentally cutting off power supply to peripheral devices during processing.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a first embodiment of the present invention. In FIG. 1, a peripheral device 11 is connected to a central processing unit 10. The central processing unit 10 is connected to the central processing unit AC cable 23.
The peripheral device 11 is supplied with power from the AC outlet 17 of the power supply interlocking device 12 via the peripheral device AC cable 24. Here, the power supply interlocking device 12
May be a power supply device or a multi-tap connected under the power supply device. In this embodiment, the power supply interlocking device 1 is assumed assuming a multi-tap shape.
2 is supplied via the power supply interlocking device AC cable 25. The central processing unit 10 includes a central processing unit power supply interlocking control unit 13. The central processing unit power supply interlocking control unit 13 continuously outputs a “power-off instruction signal” on the power-off signal line 20 when the internal power supply of the central processing unit 10 is in the cut-off state.

On the other hand, the peripheral device 11 has a built-in peripheral device power supply interlocking control unit 14. When the peripheral device 11 is performing data processing, the peripheral device power supply interlocking control unit 14 outputs a “signal indicating that data processing is in progress” on the signal line 21 indicating that data processing is in progress. Further, the power supply interlocking device 12 includes an analysis unit 15, a cutting unit 16, and an AC outlet 17. A power-off signal line 20 and a signal line 21 indicating that data is being processed are input to the logical sum circuit 1 which operates continuously even when the internal power supply of the central processing unit 10 is in a cut-off state. Output to the OR signal line 22. The OR signal line 2
2 is input to the power supply interlocking device 12, and the input value is analyzed by the analysis unit 15. The disconnecting unit 16 switches between supplying and disconnecting the power taken from the power interlocking device AC cable 25 to the AC outlet 17 according to the analysis result of the analyzing unit 15.

Next, the operation of the first embodiment of the present invention will be described with reference to FIG. When the internal power supply of the central processing unit 10 is energized, the central processing unit power supply interlocking control unit 13 outputs a “power-on instruction signal” to the power-off signal line 20. The “power-on instruction signal” is input to the OR circuit 1, and as a result of the OR operation, the OR signal line 22 is output regardless of the state of the signal line 21 indicating that the data is being processed.
Outputs the "power-on instruction signal". The analysis unit 15 included in the power supply interlocking device 12 receives the “power-on instruction signal”, gives an energization instruction to the disconnection unit 16, and
Power is supplied to the C outlet 17 and the peripheral device AC
Power is supplied to the peripheral device 11 via the cable 24. That is, when the internal power supply of the central processing unit 10 is in the energized state, power is supplied to the peripheral device 11.

On the other hand, if the peripheral device 11 is performing data processing, the peripheral device power supply interlocking control unit 14 sends the “signal indicating that data processing is in progress” to the signal line 21 indicating that data processing is in progress.
Is output, and if the data is not being processed, the aforementioned "signal indicating that the data is being processed" is not output.

When the internal power supply of the central processing unit 10 is turned off, the central processing unit power supply interlocking control unit 13 outputs the above-mentioned “power-off instruction signal” to the power-off signal line 20. The “power-off instruction signal” is transmitted to the central processing unit 10
Is input to the OR circuit 1 which continuously operates even when the internal power supply is in a disconnected state, and the logical sum of the signal line 21 indicating that the data processing is being performed is obtained. Here, if the "signal indicating that data is being processed" is output to the signal line 21 indicating that data is being processed, the "signal indicating that data is being processed" is output to the logical sum signal line 22. As a result, the central processing unit 1
Even if the built-in power supply 0 is shifted to the cut-off state, the power is continuously supplied to the peripheral device 11 which is performing data processing.

On the other hand, when the internal power supply of the central processing unit 10 is in a cut-off state and the data processing in the peripheral device 11 is completed, the central processing unit power supply interlocking control unit 13 On the other hand, the "power-off instruction signal"
And the peripheral device power supply interlocking control unit 14 does not output the “signal indicating that data is being processed” to the signal line 21 indicating that the data is being processed. A signal is output, and as a result, the power supply to the peripheral device 11 that has completed the data processing is cut off.

FIG. 2 shows an example in which the first embodiment of the present invention is disassembled into a “circuit diagram”. A method for realizing an OR circuit that operates continuously even when the internal power supply of the central processing unit is in a cut-off state, and a "power-off instruction signal" can be continuously output from the central processing unit whose internal power supply is cut off This is a circuit configuration in which a specific method of realizing the central processing unit power supply interlocking control unit is represented using a relay (hereinafter simply referred to as RL).

Referring to FIG. 2, the central processing unit 10 has a built-in central processing unit power supply interlocking control unit 13. The central processing unit power supply interlocking control unit 13 includes the RL (CPU) control unit 30 and the R
L (CPU) 31. The RL (CPU)
The control unit 30 opens the RL (CPU) 31 when the internal power supply of the central processing unit 10 is in a cut-off state, and releases the R when the internal power supply of the central processing unit 10 is in an on state.
L (CPU) 31 is turned on. On the other hand, peripheral device 1
1 has a built-in peripheral device power supply interlocking control unit 14. The peripheral device power supply interlocking control unit 14 includes an RL (I / O) control unit 32 and an RL (I / O) 33. The RL (I / O) control unit 32 brings the RL (I / O) 33 into a conductive state when the peripheral device 11 is performing data processing, and
Is not processing data, RL (I / O) 33
To the open state. The power supply interlocking device 12 includes an RL control unit 34
And the cutting unit 16 having the RL 35. The RL control unit 34 controls the RL 35 according to the state of the OR signal line 22. That is, when the OR signal line 22 is in the ground fault state, the RL control unit 34 sets the RL 35
Is turned on and the OR signal line 22 is open,
The RL 35 is opened. The OR circuit 1 simply connects the power-off signal line 20, the signal line 21 indicating that the data processing is being performed, and the OR signal line 22, and thus a wired OR is realized.

Next, the operation when the first embodiment of the present invention is disassembled into a "circuit diagram" will be described with reference to FIG. When the built-in power supply of the central processing unit 10 is in the energized state, the RL (CPU) control unit 30 conducts the RL (CPU) 31, so that the power-off signal line 20 is in the ground fault state. The ground fault state of the power-off signal line 20 is RL (I / O)
Regardless of the state of 33, the power is transmitted to the power supply interlocking device 12 via the OR signal line 22, and the RL control unit 34 sets the RL 35 to the conductive state. As a result, power is supplied to the AC outlet 17 and the peripheral device AC Power is supplied to the peripheral device 11 via the cable 24. That is, when the internal power supply of the central processing unit 10 is in the energized state, power is supplied to the peripheral device 11.

When the internal power supply of the central processing unit 10 is turned off, the RL (CPU) control unit 30
U) Put 31 in the open state. On the other hand, when the peripheral device 11 is performing data processing, the peripheral device 11 outputs RL (I / I /
O) 33 becomes conductive and the signal line 21 indicating that the data processing is being performed is in a ground fault state, but when the peripheral device 11 is not performing data processing, the RL (I / O) 33 is in an open state and the The signal line 21 indicating that data processing is being performed is also opened. Therefore, when the RL (CPU) 31 is in the open state, the ground fault state of the signal line 21 indicating that the data processing is being performed is as follows.
The power is transmitted to the power supply interlocking device 12 via the OR signal line 22 and the RL control unit 34 sets the RL 35 to the conductive state. As a result, power is supplied to the AC outlet 17 and the peripheral device 11 is connected via the peripheral device AC cable 24. Is supplied with power. That is, even when the internal power supply of the central processing unit 10 is in the cut-off state, the power is continuously supplied to the peripheral device 11 that is performing data processing. On the other hand, when the RL (CPU) 31 is in an open state and the signal line 21 indicating that the data processing is being performed is also in an open state, the open state of both relays is changed via the OR signal line 22 to a power supply interlocking device. As a result, the power supplied to the AC outlet 17 is cut off and the power supplied to the peripheral device 11 is also cut off. That is, power is not supplied to the peripheral device 11 in which the internal power supply of the central processing unit 10 is in the cut-off state and is not processing data.

FIG. 3 is a block diagram showing a second embodiment of the present invention. The second embodiment of the present invention is a case where the OR circuit 1 that operates continuously even when the built-in power supply of the central processing unit 10 is cut off is built in the central processing unit 10.

FIG. 4 is a block diagram showing a third embodiment of the present invention. In the third embodiment of the present invention, the OR circuit 1 that operates continuously even when the internal power supply of the central processing unit 10 is in a cut-off state is built in the power supply interlocking device 12. Similarly, when the OR circuit 1 that operates continuously even when the internal power supply of the central processing unit 10 is cut off is built in the peripheral device 11, it can be easily analogized. Further, examples of the use of the multi-input OR circuit 1 and the multi-stage connection of the plurality of OR circuits 1 can be easily analogized.

[0029]

According to the present invention, in a computer system for controlling the power supply of peripheral devices using a conventional power supply interlocking device, the central processing unit itself controls the internal power supply of the central processing unit by processing such as shutdown. Even in the case of "emergency disconnection", the power supply to the peripheral device is not immediately cut off in synchronization with this, and the power is continuously supplied to the peripheral device that is processing the data. As a result, data destruction or loss that may occur on the peripheral device side can be prevented at low cost.

The reason is that the OR circuit that operates continuously even when the internal power supply of the central processing unit is in a cut-off state is such that when the internal power supply of the central processing unit is in a cut-off state, the central processing unit continues to operate for peripheral devices. By taking the logical OR of the "power-off instruction signal" issued when the peripheral device is processing data and the "signal indicating that data processing is in progress", and giving this as a power control signal to the power interlocking device, This is because it is possible to prevent the power supply interlocking device from accidentally cutting off the power supply to the peripheral device during the data processing of the device.

[Brief description of the drawings]

FIG. 1 is a diagram showing a first embodiment of a peripheral device power-off system according to the present invention.
FIG. 2 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a “circuit diagram” showing the peripheral device power-off system of FIG. 1;
1 is an example of an embodiment in the case of disassembling up to.

FIG. 3 shows a second embodiment of the peripheral device power-off system according to the present invention.
It is a block diagram showing an embodiment.

FIG. 4 shows a third embodiment of the peripheral device power-off system according to the present invention.
It is a block diagram showing an embodiment.

FIG. 5 is a block diagram showing an embodiment of a method of powering off a central processing unit to peripheral devices in a conventional information processing system.

FIG. 6 is a block diagram showing another embodiment of a power-off system from a central processing unit to peripheral devices in a conventional information processing system.

FIG. 7 is a block diagram showing still another embodiment of a power-off system from a central processing unit to peripheral devices in a conventional information processing system.

FIG. 8 is a block diagram showing an embodiment in which a countermeasure is taken to prevent accidental disconnection of power supply to a peripheral device during operation of the peripheral device with respect to FIG. 6;

FIG. 9 is a block diagram showing an embodiment in which a countermeasure is taken to prevent accidental disconnection of power supply to a peripheral device during operation of the peripheral device with respect to FIG. 7;

FIG. 10 is a block diagram showing an embodiment when a peripheral control device is introduced in a conventional information processing system.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 OR circuit 10 Central processing unit 11 Peripheral device 12 Power supply interlocking device 13 Central processing unit power supply interlocking control unit 14 Peripheral device power supply interlocking control unit 15 Analysis unit 16 Disconnecting unit 17 AC outlet 18 Built-in power supply 19 Power supply device 20 Power supply disconnection signal line 21 Signal line indicating that data is being processed 22 OR signal line 23 Central processing unit AC cable 24 Peripheral unit AC cable 25 Power supply interlocking unit AC cable 30 RL (CPU) control unit 31 RL (CPU) 32 RL (I / O) control Unit 33 RL (I / O) 34 RL control unit 35 RL 36 power switch 37 microcomputer 38 memory 39 DMA controller 40 NAND circuit 41 relay switch 42 monitoring control unit 43 peripheral control device 44 power control device 51 power control signal 52 data transfer Request signal

Claims (3)

[Claims] An internal power supply of a central processing unit is continuously operated even when the internal power supply is turned off, and when the internal power supply of the central processing unit is turned off, the central processing unit sends a signal to a peripheral device. A power-off instruction signal issued continuously,
A logical sum circuit for calculating a logical sum with a signal indicating that data processing is being performed from the peripheral device and inputting the logical sum to a power supply interlocking device. 2. A peripheral device power-off system, wherein the logical sum circuit according to claim 1 is incorporated in the central processing unit. 3. A power supply disconnection system for a peripheral device, wherein the logical sum circuit according to claim 1 is incorporated in the power supply interlocking device.