JPH10290002A - Charge transfer device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make signals in wider dynamic range at low power consumption. SOLUTION: A floating diffusion(FD) part 20-1 is formed adjacently to an output gate 11. Next, an output transfer gate 21-1 is formed adjacently to the FD part 20-1 and then FD part 20-2 is formed adjacently to the output transfer gate 21-1 . Likewise, FD parts 20-1 -20-d formed. Next, reset gates 22-1 -22-n are formed adjacently to the FD parts 20-1 -20-n , and then a reset drain 23 is formed adjacently to these gates. At this time, the gates 21-1 -21-(n-1) are set up at the potential between the potential of the FD parts 20-1 -20-n and the potential when the reset gates are not in the reset operational state. Next, when a specific amount of signal charge is accumulated in the FD part 20-1 , the FD part 20-2 is supplied with the signal charge through the intermediary of the gate 21-1 . At this time, an output signal in wider dynamic ranges are made according to the detected signals VS1 -VSn . In such a constitution, a signal is given to the gates 22-1 --n and then the signal charge of the FD 20-1 -20-n are reset at equal timing for making the frequency characteristics of the resetting operation excellent.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a charge transfer device. More specifically, the signal charge transferred by the charge transfer means is supplied to a plurality of charge detection means, and the detection signal is generated by the charge detection means based on the signal charge. An output signal having a wide dynamic range is obtained by using the detection signal. Also,
A reset means is provided for each of the charge detection means, and a reset signal is supplied to each of the reset means in synchronism with each other to reset the signal charges of the charge detection means at the same timing, thereby improving the frequency characteristics at the time of the reset operation. It shall be.

[0002]

2. Description of the Related Art A charge transfer device used as a charge transfer device of a CCD (Charge Coupled Device) solid-state image pickup device or a CCD delay device, for example, an FD (floating diffusion) type output unit as shown in FIG. In the charge transfer device, the output gate 11 is formed adjacent to the last storage gate of the charge transfer unit 10 for transferring the signal charge according to the amount of incident light, and the FD unit 12 is adjacent to the output gate 11. Are formed. The FD section 12 is connected to an amplifier (not shown) formed on the same chip. The amplifier generates an output signal based on a detection signal Vs corresponding to the signal charge of the FD section 12. Also F
A reset gate 13 is formed adjacent to the D portion 12, and a reset drain 14 is formed adjacent to the reset gate 13. The transfer clock signals φ1 and φ2 are supplied to the charge transfer section 10, and the reset pulse signal φr is supplied to the reset gate 13.
The output gate 11 is supplied with the gate voltage Vog, and the reset drain 14 is supplied with the drain voltage Vdr.

FIG. 9 is a diagram showing a potential distribution on the line AA 'shown in FIG. 8. The charge transfer section 10 is driven in two phases based on transfer clock signals φ1 and φ2, and signal charges are sequentially transferred. Will be transferred. Here, the signal charges stored in the last-stage storage unit of the charge transfer unit 10 are supplied to the FD unit 12 via the output gate 11. Also, the reset gate 13
Is supplied with a reset pulse signal φr, and the reset gate 13 is periodically opened by the reset pulse signal φr, and the signal charges supplied to the FD section 12 are swept out to the reset drain 14 to perform the reset operation. Done. Note that, in FIG. 9 and the drawings described later, the hatched portions indicate states in which signal charges are stored.

[0004]

By the way, in such a charge transfer device, the power consumption is reduced by lowering the power supply voltage supplied to the charge transfer device. Assuming that the amplitude of the reset gate 13 driven by
As shown in (1), the signal charge that can be stored in the FD section 12 decreases, and when the signal charge is large, the signal charge overflows to the reset drain 14 via the reset gate 13. Thus, the signal charge that can be stored in the FD unit 12 is reduced by reducing the amplitude of the reset gate 13, and the dynamic range of the output signal is reduced.

Accordingly, the present invention provides a charge transfer device which consumes less power and can obtain an output signal having a wide dynamic range.

[0006]

A charge transfer device according to the present invention comprises: charge transfer means for transferring a signal charge; and a plurality of charge detection means for generating a detection signal based on the signal charge from the charge transfer means. Reset means for resetting the signal charges of the plurality of charge detection means at a predetermined cycle, and charge supply means for supplying signal charges from the first charge detection means to the second charge detection means of the plurality of charge detection means. Have

In the present invention, the charge detecting means for generating a detection signal based on the signal charge transferred from the charge transferring means is cascaded via the charge supplying means,
For example, reset means is formed adjacent to each of the charge detection means in a direction orthogonal to the cascade connection direction of the charge detection means.

The signal charge from the charge transfer means is supplied to the charge detection means at one end of a plurality of cascade-connected charge detection means. Here, the charge supply means is set to a potential between the potential of the charge detection means and the potential when the reset means is not in the reset operation state. In the charge detection means, the signal charge is reduced to the potential of the charge supply means. Stored
More signal charges are stored in the adjacent charge detection means via the charge supply means. When a predetermined signal charge is stored in the adjacent charge detection means, the signal charge is stored in the next charge detection means. Similarly, the signal charges are sequentially filled from the charge detecting means at one end to the other charge detecting means.

A reset signal for resetting the signal charge of the charge detecting means at a predetermined cycle is synchronously supplied to each of the reset means formed adjacent to the plurality of charge detecting means. The signal charges of the detecting means are reset at the same timing based on the reset signal.

[0010]

Next, an embodiment of a charge transfer device according to the present invention will be described with reference to the drawings.

In FIG. 1, a charge transfer section 10 serving as a charge transfer means is configured by alternately arranging transfer gates 10-t and storage gates 10-s. The charge transfer unit 10 is driven in two phases by transfer clocks φ1 and φ2.

The final stage storage gate 10 of the charge transfer unit 10
-se, the output gate 11 is configured adjacently,
An FD portion 20-1 is formed adjacent to the output gate 11. The output transfer gate 21-1 is adjacent to the FD section 20-1.
FD is formed adjacent to the output transfer gate 21-1.
The part 20-2 is formed. Similarly, a plurality of FD units 20-1 to 20-n serving as charge detection units and output transfer gates 21-1 to 21- (n-1) serving as charge supply units are alternately arranged. Cascaded via output transfer gate.
Further, reset gates 22-1 to 22-n, which are reset means, are formed adjacent to each FD section in a direction orthogonal to the arrangement direction of the FD section and the output transfer gate.
Further, a reset drain 23 is formed adjacent to each of the reset gates 22-1 to 22-n.

An amplifier (not shown) formed on the same chip is connected to the FD units 20-1 to 20-n. In this amplifier, the FD units 20-1 to 20-n convert signal charges into signal charges. An output signal is generated based on detection signals Vs1 to Vsn generated accordingly. The transfer clock signal φ1,
φ2 is supplied. A reset pulse signal φr is supplied to the reset gates 22-1 to 22-n. Output gate 11
Is supplied with a gate voltage Vog, and the reset drain 14 is supplied with a drain voltage Vdr. The output transfer gates 21-1 to 21- (n-1) have a gate voltage Vogt.
Is supplied.

FIG. 2 is a schematic sectional view taken along the line BB 'in FIG. In the charge transfer unit 10, N ^- diffusion regions and N diffusion regions are alternately formed in one direction on the surface side of the silicon substrate, and a pair of gate electrodes is arranged on each diffusion region to form a transfer gate 10-. t and storage gate 10-s
Is formed. Storage gate 1 at the last stage of charge transfer unit 10
An N ^- diffusion region is formed adjacent to 0-se, and a gate electrode is arranged on the diffusion region to form output gate 11. An FD section 20-1 composed of an N ⁺ diffusion region is provided at the output gate.
Are formed adjacent to each other. Further, an N diffusion region is formed adjacent to the FD portion 20-1, and a gate electrode is arranged on the diffusion region to form an output transfer gate 21-1. An FD portion 20-2 formed of an N ⁺ diffusion region is formed adjacent to the output transfer gate 21-1, and the output transfer gate and the FD portion are alternately formed in the same manner.

Next, FIG. 3 is a schematic cross-sectional view taken along a line CC ′ in FIG. 1 which is a direction orthogonal to the arrangement direction of the FD section and the output transfer gate. In FIG. 3, an N diffusion region is formed adjacent to the FD portion 20-2, and a gate electrode is disposed thereon to form a reset gate 22-2. A reset drain 23 composed of an N ⁺ diffusion region is formed adjacent to the reset gate.

FIG. 4 is a diagram showing the potential distribution along the line BB 'shown in FIG. 1, and FIG. 5 is a diagram showing the potential distribution along the line CC' shown in FIG.
It is the figure which showed the potential distribution by the line in three dimensions. As shown in FIG. 4, the charge transfer unit 10 transmits a transfer clock signal φ
The signal charges are sequentially transferred by two-phase driving based on 1, φ2. The signal charge stored in the last-stage storage gate 10-se is supplied to the FD section 20-1 via the output gate 11.

A gate voltage Votg is applied to the gate electrodes of the output transfer gates 21-1 to 21- (n-1), and the potential of the output transfer gates 21-1 to 21- (n-1) is As shown in FIG. 5, the potentials between the potentials (potentials) when the reset gates 22-1 to 22-n are not reset by the reset signal φr and the potentials of the FD units 20-1 to 20-n are set. I have. The potential when the reset gates 22-1 to 22-n are reset by the reset signal φr is higher than the potentials of the FD units 20-1 to 20-n. Further, the potential of the reset drain 23 is set higher than the reset gates 22-1 to 22-n by the drain voltage Vdr. The potentials of the output transfer gates 21-1 to 21- (n-1) may be set by controlling the amount of impurity implanted into the N diffusion region of the output transfer gate.

Next, the operation will be described. The signal charge is supplied to the FD section 20-1 via the output gate 11. Here, the potential of the reset gates 22-1 to 22-n and the potential of the FD units 20-1 to 20-n when the potentials of the output transfer gates 21-1 to 21- (n-1) are not in the reset state are determined. Since the potential is set to be between the potentials, when the signal charge supplied to the FD unit 20-1 increases, the signal charge overflows as shown in FIG. 4 and passes through the output transfer gate 21-1. 20-2. When a predetermined amount of signal charge is supplied to the FD section 20-2, the signal charge exceeding this amount is output to the output transfer gate 21-2.
Is supplied to the FD section 20-3 via the. Similarly, when the charge amount of the signal charge is large, the signal charge is sequentially supplied from the FD unit 20-1 to the FD unit 20-n and stored.
FIG. 6 shows the potential distribution along the line CC ′ in FIG. 1 at this time.

Next, when a reset operation is performed by the reset signal φr supplied to the reset gates 22-1 to 22-n, the potentials of the reset gates 22-1 to 22-n are increased, and for example, as shown in FIG. As shown in FIG. 7, the signal charge of the FD section 20-2 is swept out to the reset drain 23 via the reset gate 22-2 to be reset. Similarly FD
The signal charges of the section 20-1 and the FD sections 20-3 to 20-n are also discharged to the reset drain 23 via the reset gate 22-1 and the FD sections 20-3 to 20-n and reset at the same timing. You.

For this reason, the reset gates 22-1 to 22-n
Of the output transfer gates 21-1 to 21-1
Since signal charges are sequentially stored in the plurality of FD units 20-1 to 20-n separated by 21- (n-1), the FD units 20-1 to 20-n
From an amplifier (not shown) connected to the gate electrode of
An output signal with a wide dynamic range can be obtained based on the detection signals Vs1 to Vsn generated according to the signal charges of the FD units 20-1 to 20-n.

Even if a large amount of signal charges are stored by the FD units 20-1 to 20-n, the FD units 20-1 to 20-n
Since the reset gates 22-1 to 22-n are formed adjacent to each part of -n, during the reset operation, the supplied signal charges are quickly swept out to the reset drain via the reset gate to be reset. Therefore, good frequency characteristics can be obtained. Therefore, for example, the FD portion is formed long to store a large amount of signal charges, and a reset gate is provided on the short side of the FD portion to sweep out the signal charges. As a result, the width of the reset gate is narrow, so that it takes time to sweep out the signal charges and the frequency characteristics do not deteriorate.

Thus, according to the above-described embodiment,
Even if the power consumption is reduced by reducing the amplitude of the reset gate, signal charges can be stored by a plurality of FD sections. Therefore, an output signal having a wide dynamic range can be obtained based on detection signals from the plurality of FD sections. Obtainable. Further, since the reset gate is formed adjacent to each of the plurality of FD sections, the stored signal charges are quickly swept out to the reset drain via the reset gate, and a good frequency characteristic can be obtained during the reset operation. Obtainable.

In the above embodiment, a plurality of FDs
Although the sections are cascaded in a straight line, the arrangement of the plurality of FD sections is not limited to a straight line.

[0024]

According to the present invention, the signal charges transferred from the charge transfer means are stored in the plurality of charge detection means,
A detection signal based on the stored signal charge is generated from each charge detection unit. Further, the reset means is connected to the plurality of charge detection means, and the signal charges stored in the respective charge detection means are reset at the same timing.

Therefore, even if the reset gate is reduced in amplitude and the power consumption is reduced, an output signal with a wide dynamic range can be obtained by using the detection signals obtained by the respective charge detection means. Further, since the signal charges of the charge detecting means are reset quickly at the same timing, the frequency characteristics during the reset operation can be improved.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a charge transfer device according to the present invention.

FIG. 2 is a schematic sectional view taken along line B-B '.

FIG. 3 is a schematic sectional view taken along line C-C '.

FIG. 4 is a diagram showing a potential distribution along a line BB ′.

FIG. 5 is a diagram showing a potential distribution along a line CC ′.

FIG. 6 is a diagram showing a potential distribution before a reset operation.

FIG. 7 is a diagram showing a potential distribution during a reset operation.

FIG. 8 is a diagram showing a configuration of a conventional charge transfer device.

FIG. 9 is a diagram showing a potential distribution along line AA ′.

FIG. 10 is a diagram showing a potential distribution when the amplitude of the reset gate is reduced.

[Explanation of symbols]

10 ... Charge transfer unit, 11 ... Output gate, 12,
20-1 to 20-n ... FD section, 13, 22-1 to 22-n
..Reset gates, 14, 23 ... reset drains, 21-1 to 21-n ... output transfer gates

Claims (5)

[Claims] A charge transfer means for transferring a signal charge; a plurality of charge detection means for generating a detection signal based on the signal charge from the charge transfer means; and a signal charge for the plurality of charge detection means. Reset means for resetting at a cycle of the first charge detecting means;
And a charge supply unit for supplying a signal charge to the charge detection unit. 2. The method according to claim 1, wherein the reset unit is provided in each of the plurality of charge detection units. A reset signal for resetting a signal charge of the charge detection unit at a predetermined cycle is synchronized with the plurality of reset units. 2. The charge transfer device according to claim 1, wherein the charge is supplied. 3. The charge transfer device according to claim 1, wherein said charge supply means sets a potential between a potential of said charge detection means and a potential when said reset means is not in a reset operation state. . 4. A cascade connection of the plurality of charge detection means via the charge supply means, a signal charge from the charge transfer means being supplied to one end of the charge detection means, and 2. The charge transfer device according to claim 1, wherein when a signal charge exceeding a predetermined amount is supplied, the signal charge exceeding the predetermined amount is supplied to an adjacent charge detection unit via the charge transfer unit. 5. The charge transfer device according to claim 4, wherein said reset means is formed in a direction orthogonal to a cascade connection direction of said plurality of charge detection means.