JPH10289966A - Flip chip semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To ensure a transmission line of required impedance independent of the position of a conductor wiring pattern by a method wherein a dielectric layer is formed on the surface of a semiconductor chip which includes a first conductor layer, and a bump conductor is formed on a second conductor layer on the dielectric layer and electrically connected to a grounding conductor formed on a mounting board. SOLUTION: A wiring pattern formed of a first conductor layer 2 is provided onto the surface of a semiconductor chip 1, and a dielectric layer 3 is formed on the surface of the semiconductor chip 1 which includes the wiring pattern. A second conductor layer 4 is formed on the dielectric layer 3 on the first conductor layer 2 at a required point, and a grounding conductor bump 5 is formed on the second conductor layer 4. The semiconductor chip 1 is mounted on a mounting board 6 or a package with silver paste through a flip-chip mounting method. When the grounding conductor bump 5 is connected to a grounding pattern 7 located on the mounting board 6, a microstrip transmission line composed of the conductor layer 2, the dielectric layer 3, and the second conductor layer 4 is formed making the second conductor layer 4 serve as a grounding conductor.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flip-chip mounted semiconductor device, and more particularly, to miniaturization of a semiconductor chip.
Also, the present invention relates to a flip-chip type semiconductor device which is suitable in terms of high-frequency operation stability.

[0002]

2. Description of the Related Art As a conventional flip-chip type semiconductor device, for example, Japanese Patent Application Laid-Open No. Sho 61-53748 discloses that a matching circuit can be reduced in size by eliminating a through-hole and easily without causing a wafer crack. For the purpose of enabling measurement of high-frequency characteristics in a wafer state, an ultra-high frequency semiconductor device as shown in FIG. 6 has been proposed. FIG.
6A is a plan view of the microwave monolithic integrated circuit device, and FIG. 6B is a cross-sectional view taken along a line AA ′ of a matching circuit formed by the microstrip line in FIG.

Referring to FIG. 6B, a first metallization layer 1 formed on one main surface of a semi-insulating gallium arsenide substrate 101 is formed.
03, a dielectric layer 102 formed thereon, and a second-layer metallization layer 105 further formed thereon are mounted in a flip-chip type with a first-layer metallization layer 105. 103 is a container ground conductor 108 on the semiconductor mounting surface.
Are connected by a ground plane connection electrode 104. With this configuration, the second metallization layer 105 is connected to the center conductor,
A microstrip transmission line using the metallization layer 103 as a ground conductor is formed.

As another conventional technique of a flip-chip type semiconductor device, for example, Japanese Patent Application Laid-Open No. 2-122640 discloses a structure in which a semiconductor chip is mounted face down on a circuit board. For the purpose of providing a good semiconductor chip mounting structure, a configuration as shown in FIG. 8 has been proposed.

Referring to FIG. 8, a semiconductor chip 201 has a signal pad 221 formed on one main surface thereof and a ground pad 222 formed so as to surround the signal pad 221.
A circuit board 205 on which a semiconductor chip is mounted in a flip-chip type has an earth layer 210 and an earth layer bump 23.
2 is connected to the ground pad 222 of the semiconductor chip. With this configuration, the heat radiation of the semiconductor chip is improved and the signal leakage between the signal lines is prevented.

For example, Japanese Unexamined Patent Application Publication No. 7-183708 discloses a high-frequency semiconductor device shown in FIG. 9 for the purpose of increasing design flexibility, facilitating adjustment of the coupling degree of a distributed coupling line, and providing a low-loss high-frequency semiconductor device. Such a configuration has been proposed.

Referring to FIG. 9, a microstrip transmission line including first center conductor 303, first dielectric 302 and first ground conductor 301 is connected to second center conductor 30.
4, another microstrip transmission line composed of the first dielectric film 306 and the second ground conductor 305, and fixed by a bump 307 in a direction in which the center conductors face each other, and the microstrip transmission lines The degree of coupling between the lines can be adjusted according to the positional relationship between the lines.

Japanese Patent Application Laid-Open No. Sho 62-171201 discloses a package capable of supplying a stable power supply voltage even in a high frequency range by forming a power supply line having a low characteristic impedance. The following configuration has been proposed. FIG. 10 (a), FIG.
10B is a schematic diagram, FIG. 10C is a plan view, and FIG.
(D) and FIG. 10 (e) are side views.

Referring to FIG. 10, this package has a power supply line using a balanced strip line or a shielded coplanar line. Alternatively, a shielded coplanar line is formed to prevent the influence of coupling from the peripheral line with low impedance. In FIG. 10, reference numeral 401 denotes a package substrate;
Is a dielectric layer, 405 is a semiconductor element, 406 is an input signal line, 407 is an output signal line, and 408 is a bonding wire.

[0010]

However, each of the above-described prior arts has various problems as described below.

(1) In the semiconductor device described in JP-A-61-53748, as shown in FIG. 7A, a flat substrate semiconductor chip is mounted on a mounting surface.
When another wiring pattern having a relatively low impedance (indicated by a mounting substrate wiring layer 111 in the drawing) exists, the second layer metallization is performed due to the positional relationship between the second metallization layer 105 and the mounting substrate wiring layer 111. A disadvantage arises in that the impedance of the microstrip line transmission line including the layer 105, the dielectric layer 102, and the first metallized phase 103 varies or varies.

The reason is that the capacitance is formed between the second metallization layer 105 and the wiring layer 111 of the mounting substrate, and accordingly, the impedance of the transmission line is reduced accordingly. FIG. 7C is a diagram schematically illustrating that the impedance of the transmission line is reduced.

(2) Next, the above-mentioned Japanese Patent Application Laid-Open No. 2-1226 is described.
The mounting structure of the semiconductor chip described in Japanese Patent Publication No. 40 has a problem that the chip area of the semiconductor chip becomes unnecessarily large.

The reason is that, as shown in FIG. 8, in the semiconductor chip, a grid is assumed at a predetermined pitch on the surface, a desired intersection is selected from the intersection matrix, and signal pads 221 are arranged. So as to surround the signal pad 221,
Grounding pad 2 at the intersection of the front, rear, left and right grids on the same plane
This is because 22 is provided.

(3) Next, the above-mentioned JP-A-7-1837
The problem of JP 08 is that it is not easy to ensure the reproducibility of the coupling degree between two opposing microstrip transmission lines when the described semiconductor device is mass-produced, for example.

The reason is that the second center conductor 304 and the first
This is because it is difficult to secure positional accuracy on the order of microns because a microstrip transmission line including the dielectric film 306 and the second ground conductor 305 is mounted later by a flip chip method.

(4) The above-mentioned JP-A-62-17
Japanese Patent Application Laid-Open No. 1201 discloses a configuration of a package. In order to secure the ground potential of the ground potential conductor layers 402 ′ and 402 ″, for example, FIGS.
As shown in FIG. 11B, a layer that actually secures a ground potential with the outside by using a through hole (FIGS. 11A and 11B)
In this case, electrical conduction is provided to the uppermost ground potential conductor 402), or side metallization is performed at the periphery of the package as shown in FIGS. 11 (c) and 11 (d).

When this package is used for a semiconductor chip, in the case of the connection shown in FIGS.
09, there is a disadvantage that the area of the semiconductor chip becomes large.

In the case of the connection shown in FIGS. 11C and 11D, it is necessary to extend at least a part of the uppermost ground potential conductor 402 to the periphery of the semiconductor chip. There is a disadvantage that the wiring is restricted.

Therefore, the present invention has been made in view of the above problems, and has as its object to reduce the impedance of a transmission line formed on a semiconductor chip when the semiconductor chip is mounted in a flip-chip manner. It is an object of the present invention to provide a flip-chip type semiconductor device capable of securing a desired value irrespective of the pattern position of the conductor wiring on the mounting surface.

Another object of the present invention is to provide a flip-chip type semiconductor device which reduces the chip area of the semiconductor chip.

[0022]

In order to achieve the above object, a flip chip type semiconductor device according to the present invention comprises a first conductive layer formed on a front surface (front surface) of a semiconductor chip; A dielectric layer formed on the front side of the semiconductor chip, a second conductor layer formed on the dielectric layer, and at least one bump conductor formed on the second conductor layer. A semiconductor chip is mounted on a mounting substrate in a flip-chip manner, and the bump conductor is connected to a ground conductor formed on the mounting substrate by an electrical connection means.

Further, in the present invention, the first conductor layer is used as a center conductor, the second conductor layer is used as a ground conductor, and a microstrip transmission line having a desired characteristic impedance is formed. Features.

Also, in the present invention, the first conductor layer is a spiral type or a meander type inductance circuit, and the inductance component (L) of the inductance circuit and the inductance circuit are the second component.
And a capacitance component (C) of capacitance formed between the conductive layer and the conductive layer.

[Summary of the Invention] The principle and operation of the present invention will be described below. In the present invention, a first conductor layer (2 in FIG. 1) formed on a semiconductor chip, a dielectric layer (3 in FIG. 1) formed on the first conductor layer, and the dielectric layer Having a second conductor layer (4 in FIG. 1) formed on
A microstrip transmission line having a first conductor layer as a center conductor and a second conductor layer as a ground conductor is formed (FIG. 1).
(C)).

The second conductor layer is connected to another grounding conductor layer on the dielectric layer, or is directly connected to the ground potential conductor layer on the mounting board through a bump. That is, the second conductor layer does not need to be independently connected to the lower electrode of the semiconductor chip through the through hole.

In the flip-chip type semiconductor device according to the present invention, the second conductor layer is grounded by the first conductor layer, the dielectric layer formed thereon, and the second conductor layer formed thereon. A microstrip transmission line having a conductor and a first conductor layer as a central conductor is formed, and the impedance of the transmission line due to the influence of other wiring patterns on the semiconductor chip mounting surface due to the shield effect of the second conductor layer. Fluctuations and variations can be prevented.

Since the second conductor layer in the flip-chip type semiconductor device of the present invention is directly connected to the ground potential conductor layer on the mounting substrate through the bump, it functions as the ground conductor of the microstrip transmission line. Since the conductor layer and the lower layer (the lower layer in the semiconductor chip) do not need to be provided with an electrical connection means such as a through hole, an increase in the chip area involved in forming the through hole can be reduced.

[0029]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a diagram showing a configuration of an embodiment of the present invention. FIG. 1 (a) is a plan view, and FIG.
FIG. 1A is a cross-sectional view taken along the line AA ′, and FIG. 1C is a diagram illustrating a cross-section when mounted on a mounting board.

Referring to FIG. 1, in this embodiment, a wiring pattern of a first conductor layer 2 is formed on a front surface of a semiconductor chip 1. A dielectric layer 3 is formed on the front surface of the semiconductor chip 1 including the wiring pattern. A second conductor layer 4 is formed at a desired position on the dielectric layer 3 on the first conductor layer 2. On the second conductor layer 4, a ground bump 5 made of a conductor is formed.

In this embodiment, the second conductor layer 4
It is not electrically connected to a lower wiring layer (semiconductor chip side) by a through hole or the like.

The semiconductor chip having the above configuration is mounted on a mounting substrate 6 or a package or the like by a flip chip method using silver paste 8 or the like (see FIG. 1C).

When the grounding bump 5 is connected to the grounding pattern 7 on the mounting substrate 6, the first conductor layer 2, the dielectric layer 3, and the second conductor layer 4 are centered on the first conductor layer 2. A microstrip transmission line having a conductor and the second conductor layer 4 as a ground conductor is formed.

If the width W 'of the second conductor layer 4 is sufficiently large (usually about three times W) with respect to the width W of the first conductor layer 2, the characteristics of the microstrip type ground transmission line can be obtained. The impedance Z _o is determined by the width W of the first conductor layer 2, the thickness (distance between the first conductor layer and the second conductor layer) H of the dielectric layer 3, and the relative dielectric constant ε _r .

[0036]

(Equation 1)

Here,

(Equation 2)

Here, ε _eff is called “effective permittivity”.

In this embodiment, a microstrip transmission line having a desired characteristic impedance is formed at a desired position on a semiconductor chip by using these relational expressions.

[0040]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to more specifically describe the above-described embodiment of the present invention, an embodiment of the present invention will be described with reference to the drawings.

[First Embodiment] FIG. 2 is a view showing the structure of a first embodiment of the present invention.
Two FET sections Q1 and Q2, a bias circuit section 20 and a matching circuit section 21 are formed, and a part of the matching circuit section 21 is formed by a wiring layer formed of a first conductor layer 2 as shown in FIG. Contains.

The width W of the first conductor layer 2 is patterned at about 55 μm. The GaAs including the first conductor layer 2
A polyimide layer 23 (ε _r ≒ 4.7) having a thickness of about 30 μm is formed on the surface of the s substrate 22.
A second conductor layer 4 is further formed on the desired portion of the polyimide layer. The second conductor layer 4 includes A
A ground bump 5 having a diameter of about 100 μm made of a u material is formed.

FIG. 3 shows a semiconductor chip (FIG. 2) of this embodiment.
2 (a) and FIG. 2 (b)) are sectional views showing the manufacturing steps in the order of the steps.

An FET portion 32 is formed on a GaAs substrate by using an existing ion implantation technique, and a first insulating film 33 such as SiO ₂ is formed thereon by an existing CVD method (FIG. 3).
(A)).

Next, a necessary portion of the first insulating film 33 is opened by a known etching technique, and a Schottky metal 34 and an ohmic metal 35 are formed by a known sputtering technique and a vapor deposition technique (FIG. 3B). )reference). On this occasion,
The Schottky metal for wiring 34 'may be formed on the first insulating film which does not open the window.

Further, S is further formed by an existing CVD method.
A _second insulating film 36 made of iO ₂ or the like is formed, and the first through hole 3 is formed at a necessary portion by an existing dry etching technique.
7 is provided, and a first contact wiring is performed on the Schottky metals 34 and 34 ′ and the ohmic metal 35 at desired locations in the lower layer. A first conductor layer 38 and another conductor layer (1) 39 are formed on the semiconductor chip thus configured by A.
It is formed by existing wiring technology such as u plating technology (FIG. 3
(C)).

A polyimide layer 40 is formed thereon by a known film forming technique, a window is formed in a desired portion by using an etching technique, and a second through hole 41 is formed in a desired gold-plated wiring layer below. To form

Further, the second conductor layer 42 and the other conductor layer (2) 43 are formed by a known Au plating wiring technique, and the Au ground bumps 44 and the other bumps 4 are formed at desired locations.
5 is formed by an existing bump forming technique (see FIG. 3D).

Finally, the semiconductor chip is cut out by dicing.

The mounting board mounted on the mounting board on the semiconductor chip 71 manufactured as described above by using the silver paste 8 by the flip chip method has a ground pattern 7 at a desired position.
3 and another conductor layer (3) 74 are formed, and by this mounting, the second conductor layer 4 is electrically maintained at the ground potential as a ground wiring metal. As a mounting agent for mounting the semiconductor chip 71 on the mounting substrate 72, a solder or other solder material may be used instead of the Ag paste.

The operation and effect of the semiconductor device according to the embodiment of the present invention configured as described above will be described. The first conductor layer 2, the dielectric layer (polyimide layer) 23, and the second conductor layer 4 are microstrip transmission lines having the first conductor layer 2 as a central conductor and the second conductor layer 4 as a ground conductor. Is formed. In this embodiment, the first conductor layer width, the dielectric material, and the thickness are set so that the characteristic impedance of the microstrip transmission line is about 50Ω.
Due to the shield effect of the second conductor layer 4, the first conductor layer is less likely to cause impedance variation due to the presence of another wiring pattern on the mounting board 72.

[Second Embodiment] FIG. 4 is a diagram showing a configuration of a flip chip type semiconductor device according to a second embodiment of the present invention. The basic structure and manufacturing method of this embodiment are the same as those of the first embodiment.

In this embodiment, the spiral-type inductance element 50 is formed by the first conductor layer 2, the dielectric layer 3 is formed thereon, and the second conductor layer 4 is further formed. As described above, the second conductor layer 4 is set to the ground potential by flip-chip mounting, so that the spiral inductance element 50 and the capacitance between the grounds (the capacitance between the first conductor layer and the second conductor layer) are formed. It resonates and is used for a semiconductor circuit.

Referring to FIG. 4, the conductor width of the spiral type inductance element (5 turns): P is 10 μm, the gap width: q is 10 μm, and the first conductor layer and the second conductor layer are H: 10 μm. (Dielectric layer is polyimide)
The resonance frequency f _o is as the following equation (4).

[0055]

(Equation 3)

C is the speed of light and ε _eff is the effective dielectric constant, see equation (2) above.

[Third Embodiment] FIG. 5 is a diagram showing a configuration of a flip-chip type semiconductor device according to a third embodiment of the present invention. 5A is a plan view, FIG. 5B is a cross-sectional view taken along line DD ′ of FIG. 5A, and FIG. 5C is a plan view showing a mounted state. The basic structure of this embodiment is the same as that of the first embodiment, but in this embodiment, in addition to the first conductor layer 2 on the semiconductor chip 1, the third structure formed on the semiconductor chip A first dielectric layer formed on the conductive layer; a first dielectric layer formed on the second dielectric layer through the third conductive layer;
The capacitor element is formed facing the conductive layer of FIG.

In FIG. 5, the second dielectric layer 61 is made of Si
It is an N film and has a thickness of about 200 nm. The third conductor layer 60 is electrically connected to the second conductor layer 4 through the through hole 62. This is unique to the third embodiment.

The second conductor layer 4 is divided (4, 4 ', 4 ", 4"') as shown in FIG.

The purpose of this embodiment is to use the capacitance between the second conductor layer 4 and the first conductor layer 2 for adjusting the capacitance of the circuit. 4 ', 4'',
4 ″ ′) can be connected as desired by the bonding wire 63 (see FIG. 5C), so that the capacitance of the capacitance circuit can be adjusted.

[0061]

As described above, according to the present invention, the following effects can be obtained.

(1) The first effect of the present invention is that the impedance of the transmission line formed on the semiconductor chip is affected by the wiring pattern present on the mounting substrate when the semiconductor chip is mounted by the flip chip method. Change can be reduced.

The reason is that, in the present invention, the ground conductor (second conductor layer) constituting the transmission line can be formed on the surface in contact with the flip-chip mounting surface. This is because electric field leakage can be reduced.

(2) A second effect of the present invention is that in a flip-chip type semiconductor device, the chip area of a semiconductor chip can be reduced and the mounting area can be reduced.

The reason is that, in the present invention, since the ground conductor of the transmission line formed on the semiconductor chip is directly connected to the mounting board, it is unnecessary to form an extra through hole on the chip.

(3) A third effect of the present invention is that the reproducibility of the coupling (impedance) of the transmission line formed on the semiconductor chip is good.

The reason for this is that, in the present invention, since the transmission line structure is manufactured by a semiconductor process, the transmission line structure has a micron (μm).
m) The dimension of the order can be controlled.

[Brief description of the drawings]

FIGS. 1A and 1B are diagrams showing an embodiment of the present invention, wherein FIG. 1A is a plan view, FIG. 1B is a cross-sectional view taken along line AA ′ of FIG. 1A, and FIG.

FIG. 2 is a diagram showing a first embodiment of the present invention, wherein (a)
Is a plan view, (b) is a sectional view taken along the line BB 'of (a), (c)
Is a sectional view at the time of mounting.

FIG. 3 is a cross-sectional view showing a manufacturing step of the semiconductor chip in the first embodiment of the present invention in the order of steps.

FIG. 4 is a view showing a second embodiment of the present invention, and (a).
FIG. 2B is a plan view, FIG. 2B is a cross-sectional view at the time of mounting, and FIG. 1C is a view showing a spiral inductance element.

FIG. 5 is a diagram showing a configuration of a third embodiment of the present invention;
(A) is a plan view, (b) is a sectional view taken along line DD ′ of (a),
(C) is a plan view showing a mounted state.

FIG. 6 is a diagram showing a semiconductor device according to a conventional technique (Japanese Patent Application Laid-Open No. 61-53748).

FIG. 7 is an explanatory view schematically showing a problem of the semiconductor device described in JP-A-61-53748.

FIG. 8 is a diagram showing a configuration of a semiconductor device of a conventional technique (Japanese Patent Laid-Open No. 2-122640).

FIG. 9 is a diagram showing a configuration of a semiconductor device of another conventional technique (Japanese Patent Laid-Open No. 7-183708).

FIG. 10 shows another conventional technique (Japanese Patent Laid-Open No. 62-1712).
FIG. 1 is a diagram showing a configuration of a package of Japanese Patent Publication No.

FIG. 11 is a diagram for explaining a problem of the package described in Japanese Patent Application Laid-Open No. 62-171201.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 semiconductor chip 2 first conductor layer 3 dielectric layer 4 second conductor layer 5 ground bump 6 mounting board 7 ground pattern 8 silver paste 9 other conductor layer (2) 10 through hole 11 other conductor layer (1) 12) Other bumps 13 Other conductor layers (3) Q1, Q2 FET section 20 Bias circuit section 21 Matching circuit section 22 GaAs substrate 23 Polyimide layer 31 GaAs substrate 32 FET section 33 First insulating film 34, 34 'Schottky Metal 35 Ohmic metal 36 Second insulating film 37 First through hole 38 First conductor layer 39 Other conductor layer (1) 40 Polyimide layer 41 Second through hole 42 Second conductor layer 43 Other conductor layer (2) 44 Grounding bump 45 Other bumps 50 Spiral inductance element 51 Through hole 52 Lower layer wiring conductor 60 Conductor layer 61 second dielectric layer 62 through hole 63 bonding wire 71 semiconductor chip 72 mounting substrate 73 ground pattern 74 other conductor layer (3) 101 semi-insulating gallium arsenide substrate 102 dielectric layer 103 first layer metal Layer 104 ground plane connection electrode 105 microstrip line 106, 107 through-hole contact 108 container ground conductor 109 container input / output transmission line 110 container insulator substrate 111 mounting substrate wiring layer 201 semiconductor chip 202 pad 203 bump 205 circuit substrate 206 conductor Pattern 210 ground layer 211 dielectric pattern 212 signal line pattern 221 signal pad 222 ground pad 231 signal bump 232 ground bump 301 first ground conductor 302 first dielectric 303 first center conductor 304 Second central conductor 305 Second ground conductor 306 First dielectric film 307 Bump 401 Package substrate 402 Ground potential conductor 403 Dielectric layer 404 Power supply conductor 405 Semiconductor element 406 Input signal line 407 Output signal line 408 Bonding Wire 409 Through hole 410 Side metallization

Claims (4)

[Claims] 1. A first conductor layer formed on a front surface (front surface) of a semiconductor chip, a dielectric layer formed on a front surface of the semiconductor chip including the first conductor layer, and on the dielectric layer A semiconductor chip comprising: a second conductor layer formed on the second conductor layer; and at least one bump conductor formed on the second conductor layer. A flip-chip type semiconductor device, wherein the flip-chip type semiconductor device is connected to a ground conductor formed on a mounting board by an electrical connection means. 2. A microstrip transmission line having a desired characteristic impedance is formed by using the first conductor layer as a center conductor and the second conductor layer as a ground conductor.
The flip-chip type semiconductor device according to claim 1, wherein: 3. The method according to claim 1, wherein the first conductor layer is a spiral or a mounder type inductance circuit, and an inductance component (L) of the inductance circuit and the inductance circuit are connected to the second conductor layer. 2. The flip-chip type semiconductor device according to claim 1, wherein a resonance circuit is formed between the capacitance component and a capacitance component (C) of the capacitance formed in the semiconductor device. 4. A capacitance circuit in which the first conductor layer forms a parallel-plate capacitance with a third conductor layer, which is another conductor layer, wherein the first conductor layer forms a parallel plate capacitance. The surface facing the capacitance circuit is divided into at least two or more pieces, and a desired number of second conductor layers among the plurality of divided second conductor layers are electrically connected. 2. The flip-chip type semiconductor device according to claim 1, wherein the capacitance of the capacitance circuit can be adjusted.