JPH10289569A - Fifo memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve plotting efficiency of a CPU in a display information processor by incorporating a writable/readable memory capable of freely selecting a word line of a storage part in the address generation part of its storage part and selectively shortening a write period according to the read data. SOLUTION: A counter 4 in a read side address generation part 1 counts up an inputted read side address clock, and inputs its value to a read side address of a word line control RAM 5. The RAM 5 inputs a CPU address and a CPU data bus, and outputs a pattern corresponding to the read side address to a decoder 6. A combination circuits group 2 strobes the outputs A0 to An-1 of the decoder 6 with an inputted enable signal OE, and activates one among the word lines W0-Wn-1 of the storage part 3. Thus, the improvement of the CPU plotting efficiency of 200% is attained in a paint-out display state.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage device,
In particular, FIFO (First In Fi), which is suitable for use in a display information processing device for displaying characters and figures.
rst Out; first in first out) memory.

[0002]

2. Description of the Related Art FIG. 6 shows an example of the configuration of a conventional display information processing apparatus. Referring to FIG. 6, the display information processing apparatus includes a central processing unit (hereinafter, referred to as a "CPU") 11, L
A display device 13 for displaying characters and figures such as a CD (liquid crystal display) monitor, a data memory (hereinafter, referred to as "video RAM") 12 for storing display data, a CP
A drawing control device 10 for controlling the U11 and the video RAM 12 and sending the data of the video RAM 12 to the display device 13 is provided. The drawing control device 10 includes a first-in first-out memory circuit (hereinafter, “FIFO”) capable of storing one line of display data.
10-1) and a D / A converter 10-2 for converting a digital signal of the FIFO memory 10-1 into an analog signal.

The data displayed on the display device 13 is referred to as CP
U11 is transmitted to the video RAM 12 via the drawing control device 10.
And the FIFO memory 10 in the drawing control device 10
In synchronization with the horizontal synchronizing signal at the timing shown in FIG. 8, one line of display data is sequentially written, and the horizontal blank signal indicates the display period.
Reading is started in order from the first written data of 0-1 and data is sent to the display device 13. By performing this operation every line (line), characters and graphics are normally displayed on the display device 13. In FIG. 8,
FIFO-WEB is a signal for controlling data writing to the FIFO memory, and is active at a low level in the figure. FIFO-RDB is a signal for controlling data reading from the FIFO memory, and active at a low level in the figure. Have been.

On the lead side, since there is a general standard used in a display device, the read period (the FIFO read period in FIG. 8) is constant.

[0005] The write side becomes shorter with the speeding up of the video RAM 12, and is usually shorter than the read period.
In the example shown in FIG. 8, the write period (FI
FO write period) is about half.

When the CPU 11 changes characters or graphics displayed on the display device 13, the drawing control device 10 accesses the video RAM 12 during one horizontal synchronization period (F
The CPU 11 can access the video RAM 12 during a period during which the write period of the IFO memory is not performed), that is, during a period indicated by B in FIG.

[0007] During this period, the CPU 11 rewrites data in the video RAM 12 to change characters and figures displayed on the display device 13. The CPU 11 may access the video RAM 12 in order to temporarily store not only display data but also other data.

Accordingly, in FIG. 8, the longer the period B during which the CPU 11 can access the video RAM 12, the higher the drawing efficiency of the CPU 11 and the higher the speed of the display information processing apparatus as a whole.

As described above, the CPU 11 controls the video RAM 1
It is extremely important to increase the time (period B in FIG. 8) during which the access to No. 2 can be accessed.

FIG. 7 is a diagram showing an example of the configuration of a conventional FIFO memory circuit, which is disclosed in Japanese Patent Laid-Open No. 3-125389. This circuit is a normal RAM
And a FIFO function. FIG. 7 (a)
Is a block diagram showing the overall functional configuration. In parallel with an address decoder 71, a serial input-parallel output shift register 72 is provided, and outputs of the address decoder and the shift register are passed through a logic block 73.
It is supplied to the word line driver 74.

The logic block 73 receives, from a CPU or the like (not shown), an output of a decoder 71 for specifying an address corresponding to an address signal supplied via an address bus, and an output of a shift register 72 for sequentially specifying an address. In the case of the normal RAM mode, the address decoder 7
1 is supplied to the word line driver 74 and
In the case of the IFO mode, the output of the shift register 72 is supplied to the word line driver 74.

FIG. 7B is a diagram showing a circuit configuration of a portion corresponding to one word line W among the address decoder 71, the shift register 72, the logic block 73, and the word line driver 74.

The selection signal SE has a logical value "1" when the RAM mode is selected, and has a logical value "0" when the FIFO mode is selected. A FIFO is connected to the data input terminal of the first flip-flop of the shift register (not shown).
It is connected to a circuit that outputs a logical value "1" only once in synchronization with the fall of the clock pulse CP immediately after the start of the mode.

When the FIFO mode is selected, the reset line RS falls and each flip-flop (F
After the output of F) is cleared (Q = “0”), the logical value “1” is supplied only once to the first flip-flop of the shift register, and is sequentially synchronized with the falling edge of the clock pulse CP. Data shifts in the shift register, and in synchronization with the rising edge of the clock pulse CP,
The word lines of the storage unit 75 are sequentially driven from the beginning, and the data in the storage unit 75 is accessed in order.

[0015]

However, in the above-mentioned conventional FIFO memory, since data written in a first-in-first-out manner is read out in a first-in-first-out manner, all data must be written in order to read all the data. There must be.

Therefore, this FIFO memory is shown in FIG.
When the memory is used as the FIFO memory 10-1 of the above-described drawing control device, it is necessary to always write a data amount that can be used in the read period.

In FIG. 8, since the period A during which the drawing control device 10 accesses the video RAM 12 is always constant, the time during which the CPU 11 can access the video RAM 12 (period B in FIG. 8) also becomes constant. , C
This hinders the improvement of PU drawing efficiency.

At the same time, the display information processing apparatus as a whole
There is a problem that a high-speed system cannot be realized.

Recently, the amount of read data has been increasing along with the demand for miniaturizing the display screen and increasing the amount of information that can be displayed.

However, since there is no change in the general standard that determines the cycle of the horizontal synchronizing signal, the period during which the drawing control device accesses the video RAM (FIFO) is increased.
Memory write period) and the CPU
It is becoming an important issue to increase the time (period B in FIG. 8) in which the data can be accessed.

Accordingly, the present invention has been made in view of the above problems and problems, and its object is to provide a CPU.
And a FIFO memory that controls the video RAM and sends the data of the video RAM to the display device, and is capable of improving the drawing efficiency of the CPU of the display information processing device including the drawing control device. .

[0022]

In order to achieve the above object, a FIFO memory according to the present invention has a built-in writable and readable memory capable of freely selecting a word line of the storage unit in an address generation unit of the storage unit. However, it is characterized in that the write period can be selectively shortened depending on the read data.

Further, the present invention is characterized in that the internal pattern held in the storage section can be freely rewritten by a central processing unit.

[0024]

Embodiments of the present invention will be described below. In a preferred embodiment, the FIFO memory of the present invention incorporates a word line control RAM (5 in FIG. 1) in an address generation unit in the FIFO memory, and for example, the pattern of the word line control RAM is determined by a display screen pattern or the like. And by freely controlling the access order of the word lines of the storage unit (3 in FIG. 1), it is possible to shorten the write period of the FIFO memory and improve the drawing efficiency of the CPU. .

That is, in the embodiment of the present invention, depending on the pattern of the display screen, not all of the display data of the video RAM is written to the FIFO, but only the minimum necessary data is written. By the operation of the RAM, a desired display screen is correctly displayed on the display device.

As described above, in the preferred embodiment of the present invention, when the display screen is repeatedly displayed with a certain pattern or when the display screen is filled with one color, the drawing control device (10 in FIG. 6) is used. The period for accessing the video RAM (12 in FIG. 6) (this period corresponds to the write period of the FIFO memory) can be shortened.

[0027]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a first embodiment of a FIFO memory according to the present invention; In the present embodiment, the overall configuration of the display information processing device including the CPU, the drawing control device, the video RAM, and the display device is the same as the configuration shown in FIG. Next, the FIFO memory 10-1 for storing one line of display data in the drawing control device 10 will be described.

FIG. 1 is a diagram showing the configuration of an embodiment of a FIFO memory according to the present invention. In the FIFO memory of the present embodiment, the read address generation unit 1 of the FIFO memory includes a word line control RAM (random access memory).
5 is built in.

Referring to FIG. 1, a read-side address clock, a data bus from CPU (see 11 in FIG. 6),
The outputs A0 to An-1 of the read-side address generation unit 1 to which the address from the CPU is input are output enable signals O
The signal is input to the combinational circuit group 2 together with the E signal, and the output of the combinational circuit group 2 is connected to the word lines W0 to Wn-1 of the storage unit 3.

The read-side address generator 1 receives a counter 4 for receiving a read-side address clock, a word line control RAM 5 which receives an output of the counter 4, a CPU data bus and a CPU address, and an output of the word line control RAM 5. Decoder 6 for decoding and outputting
And is provided.

When the read-side address clock is input, the counter 4 in the read-side address generator 1 counts up, and the value of the counter 4 is stored in the word line control RA.
It is input to the read side address of M5.

The word line control RAM 5 outputs a pattern corresponding to the read-side address to the decoder 6.

The output of the decoder 6 is the combinational circuit group 2
, One of the word lines of the storage unit 3 is activated by being strobed by the input OE signal.

In the present embodiment, the display area is set
FIG. 2 shows an example in which the dot length is set to 6 dots in the vertical direction.
This will be described below with reference to FIGS. 3, 4, and 5. The number of vertical and horizontal dots in the display area is, of course, not limited to this. FIG. 2 is a diagram showing a block configuration of the read-side address generator 1 showing the bit width of the bus. FIG. 3 is a diagram showing an example of an internal pattern of the word line control RAM 5. FIG. 4 is a timing chart for explaining the operation from the input of the read-side address clock to the output of the word line control RAM 5. FIG. 5A shows data in the storage unit 3, and FIGS. 5B and 5D show patterns appearing on a display device of 32 dots in the horizontal direction and 6 dots in the vertical direction.
FIG. 5C is a diagram showing another example of the internal pattern of the word line control RAM.

Now, the word line control RA shown in FIG.
It is assumed that the pattern shown in FIG. 3 is written in M5 through a signal line of 5 bits of CPU address and 5 bits of CPU data bus. Word line control RAM
The address 5 (5 bits) is comprised of addresses 0 to 31, and the output (OUT) is comprised of 5-bit data.

The storage unit 3 of the FIFO memory stores FIG.
(A) The data described in the first line is written as W0, W1, W2,...
Nothing is written in W31 (indicated by "empty").

Next, when the first read-side address clock in the first row of the display device is input, the output of the 5-bit counter 4 becomes "0" in FIG. The word line control RAM 5 receives the pattern "LLLL"("0h" in hexadecimal notation) corresponding to the address 0 in FIG. 3, and the word line control RAM pattern in hexadecimal (hexadecimal notation) 2), and the output A (0) of the decoder 6 for converting 5 bits to 32 bits in FIG. 2 becomes active, and the first word of the storage unit 3 is passed through the combinational circuit group 2 (see FIG. 1). W0 is selected.

When W0 is selected, the storage unit 3 stores in FIG.
(A) Since the data in the first row has been written, W0
The data “white” is displayed on the display device (see 13 in FIG. 6).

When the next read-side address clock is input, the output of the 5-bit counter 4 (see FIG. 2) becomes "1", and the word line control RAM 5 corresponds to the address 1 in FIG. 5A is output from the storage unit 3 via the decoder 6 (see FIG. 2) and the combinational circuit group 2 (see FIG. 1). It is output and displayed on a display device.

The above operation is repeated every time the read-side address clock is input, and the data in the first row of FIG. 5A is displayed on the display device.

When the ninth read-side address clock is input, the output of the 5-bit counter 4 (see FIG. 2) becomes "8" and the word line control RAM 4
5 outputs a pattern “0h” corresponding to the address 8 of FIG.
(A) W0 data “white” in the first row, that is, the storage unit 3
Is output and displayed on the display device.

Thus, looking at the internal pattern of the word line control RAM 5 shown in FIG. 3, since the pattern is repeated for each address 8, as shown in the timing chart of FIG.
The output of M5 is repeated every eight read-side address clocks, and the storage unit 3 repeatedly selects up to eight words from the top.

Since this operation is repeated for each row, as shown in FIG. 5B, a repeated pattern for every 8 dots is displayed on the display device.

In this case, as shown in FIG. 5A, even if no display data is stored in the storage unit 3 after W8, a display device of 32 dots in the horizontal direction and 6 dots in the vertical direction does not
Since the data is normally displayed, the FIFO write period in FIG.
1/4 (= 8 dots / 3
2 dots), which increases the period during which the CPU can access the video RAM, thereby improving the drawing efficiency of the CPU.

Further, the pattern of the word line control RAM 5 is simply rewritten by the CPU as shown in FIG. 5C while the data of the storage section shown in FIG.
A pattern as shown in FIG. 5D can also be displayed. Note that CP
The pattern data stored in the word line control RAM 5 from U is shown in FIG.
Rewritten via the U data bus.

Therefore, in the present embodiment, FIG.
In the case of a display state such as a repetitive pattern as shown in (c), since the word line control RAM 5 is incorporated, the order of selecting word lines in the storage unit 3 can be set freely. The period can be shortened, and as a result, the period during which the CPU can access the video RAM can be extended.

When the CPU accesses the video RAM, that is, when the display pattern is changed, the display device generally has a display output of a repetitive pattern or a fill in many cases. Efficiency can be improved, and as a result, a high-speed system can be realized as the entire display information processing apparatus.

The cycle of a general horizontal synchronizing signal is 63.5 μm.
s, the data required to display one line to be written from the video RAM to the FIFO memory is 640 words, and
Assuming that it takes an average of 50 ns to perform a word write, in a normal display that is not a display of a repetitive pattern or fill, the period during which the CPU can access the video RAM is about 31.5 μs (= 63.5 μs−50 ns) from FIG.
× 640 times).

On the other hand, in this embodiment, the CPU
The maximum period during which the video RAM can be accessed is that the number of FIFO writes is one and the word line control RA
This is the time when all the internal patterns of M are set to “0h” and the display device is in the solid display. The CPU at this time is
The period during which the AM can be accessed is about 63.45 μs (= 6
(3.5 μs−50 ns × 1 time), so that the CPU drawing efficiency is improved by about 200% compared to the normal display state.

When the conventional FIFO memory is used, even in the solid display state, the same F value as in the normal display state is used.
Since this is the number of times of IFO writing, the present embodiment improves the CPU drawing efficiency by about 200% compared to the solid display state of the display information processing apparatus using the conventional FIFO memory.

[0051]

As described above, according to the present invention,
A word line control RAM is built in an address generation unit in the FIFO memory. For example, the pattern of the word line control RAM is rewritten according to a display screen pattern and the like, and the access order of the word lines in the storage unit is freely controlled. Is shortened, and as a result, the drawing efficiency of the CPU can be particularly improved. As an example of the quantitative effect of the present invention, the present invention is about 200% less than the solid display state of a display information processing apparatus using a conventional FIFO memory.
To improve the CPU drawing efficiency.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a diagram illustrating a configuration of a read-side address generation unit according to an embodiment of the present invention.

FIG. 3 is a diagram showing an example of a pattern of a word line control RAM in one embodiment of the present invention.

FIG. 4 is a timing chart illustrating an operation of the word line control RAM when the pattern of FIG. 3 is used in one embodiment of the present invention.

FIG. 5 is a diagram for explaining one embodiment of the present invention;
3A is a diagram illustrating an example of data stored in a storage unit according to an embodiment of the present invention. FIG. 3B illustrates a display screen when the storage unit data of FIG. 3A is applied to the pattern of FIG. FIG. 13C is a diagram showing another example of the pattern of the word line control RAM, and FIG. 14D is a diagram showing a display screen when the storage unit data of (a) is applied to the pattern of (c). FIG.

FIG. 6 is a diagram illustrating a schematic configuration of a display information processing apparatus.

FIG. 7 is a diagram illustrating an example of a configuration of a conventional FIFO memory.

FIG. 8 is a timing chart showing a write / read period of the FIFO memory.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Read side address generation part 2 Combination circuit group 3 Storage part 4 Counter 5 Word line control RAM 6 Decoder

Claims (5)

[Claims] 1. An address generation section of a storage section includes a memory capable of freely selecting a word line of the storage section, and a writing period to the storage section can be selectively shortened depending on read data. F characterized by having
IFO memory. 2. An internal pattern held in the memory,
2. The FIFO memory according to claim 1, wherein the FIFO memory can be freely rewritten by a central processing unit. 3. An address generation unit for generating an address of a storage unit, comprising a memory for controlling a word line of the storage unit, wherein the storage unit is accessed based on an output of the memory, and data read from the storage unit. A pattern stored in the memory for controlling the word lines in accordance with (i), whereby the order of access to the word lines in the storage unit is freely controlled. 4. The address generating section reads pattern data of the memory using an output of a counter as an address input, decodes the read pattern data and supplies the decoded pattern data as an address output to the storage section, and 4. The storage device according to claim 3, wherein said memory is accessible from said CPU to rewrite a storage pattern. 5. The storage device according to claim 3, wherein the storage device is a CPU.
And a video RAM that stores display data, and includes a drawing control device that sends the data of the video RAM to a display device. The storage device stores at least one line of display data. By rewriting the pattern stored in the word line control memory and freely controlling the access order of the word lines in the storage section, the write period to the storage section is selectively shortened, and the A display information processing apparatus, wherein a period during which a CPU accesses the video RAM is extended.