JPS5961876A - Character rotator - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a character rotation device that rotates patterns as necessary when displaying or printing characters, figures, etc. in a dot matrix.

Conventional configurations and their problems In recent years, there have been remarkable advances in technology for processing and editing Japanese text, and among them, various devices have been devised for displaying and printing kanji and kana.

Some of such display/printing devices are equipped with a character rotation device. That is, Japanese texts can be written vertically or horizontally, and are displayed or printed in either vertical or horizontal writing as necessary. For example, if characters as shown in FIG. 1 (,) are sequentially displayed or printed in the horizontal direction, a horizontally written Japanese text can be obtained. If the characters in FIG. 1(a) are rotated by 900 as shown in FIG. 1(b) and then sequentially displayed or printed in the horizontal direction, a vertically written Japanese text can be obtained.

Now, when performing the above-mentioned horizontal or vertical writing display or printing, the inside of the display/printing device is as shown in FIG. 1(a).

Although the patterns shown in (b) may be prepared separately, such a method is not very economical.

Therefore, when displaying or printing the pattern shown in Figure 1(b), prepare only the pattern shown in Figure 1(b), and use the pattern in Figure 1(a) when displaying or printing. Function to display or print by rotating 900 degrees,
That is, there are some devices in which a character rotation device is provided in a printing/display device.

Hereinafter, a conventional character rotation device such as a double character rotation device will be explained.

FIG. 2 is a block diagram of a conventional character rotation device. In the figure, 1 is a rotation control unit that controls character rotation using a rotation signal a that indicates the direction of rotation, and 2 is a rotation control unit that sequentially outputs addresses according to a certain pattern based on an address count signal d' sent from the rotation control unit 1. It is an address counter. Reference numeral 3 denotes a font memory which outputs data corresponding to the address sent from the address counter 2 via the address bus 4, and stores a standard pattern composed of fonts of 26 x 26 bits as shown in Fig. 3. ing. Reference numeral 6 denotes a rotation unit that rotates the pattern using pattern data 2 sent from the font memory 3 via the data bus 6, and a control signal sent from the rotation control unit 1, that is, a horizontal shift that controls reading and reading of the pattern data. Signal S, vertical shift signal C
controlled by

Hereinafter, the configurations of the rotation control section 1 and the rotation section 6 will be explained in more detail using FIGS. 4 and 6.

FIG. 4 is a block diagram of the rotation control section 1. In the same figure, 1a indicates whether the rotating unit 6 is reading the pattern data 2 of the font memory 3, or if the rotating unit 6 is not yet reading the rotated character signal f.
A font data latch signal and a rotation data read signal C are sent out via the logic circuit group 1b in response to a read signal d indicating whether the font data is being outputted and a font data read start signal e.

FIG. 6 is a block diagram of the rotating section 6. In the same figure,
SO1 to s26 are parallel-in/parallel-out shift registers, and are composed of 26 bits x 26 lines in total.

Below, regarding the character rotation device configured as above,
The operation will be explained using the waveform diagram shown in FIG.

In Fig. 6, Fig. 6(a) shows the rotation signal a, Fig. 6(b) shows the font data latch signal q, and Fig. 6(c) shows the rotation signal a.
(in the same figure) indicates the rotation data readout signal, (e) indicates the horizontal shift signal sent to the rotation unit 6 to control pattern data reading and reading, and (e) in the same figure indicates the horizontal shift signal sent to the rotation unit 6 to control the pattern data readout. The vertical shift signal C that controls the reading and reading of the font memory 3 is shown in FIG. Figure (g) shows the font data read start signal e.

First, the case where the rotation direction is 0π shown in FIG. 1(a) will be explained. When the first address where the font pattern to be read is stored is set in the address counter 2, the read start signal e and the read signal d are input to the rotation control unit 1, and the lock is locked as shown in FIG. The generating section 1a starts outputting the font data latch signal q and the rotation data read signal. At this time, the rotational signal a is "L I+" because the rotational direction is 0π (Fig. 6 t
1).

That is, when the rotation direction is 0π, the signal waveforms of each part are as shown in Figure 6.
It will be like one period.

Now, the font day clutch signal q1 is the horizontal shift signal b1
Then, it is sent to the rotating section 4. The data bus 6 is 2
Shift register group s01~ as 00'~225'
It is input serially to s25. When the horizontal shift signal S is input, the data bus 225' is transferred from the 25th stage (hereinafter referred to as 501-25) of the shift register sD1 to sol -25-+s01-24-...5c11.
-01→501-Do and 501-00→q25.

The other shift registers s02 to s25 operate similarly.

At the time when the horizontal shift signal b1 is input, the data bus Z
25 information is stored in shift register 501-25. The data bus 224 is stored in 502-25... At the same time, an address count signal a' is output to the address counter 2, and the address counter 2 advances by 1 to indicate the address where the next font data is stored and prepares for the next readout. Next, when the font data latch signal q2 is output from the clock generator 1a shown in FIG. 4, the rotation controller 1 outputs the horizontal shift signal b2, and the information on the data bus z25 is transferred to the shift register 501-25. Stored. Information stored in shift register 501-25 is shifted to 501-24. At the same time, the address counter 2 counts up in response to the address count signal. In this way, 261 lines of information are sequentially read out from the font memory 3 and stored in the rotation unit 6. At the time of the horizontal shift signal b26, the information stored in the shift register 501-25 at the time of b1 has been shifted to F+01-0.

When 26 rai>·min, that is, one pattern has been stored, reading of rotation data from the rotation unit 5 begins.

The clock generator 1a generates a rotation data read signal at 26
Outputs pulses (26 dots). At the time of the rotational data read signal 51, a horizontal shift signal b1' is outputted and input to the shift register group s[11 to S26 of the rotating section,
Shift register 801-00 information is sent to f25. Information on 502-0 goes to f24, 503-0 → f23
...read out from 526-0→f00.

Also, the information in shift register 501-1 is shifted to shift register 501-0. 501-2→501-1・・・・・・
Sc]1-. 25 → 501-24.

The twisted shift register groups s02 to S26 also perform similar operations, and rotation data in the rotation direction 0π is output to the rotation data buses f25 to foo. This sequential shift operation is repeated 26 times to read out the data stored in the shift register groups s01 to s26.

Next, Fig. 1(d) shows the rotation direction 3π/2 (270°
) case will be explained. Note that when the rotation direction is 3π/2, the signal waveforms of each part are as shown in FIG. 6 t2. First, in the same way as when the rotation direction is 0π, the first address where the font pattern to be read is stored is set in the address counter 2, and the read start signal e and read signal d are input, as shown in FIG. The clock generator 1a starts outputting the font data latch signal q and the rotation data read signal.

Now, since the rotation signal a is "H", the font data latch signal 91' is output from the rotation control section 1 as a vertical shift signal b1, and is sent to the shift register group s01 to 826 of the rotation section 6.
is input. At this time, information on data bus 6 200 is stored in shift register 501-0, and information on zol is stored in shift register 501-1, zol-+501-2...=z2
5→g01-25 respectively. The information in the shift register 501-0 is shifted to the shift register 5D2-[+, and the information in the shift register 501-1 is shifted to 502-1.
-2-+ s 02-2...5ol-25→5
02-25, respectively.

Each of the shift register groups 806 to s26 performs the same operation. At the same time, the address counter 2 counts up by one and prepares to read the next font data. Then, the font data latch signal q 2 / is supplied to the clock generator 1
When the rotation control unit 1 outputs the vertical shift signal C2, the rotation unit 6 reads the nosittern data of the next address read from the font memory 3 through the data bus 2.
The information of 00 is stored in the shift register 501-0, and the zo
Information on l is sent to 501-1...z25→g01-25
Each is stored in a map. The turn data of the previous address stored in the shift register 501-0 is 501-0.
→ shifted to 502-0, so 1-1 → s[]2-
1... and the contents of the shift register sol are shifted to the shift register s02. This operation is repeated 26 times and the pattern data is the shift register group s01 of the rotating section 6.
~s25 is stored. By the 26th time, the pattern data at the start address of the font pattern that was attempted to be read from the font memory 3 has been stored in the shift register s26.

When storing pattern data for 26 lines, the rotation direction is 0.
As in the case of π, reading of rotation data from the rotation unit 6 is started. The readout signal d1' is inputted to the rotating section as a horizontal shift signal b1'', and the information in the shift register 526-0 is read out to the rotating data bus f00, and the information is read out to the rotating data bus f00.
0→fo1...501-0→f25.

At the same time, the information in shift register 526-1 is shifted to 526-0, 525-1→525-0...501-1→5
The data is shifted to 01-0 in preparation for the next readout. The pattern data read out in this way is rotated in the rotation direction 3π/
2 (270°) rotation data is output to the rotation data bus f. In this way, a rotation pattern is obtained.

However, although the conventional device described above has a high rotation speed, it requires a large number of shift register groups, which requires a large number of ICs, making it expensive.
) and 3π/2 (270°), so the range of use is narrow. Furthermore, it has the disadvantage that it is difficult to deal with changes in the dot pattern configuration of the font, for example when it becomes 30x30 or 32x32.

Purpose of the Invention In view of the above drawbacks, the present invention eliminates the IC of the shift register group conventionally used for rotating characters and figures, and also eliminates the need for 0π
(0°), π/2 (90°), π (180°).

To provide a character rotation device that is capable of rotating characters and figures in the 3π/2 (2700) direction and can also quickly respond to conversion of font memory that stores dots of characters and figures. .

Structure of the Invention The present invention provides a memory having a number of bits greater than the number of dots of a dot pattern of a character or figure stored in a font memory, and when storing character or figure data in the memory, rotates the character or figure. The above object is achieved by configuring the data to be stored in the storage position of the memory in such a manner that it appears to be stored horizontally, vertically, and horizontally, and to output character and graphic data from the memory according to the storage position. It is.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 7 is a block diagram of a character rotation device in one embodiment of the present invention.

In the figure, reference numeral 10 denotes a clock generator, which generates a line count signal (■) representing the number of lines of the pattern to be read, and a pattern dot using a write signal H1 (described later) indicating whether the memory is writing or reading, and a pattern data read start signal. It sends out a dot count signal representing a number, and a read clock signal R (32×32.=1024 outputs) when reading a rotation pattern by a memory to be described later. Reference numeral 11 denotes a rotation control unit, which outputs a rotation signal F for instructing the rotation direction, and the above-mentioned line count signal ■.
The dot count signal includes an address count signal that causes the address counter 12 to sequentially read out patterns to count up one by one in response to the clock signal H, and a shift signal E that causes the data held in the data latch circuit 13 to be read out one dot at a time. At the same time, it also sends selection signals N, O, and P that control a group of multiplexers in an address control section, which will be described later. Reference numeral 14 denotes an address control section which controls the address of the memory 14 (described later) in response to the above-mentioned read start signal, dot count signal, and clock signal R2 selection signals N, O, P, rotates the pattern, and rotates the pattern. The control unit 11 detects through the count bus M which line and which dot is being processed. 1
A font memory 5 inputs the address sent from the address counter 12 via the address bus A, and sends pattern data (26 bits) to the data latch circuit 13 via the data bus B. Reference numeral 16 denotes a memory, which sends rotation data G in response to an address signal sent from the address control section 14, a shift signal E, and a pattern data signal Q of a one-dot pattern sent from the data latch circuit 13.

The specific configuration of the memory 16 will be shown below with reference to FIG.
, the first memory 16 receives the address signal L (CBAo) shown in FIG.
~9) Although it is a 1-bit memory, it appears to be a memory with the same number of bits represented by the upper address 2m (CBA5-q) and the lower address L/s 2n (CBAo-4). can be expressed. If the dot pattern configuration is 26 (dots) x 26 (lines), the memory 16 may be a 1-dot configuration memory with a capacity of 32 x 32 (2 x 2), and in fact, a 1024 x 1 bit memory may be used. Note that although the configuration of the memory 16 will be described below as a 2π/2m×1 bit configuration (1024×1 bit), it is not necessarily necessary to have a×1 bit configuration.

Next, the address direction of the address control unit 14 with respect to the apparent upper and lower addresses of the memory 14 is set to the first o.
As shown in the figure.

In the same figure (8), the counting direction of the lower address is up (hereinafter abbreviated as UP), the counting direction of the upper address is also UP, and the lower address is in the main scanning direction (hereinafter abbreviated as ■). On the other hand, the upper address means the sub-scanning direction (hereinafter abbreviated as "stock"). In the figure (B), since the counting direction of the lower address is UP, it is in the sub-scanning direction, and when the counting direction of the upper address is down (DO'WN), it is in the main scanning direction. Note that the main scanning direction and the sub-scanning direction are the directions in which the memory 16 is apparently addressed, regardless of the upper and lower addresses.

Next, the specific configuration of the address control section 14 will be explained using FIG. 11. 21 is ■UP counter, 22 is ■Down (hereinafter abbreviated as DOWN) counter, and 23 is [stock] UP.
The counter 24 is a [phase] DOWN counter. Note that the UP counters 7p21 and 23 are binary counters that are loaded with 'oooooo' and counted up, and the DOWN counters 22 and 24 are binary counters that are loaded with '11111' and counted down.26 is ■
■Multiplexer which selects whether it is in the UP direction or the DOWN direction, and N is its selection signal (■Selection signal). 26 is [
The [phase] multiplexer selects whether the [phase] is in the UP direction or the DOWN direction, and Q is its selection signal ([phase] selection signal). 27 is a lower address multiplexer that selects whether the lower addresses CBAO~4 are ■ or [phase], 28 is an upper address multiplexer that selects whether the upper addresses CBA5~9 are ■ or [phase], and P is the selection signal (■■ selection signal).

Note that S is ■UP count bus, T is ■DOWN count bus, U is [phase] UP count bus, and ■ is [phase] DOW.
N count bus, W is ■address bus, X is ■address bus, Y and Z are lower address Y and upper address Z of the selected address signal.

Next, the control direction of the address signal and the apparent storage position of the 26×26 dot pattern in the memory 16 will be explained using FIG.

First, when writing to the memory 16, the lower addresses C13AO-4 are DOWN and the upper addresses CBA5-9 are [phase] UP, regardless of the rotation direction. 26×26
The rotation control unit 11 controls where on the 32×32 dot matrix the dot pattern is stored. When the rotation direction is 0π, it is on the upper left, when it is π/2, it is on the upper right, π
When , it is stored in the lower right, and when 3π/2, it is stored in the lower left. Next, when reading out the rotation pattern G from the memory 16, the address signal is controlled in the direction of rotating the pattern. The counting direction of the address signal at this time is as shown in FIG. In other words, when the rotation direction is π/2, the lower address Y is in the [phase] DOWN direction, and the upper address Z is in the [phase] DOWN direction.
If read in the PUP direction, π as shown in Figure 1.
/2 rotation pattern can be obtained. Even when the rotation directions are Oπ, π, and 3π/2, the respective rotation patterns shown in FIG. 1 can be obtained by performing the control shown in FIG. 12 in the same manner.

Next, using FIG. 13, the selection signal M of the rotation control section 11,
The circuit for generating O and P is shown. In FIG. 13, numeral 31 is a decoder for the rotation signal F that operates only while the write signal H is °'L'' (while the memory 16 is being read). Output 2 rotation direction π/2 to F2 ゛'H Pa Output 2 rotation direction π to F6 °
Output °H'° 2 Output "H" to F4 in rotation direction 3π/2. Naoto's F1 to F4 are rotation decode signals. 32 is a circuit for generating the selection signal N. As shown in the upper part of FIG.
The multiplexer 26 generates °'L''' so that it selects ■.33 is the [phase] which controls the [phase] multiplexer.
34 is a generation circuit for the selection signal ◯; and 34 is a generation circuit for the [phase] selection signal P.

Next, a circuit for generating the address count signal C and shift signal E in the rotation control section 11 will be explained using FIG. 14 and FIG. 16. Note that FIG. 16 shows a waveform diagram of each signal.

In FIG. 14, reference numeral 41 denotes a decoder for the UP count bus S, which outputs 81 as an L pass when the count is "00000" and outputs 82 when the count is "00110".

42 is a decoder for the [phase] UP count bus U, which outputs Ul at count 'oooooo' and U2 at '00110'.
43 is a circuit that generates a non-shift signal SS, and 44 is a circuit that generates a non-count signal UU. In the figure, 45 is a decoder for the rotation signal F. 4e is a decoder for the rotation signal F. 4e is a circuit that generates a non-shift signal SS. In the generation circuit, the rotation direction is 0.
At times other than π and 3π/2, the dot count signal and the non-shift signal SS are logically summed to obtain a shift signal E.

Reference numeral 47 denotes an address count signal C generating circuit which calculates the logical sum 9 of the line count signal 2 and the non-count signal UU and generates the address count signal C except when the rotation direction is π or 3π/2.

Hereinafter, the operation of the character rotation device configured as described above will be described first with respect to the rotation direction 0π. When the first address in which the font pattern to be read is stored is first set in the address counter 2 and the read start signal is input, the clock generator 10 generates the dot count signal ■ and the line count signal. Start.

The font memory 16 also outputs pattern data corresponding to the address bus A to the data bus B.

Data latch circuit 13 holds the contents of data bus B in response to a data launch signal.

Now, in the rotational direction 0π, apparently 26X2 of the memory 16
The storage position of pattern No. 6 is at the upper left as shown in FIG. Therefore, the lower address Y becomes ■DOWN, and the upper address Z becomes [phase] UP. 32 dat when shifting data from the data launch circuit 17 and writing it to the memory 14
If the data is shifted after the lower address Y advances by -26dat = 6 dat (actual countdown), the pattern can be moved to the left end. and the 16th
A shift signal E as shown in FIG. E is generated. The address color/receiver 12 sequentially counts up and becomes ready to read the data r of the next address. Further, since the address count signal C is in the rotational direction 0π, the rotation control section 11 generates the line count signal ■ by twisting the address count signal C. Then, sequentially, memory 1
When the write operation is completed in step 6, the read operation starts, and the clock generator 10 generates the read clock signal R. At the time of reading, the rotation signal decoder 31 operates, and the address signal bus L of the memory 16 indicates that the lower address Y is UP.
, the upper address Z becomes @UP, as shown in Figure 1 (
A pattern as shown in a) can be obtained.

Next, the rotation direction π/2 will be described.The rotation direction π/2 is written in the upper right corner of the memory 16. In the case of the rotation direction π/2, the contents of the data wrap circuit 13 may be shifted and stored in the memory 16 from the beginning in synchronization with the transmission of the address signal bus L.

Further, in the case of the rotation direction π, the data is stored at the lower right when writing to the memory 16. If the address counter 12 is counted after the address signal bus L has advanced by 6 lines, a 26×26 pattern can be stored at the lower end. Rotation control section 1
1 generates an address count signal C as shown in FIG. 16C.

Furthermore, for the rotation direction 3π/2, a combination of 0π and π can be stored at the lower left.

Rotation direction π/2. For π and 3/2π, if the reading direction is carried out in the same manner as for the rotation direction ○π, each rotation pattern shown in FIG. 1 can be obtained.

As described above, according to this embodiment, the memory 16 having a 2 x 2 x 1 bit configuration is provided, and the pattern is stored in the memory 16 while apparently being shifted horizontally, vertically, and vertically, and the reading direction from the memory 16 is switched in accordance with the direction of one rotation. As a result, four types of rotation directions, which could not be achieved in the past, can be freely realized, and there is no problem of misalignment of the read pattern.

Further, by employing the memory 16 in comparison with the conventional shift register group shown in FIG. 2, the cost is lower and the number of ICs can be significantly reduced.

In the case of this embodiment, many of the IC-based counters are binary counters, so they can be used as they are regardless of the dot configuration of the font pattern, and the conventional hexadecimal counters are not required.

Furthermore, even if the configuration of the dot pattern changes, it can be dealt with immediately by changing the decoding timing of the non-shift signal SS and the non-count signal UU.

In the embodiment, the bit configuration 2nx2rn of the memory 16 is set to n = m = 5, but n\m has no effect. In addition, when storing data in the memory 16, the read direction of the data bus B may be GoO although the data is stored from G25, and the lower address Y during writing may be ■DOWN or ■UP; in this case, the storage position may be different. Therefore, all you need to do is change the reading direction.

Effects of the Invention As described above, the present invention provides a memory having a number of bits greater than the number of dots of a dot pattern of a character or figure stored in a font memory, and changes the storage position of the memory according to the rotation of the character or figure. By storing and reading that data, we can eliminate the shift register group ICs conventionally used for rotating characters and figures, and also eliminate Oπ (0°
), π/2 (900), π (1800), 3π/2 (
270°) direction, and the font memory can be quickly replaced if necessary, which has great effects.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the rotation of a character pattern, FIG. 2 is a block diagram of a conventional character rotation device, FIG. 3 is a diagram showing a dot configuration of a character pattern, and FIG. 4 is a block diagram of a rotation control unit.
FIG. 6 is a block diagram of the rotation unit, FIG. 6 is a waveform diagram of each part of a conventional character rotation device, FIG. 7 is a block diagram of a character rotation device in an embodiment of the present invention, and FIGS. 8 and 9 are FIG. 10 is a diagram showing the configuration of the memory, and FIG. 10 is a diagram showing the address direction of the address control unit with respect to the apparent storage location of the memory.
Figure 1 is a block diagram of the address control section, Figure 12 is a diagram showing the control direction of the address signal and the memory storage position of the pattern, Figure 13 is a block diagram of the selection signal generation circuit of the rotation control unit, Figures 14 and 12 are Figure 16 is a block diagram of the address count signal and shift signal generation circuit in the rotation control section;
FIG. 16 is a waveform diagram of each part in this embodiment. 1o...Clock generation unit, 11...Rotation control unit, 12...Address counter, 13...
...Data latch circuit, 14...Address control unit, 16...Font memory, 16...Memory. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 6
Figure 7 Figure 5 Figure 8 Figure 9 Raft Figure 10 f, 41 (B)
Figure 13 Figure 14 Figure 15

Claims (2)

[Claims] (1) A font memory that stores characters and graphics in a dot configuration, and a 2" x 2m font having a number of bits greater than the number of dots of the dot pattern of the characters and graphics stored in the font memory (however, n≧2m). , m≧2 integer)
A memory having a bit configuration, a control unit that controls data input and output from the font memory and the memory, and a clock generation circuit that provides a control clock to the control unit,
When storing character or graphic data in the memory, the character or graphic data is stored apparently at the upper right, lower right, upper left, or lower left of the memory depending on the rotation direction of the character or graphic, and the storage position is A character rotation device that outputs character and graphic data from the memory in accordance with the above. (2) The control unit includes an address control unit that controls addresses of the memory, and the address control unit includes two sets of counters, one set being an amplifier counter and a down counter,
2. The character rotation device according to claim 1, wherein said counter stores data in said memory and reads data from said memory in accordance with the rotation direction of characters and graphics.