JPH10285398A - Image-forming method and system therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image-forming system which is applicable to image information with high frequency. SOLUTION: This method adopts a delay clock generating means 1 that receives a reference clock 6 synchronously with a pixel clock and generates a plurality of delayed clocks 7, a delay time measurement means 2 that measures a delay clock equivalent to one pixel time among delay times of pluralities of the delayed clocks 7, a delay clock selection means 3 that selects a desired number of delayed clocks 9 within one pixel time based on the measured value and provides an output of the selected clocks, a pulse generating means 4 that applies logical arithmetic operation to a desired number of the selected delay clocks 9 and a reference clock 6 respectively to generate pluralities of pulses 10 with different pulse width, and a pulse selection means 5 that selects a corresponding pulse from a plurality of pulses 10, in response to the gradation of received multivalue image information 11 and provides an output of the selected pulse as binary image information 12.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image forming method and apparatus for forming a halftone image by pulse width modulation of input multi-valued image information.

[0002]

2. Description of the Related Art There are an analog generation method and a digital generation method as a method for generating a multi-step pulse width. The analog generation method is a method of comparing a triangular wave generated in synchronization with image information with a D / A conversion output of the image information, as described in Japanese Patent Application Laid-Open No. 62-39972. The digital generation method is a method in which a clock faster than the pulse width to be generated is input and the frequency is generated by a counter or the like.

[0003]

The above prior art has a problem that it can be applied to image information having a low frequency (about 20 MHz or less), but cannot be applied to image information having a high frequency.

An object of the present invention is to provide an image forming method and apparatus which can be applied to high-frequency image information.

[0005]

According to the present invention, there is provided an image forming method for converting multi-valued image information into binary image information modulated in a time axis direction. To generate a plurality of delay clocks having different delay times in stages, select the number of delay clocks necessary to divide one pixel time from among them, and set a time width corresponding to the delay time of the selected delay clock. And generating a pulse having a corresponding time width corresponding to the input gradation of the multi-valued image information as binary image information.

The required number of delayed clocks are measured from the plurality of generated delayed clocks that fall within the one pixel time, and are selected stepwise. As a result, when the delay time difference between the stepwise delayed clocks generated is not constant, the division accuracy of the pixel time can be improved and the high-frequency pixel clock can be followed.

Further, when the pixel time changes due to a change in the resolution of the binary image information, the number of delay clocks to be selected is increased or decreased according to the pixel time. Thereby, it is possible to cope with a change in resolution specifications of a printer, a display, and the like.

An image forming apparatus according to the present invention for realizing the above method comprises: a delay clock generating means for generating a plurality of delay clocks having different delay times stepwise from a reference clock synchronized with a pixel clock; A delay time measuring means for measuring a delay clock corresponding to one pixel time from among the delay clocks, and a delay time selecting means for selecting a required number of delay clocks within the delay time of the measured delay clock. A pulse generating means for generating a pulse having a stepwise different pulse width by a logical operation of each of the delayed clocks and the reference clock, and selecting a pulse having a pulse width corresponding to the input gradation of the multi-valued image information. And a binary image information converting means for outputting as binary image information.

According to the present invention, a large number of generated delay clocks having a short delay time are measured, and a delay clock necessary for dividing a pixel time corresponding to a resolution is selected with high accuracy. Can be easily generated, and can be easily applied to high-frequency multivalued image information.

[0010]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a configuration diagram illustrating a schematic function of an image forming apparatus according to an embodiment. The image forming apparatus according to the present embodiment includes a delay clock generation unit 1, a delay time measurement unit 2, a delay clock selection unit 3, and a pulse generation unit 4.
And the pulse selection means 5.

The operation of the image forming apparatus according to the present embodiment will be described with reference to a time chart of FIG. The reference clock 6 shown in (a) is obtained by dividing the synchronous clock (pixel clock) of one pixel by half. That is, the multilevel image information 11 shown in (y) is input in synchronization with the pixel clock shown in (x).

The delay clock generator 1 generates a plurality of delay clocks 7 having different delay times shown in (b) to (i) from the reference clock 6 shown in (a). FIG. 2 shows eight odd-numbered (7-1, 7-3,...) Out of the 16 delayed clocks 7 generated by the delayed clock generating means 1. The delay times of the eight delay clocks 7 shown in (b) to (i) from the reference clock 6 are denoted by t1 to t8, respectively.

FIG. 3 shows a configuration diagram of the delay clock generating means 1. The delay clock generation means 1 connects 16 buffer gates 13 to 28 in series, and generates 16 delay clocks 7 whose delay times from the reference clock 6 differ stepwise. The number of buffer gates is determined by the relationship between the required number of generated pulses 10 and the delay time of one buffer gate. The delay time per buffer gate is as small as about 5 ns. Therefore, the time of one pixel is 30 ns.
If the pixel frequency is about 33 MHz, the time of one pixel can be divided into six by six delayed clocks in series with six buffer gates. As described above, according to the delay clock generation unit of the present embodiment, by increasing the number of stages of the buffer gate, it is possible to easily obtain a large number of small delay times to be applied to a high-frequency image.

However, the delay time of one buffer gate is not always the same for each buffer gate, but depends on the configuration of the buffer gate, the connection method, environmental conditions, and the like.
That is, although the buffer gate depends on a discrete TTL gate, a gate configuration inside the LSI, and the like, the delay time of each buffer gate is not constant due to the influence of wiring delay, temperature, and the like. For this reason, a delay clock corresponding to one pixel time cannot be fixed and handled. It is necessary to measure a delay clock corresponding to one pixel time at least during a period until the operating temperature is stabilized after the image forming apparatus is started, or for each screen or sheet of the image output apparatus.

The delay time measuring means 2 measures the delay time of the delay clock 7 periodically or irregularly, such as when the apparatus is started up or immediately before the image forming process, by inputting the delay time measuring signal 65. That is, with the falling time t0 of the reference clock 6 as the sampling clock 34, the delay time of the delay clock 7 corresponding to t0 is measured. In the illustrated example, the delay clock 7-11 (t6) and the delay clock 7-13 (t7) in which the state of the delay clock changes from 1 to 0 immediately before and immediately after the time t0 are detected, and this corresponds to t0. The delay time to be performed is set as a delay clock 7-11 (t6), and is output as a delay time measurement value 8.

The delay time selecting means 3 selects a desired number falling within the time of the measured delay time 8 from the generated 16 delay clocks 7. The desired number is determined according to the maximum gradation (resolution) of the input image information or the required halftone of the output image. In the illustrated example, from among the delayed clocks 7-1 to 7-11 that fall within the time of the measured value 8, FIG.
As described above, the six delay clocks 9 are selected and output from the odd-numbered buffer gates so that the difference between the pulse widths of the generated pulses 10 is substantially equal (strictly different from the characteristics of the buffer gates). I have. The method of selecting the delay clock 9 may be, for example, such that the ratio of the pulse widths of the generated pulses 10 is constant, other than equalizing the pulse width difference.

The pulse generating means 4 includes reference clocks 6 and 6
The logic operation of each of the selected delay clocks 9 is performed to generate six pulses 10 shown in (j) to (o) of FIG. The pulse selecting means 5 is a multi-valued (eight-stage) image information 1
1 is input, one of eight pulses including six generated pulses 10 and all white (all 0) and all black (all 1) is selected, and a binary value modulated in the time axis direction is selected. Output as image information 12.

FIG. 4 is a block diagram showing one embodiment of the delay time measuring means 2. The delay time measuring means 2 is constituted by a microcomputer 29. Delay time measurement signal 65
Accordingly, 16 delay clocks 7 are sampled at the falling edge of the reference clock 6, and the delay time t0 shown in FIG. 2, that is, the number of buffer gate stages corresponding to the delay time of one pixel is detected from the sampling result. Here, the number of stages of the buffer gate for generating the delay clock 7-11 shown in (g) = 11 is detected and output as the delay time measurement value 8.

FIG. 5 is a block diagram showing another embodiment of the delay time measuring means 2. The delay time measuring means 2 includes an inverter 30, a latch 31, and an encoder 32.
Latch 3 which starts operation in response to delay time measurement signal 65
Reference numeral 1 denotes a rising edge of a sampling clock 34 obtained by inverting the reference clock 6, latches 16 delayed clocks 7, and outputs the latched data 33. Encoder 3
2 encodes the latch data 33, that is,
The data is converted into 4-bit binary data and output as a measured delay time 8. In the case of the time chart of FIG. 2, the measured delay time 8 is (1011) or (1100).
(11 or 12 in decimal). In this example,
The delay time measuring means 2 does not require a program.

FIG. 6 is a block diagram of the delay clock selecting means 3. The delay time selecting means 3 comprises a γ setting means 40, a delay calculating means 41, and a delay selecting means 42. The delay calculating means 41 calculates the delay time measurement value 8 to calculate the delay time of each gradation assigned to a plurality of gradations. The delay selecting means 42 selects the delay clocks 7 corresponding to the delay times of the respective gradations based on the operation value 43 of the delay operation means 41 and outputs the selected delay clocks 9.

The delay time of each gradation can be set as shown in FIG. FIG. 7 is an example of the γ characteristic curve of the γ setting means 40 shown in FIG. 6, and three types of curves can be selected. Thereby, the delay clocks 9 having different γ characteristics can be easily obtained.

FIG. 8 is a block diagram of the pulse generating means 4. The pulse generation means 4 includes eight exclusive OR gates 50 to 57. The eight exclusive OR gates 50 to 57 execute a logical operation of the reference clock 6 and the eight selected delay clocks 9 to generate eight pulses 10.

FIG. 9 is a block diagram of the pulse selecting means 5. The pulse selecting means 5 includes a selector 60. 3
One of the eight-step generated pulses 10-1 to 10-8 is selected according to the bit, that is, the 8-level multi-valued image information 11, and the selected pulse 10 is output as the binary image information 12. By the above operation, the multi-level image information 1 of 8 gradations
1 is converted into binary image information 12 that has been pulse-width modulated to eight gradations in the time axis direction.

According to the present embodiment, since a binary image signal that is pulse-width modulated in multiple stages in synchronization with a pixel clock can be easily generated, it can be easily applied to a multivalued image signal having a high pixel clock frequency. In addition, since the delay clock that is the source of the multi-step pulse width is selected by measuring the delay time, the division accuracy of the pixel time corresponding to the resolution can be improved, and a high-quality image can be formed.

FIG. 12 shows a schematic configuration of an image forming system in which the image forming apparatus of the present invention is applied to a laser printer. This system includes an image forming apparatus 80, a personal computer 81, a laser printer 82, and a control device 83.

The controller 83 exchanges various signals with the laser printer 82, for example, inputs a signal corresponding to a one-line synchronization signal to generate a pixel clock, and divides the pixel clock by １ ／ to generate a reference clock. 6 is output. Further, it outputs a delay time measurement signal 65 at the resolution 75 of the laser printer 82 and the timing at which measurement is required.

The image forming apparatus 80 generates a plurality of delay clocks starting from the reference clock 6, measures a delay clock corresponding to one pixel time at the timing of the delay time measurement signal 65, and converts the one pixel time into a resolution. The number of delay clocks necessary for division corresponding to 75 is selected, and a pulse having a pulse width corresponding to the delay time of each selected delay clock is generated. On the other hand, according to the gradation of the multi-level image signal 11 input from the personal computer 81, a pulse having a corresponding pulse width is output as a binary image signal 12 to the laser printer 82. The printer 82 creates and records a halftone image based on the pulse width modulated binary image signal 12.

In the above description, the image source is a personal computer, but a digital camera, an image scanner, or the like that outputs a multi-valued image signal can be used. The image output device may be a printer using another recording method such as an ink jet printer, a thermal printer, or a display.

Next, as another embodiment of the present invention, an image forming apparatus capable of coping with a change in resolution of multi-valued image information will be described. FIG. 10 is a configuration diagram of an image forming apparatus according to another embodiment. The same components as those in FIG. 1 are denoted by the same reference numerals. The difference from FIG. 1 is that a clock selection unit 70, a second delay time selection unit 71, and a third delay time selection unit 72 are added.

The operation of the image forming apparatus will be described with reference to a time chart of FIG. According to the resolution designation signal 73, the time of one pixel in FIG.
10 (resolution B). For example, when the resolution is A, (a), (d), (l)
The resolution corresponds to (p), (q), and (r) of B.

The clock selecting means 70 receives the first reference clock 74 and the second reference clock 75, selects one of them according to the resolution designation signal 73, and selects the selected reference clock 76.
Output as Each pulse width of the first reference clock 74 and the second reference clock 75 corresponds to one pixel time at each resolution. The second delay clock selecting means 71, like the delay clock selecting means 3,
A desired plurality of delay clocks 77 are selected and output from the plurality of delay clocks 7 based on the delay time measurement value 8. The third delay clock selecting means 72 outputs a resolution specifying signal 73
, One of the delay selection clock 9 and the second delay selection clock 77 is selected and input to the pulse generation means 4 as the third selection delay clock 78.

According to the present embodiment, the selection reference clock and the third delay selection clock are selected in accordance with the resolution. The image information 12 has the same ratio of pulse width to the time of one pixel, so that an image of the same quality can be formed.

[0033]

According to the image forming apparatus of the present invention, even if the image frequency of the multi-level image signal is increased, a binary image signal that is pulse-width modulated in multiple stages in synchronization with the pixel clock can be generated. A high-quality halftone image can be formed at high speed.

Further, since the delay time of the delay clock, which is the source of the pulse width, is measured on-line and its fluctuation is measured, a large number of delay clocks with a small delay time can be easily generated by a buffer gate or the like, and the high frequency It can be easily applied to image formation of multi-valued image information.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of an image forming apparatus according to an embodiment of the present invention.

FIG. 2 is a time chart illustrating an operation of the image forming apparatus of FIG. 1;

FIG. 3 is a configuration diagram of a delay clock generation unit of FIG. 1;

FIG. 4 is a configuration diagram of a delay time measuring unit according to an embodiment of FIG. 1;

FIG. 5 is a configuration diagram according to another embodiment of the delay time measuring means of FIG. 1;

FIG. 6 is a configuration diagram of a delay clock selection unit of FIG. 1;

FIG. 7 is a γ characteristic diagram of the γ setting means shown in FIG. 6;

FIG. 8 is a configuration diagram of a pulse generation unit in FIG. 1;

FIG. 9 is a configuration diagram of a pulse selection unit in FIG. 1;

FIG. 10 is a schematic configuration diagram of an image forming apparatus according to another embodiment of the present invention.

FIG. 11 is a time chart illustrating the operation of the image forming apparatus of FIG. 10;

FIG. 12 is a schematic diagram of an image creating system to which the image forming apparatus of the present invention is applied.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Delay time generation means, 2 ... Delay time measurement means, 3 ... Delay clock selection means, 4 ... Pulse generation means, 5 ... Pulse selection means, 6 ... Reference clock, 7 ... Delay clock, 8 ...
Delay time measurement value, 9: selected delay clock, 10: generated pulse, 11: multi-valued image information, 12: binary image information.

 ────────────────────────────────────────────────── ─── Continuing from the front page (72) Inventor Asahiko Kikuchi 2-6-1 Otemachi, Chiyoda-ku, Tokyo Nichiko Koki Co., Ltd.

Claims (5)

[Claims] 1. An image forming method for converting multi-valued image information into binary image information modulated in a time axis direction, wherein a plurality of delay clocks having delay times different in stages are generated in synchronization with a pixel clock. Then, the number of delay clocks necessary to divide one pixel time is selected from among them, a pulse having a time width corresponding to the delay time of the selected delay clock is generated, and the input level of the multi-valued image information is generated. An image forming method comprising: outputting a pulse having a corresponding time width according to a tone as binary image information. 2. The method according to claim 1, wherein the required number of the delayed clocks is measured from those generated within the one pixel time from among the plurality of generated delayed clocks, and is selected in a stepwise manner. An image forming method comprising: 3. The method according to claim 1, wherein when the pixel time changes due to a change in resolution of the binary image information, the number of delay clocks to be selected is increased or decreased according to the pixel time. Image forming method. 4. An image forming apparatus for converting multi-valued image information into binary image information modulated in a time axis direction, wherein a plurality of delay times differing stepwise from a reference clock synchronized with a pixel clock. A delayed clock generating means for generating a delayed clock of
A delay time measuring means for measuring a delay clock corresponding to a pixel time; a delay clock within a delay time of the measured delay clock, and a delay time selecting means for selecting a required number; A pulse generation means for generating a pulse having a stepwise different pulse width by a logical operation of each of the reference clocks and a pulse having a pulse width corresponding to the input gradation of the multi-valued image information;
An image forming apparatus, comprising: binary image information conversion means for outputting as value image information. 5. An input means for inputting multi-valued image information, an image forming apparatus for pulse width modulating the multi-valued image information and outputting it as binary image information, and displaying or recording the binary image information. In the image forming system including an output device, the image forming device generates a pulse having a time width that can correspond to the resolution of the output device and has a different time width from a pixel clock based on a synchronization signal of one line of the output device. Means for modulating the input gradation of the multi-valued image information by pulse width modulation.