JPH10284701A - Manufacture of semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To downsize the chip size, while increasing the storage capacity by setting first and second conductivity types of MOSFETs, according to a minimum processing dimensions of the elements, and also forming a mask layer, while separating it at the space part to a memory array part. SOLUTION: A space part is provided at the boundary between a peripheral circuit part 14 and a memory cell array part 15, and a first conductivity type of MOSFET and a second conductivity type of MOSFET constituting the peripheral circuit parts 14 are set, according to a minimum processing dimensions of the elements, where the dimensional slippage to form the mask layers used for the ion implantation is ignored. Then, the mask layer used for the first conductivity type of MOSFET which is used for the ion implantation to form the second conductivity type of MOSFET is made, while being separated at the space part to the memory array part 15 constituted of the peripheral circuit part 14 and the first conductivity type of MOSFET. Thus, the semiconductor storage device can be highly integrated, while preventing the gate insulating film of the first conductivity type of MOSFET from electronic breakdown.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor memory device, and more particularly to a P-channel type MO of a peripheral circuit provided in a memory cell array of a dynamic RAM (random access memory) having a large storage capacity.
The present invention relates to an effective technique used for a mask layer forming technique for ion implantation for forming an SFET and an N-channel MOSFET.

[0002]

2. Description of the Related Art Only a required block in which a memory cell to be selected is provided is operated, a memory area to be operated is reduced as much as possible to achieve low power consumption, and a sub-word line to which a memory cell is connected is selected. In order to increase the speed, a split word line system has been proposed in which a plurality of sub-word lines are provided for connecting memory cells to a main word line. An example of such a divided word line system is disclosed in Japanese Patent Application Laid-Open No. 2-158995. In the above publication, the main word line is referred to as a pre-word line, and the sub-word lines are referred to as word lines.

[0003]

In the above-mentioned divided word line system, a complementary bit line arranged so as to intersect with a word line is also divided through a sense amplifier. The memory cells are arranged in a matrix of the divided word lines and the divided bit lines, and the sense amplifiers and the word drivers for selecting the divided word lines are arranged in the periphery thereof. For example, in a dynamic RAM such as 64 Mbits, the whole is divided into four memory blocks, and each memory block forms as many as 8 × 16 memory cell arrays.

FIG. 6 shows a configuration diagram of a 64-Mbit memory cell array and its peripheral circuits developed prior to the present invention. The figure shows four memory cell arrays (memory mats) MMAT as representatives, two sense amplifiers SA and sub-word drivers SWD provided in the periphery thereof. The sense amplifier SA and the sub-word driver in the peripheral circuit section are an N-channel type MO.
CMO composed of SFET and P-channel MOSFET
The P-channel MOSFET and the N-channel MOSFET are configured as shown in the enlarged view of FIG.
In consideration of the mask shift of a mask layer used for ion implantation for forming an OSFET, a margin such as 2L 'is provided from the center line shown by a dotted line in FIG. A MOSFET and an N-channel MOSFET are formed. For example, when forming a P-channel MOSFET,
A mask layer is formed on the side of the N-channel MOSFET as indicated by hatching in the enlarged view of FIG.

In the present inventors, although the margin itself is small due to the mask layer for forming the P-channel MOSFET and the N-channel MOSFET separately, in the dynamic RAM having a large storage capacity as described above. Since a large number of memory cell array portions are stacked vertically and horizontally as described above, the one small mask alignment margin increases in proportion to the number of the divided memory cell arrays, and becomes unignorable. I noticed.

An object of the present invention is to provide a method of manufacturing a semiconductor memory device which realizes a large chip with a large memory capacity. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0007]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, in the method for manufacturing a semiconductor memory device, a space portion is provided at the boundary between the peripheral circuit portion and the memory cell array portion, and the first conductivity type MO constituting the peripheral circuit portion is provided.
The SFET and the second conductivity type MOSFET are set according to the minimum processing size of the element ignoring the dimensional deviation forming the mask layer used for the ion implantation, and the second
A mask layer formed in a first conductivity type MOSFET portion used for ion implantation for forming a conductivity type MOSFET is separated by a space portion between the peripheral circuit portion and a memory cell array portion formed by the first conductivity type MOSFET. To form.

[0008]

FIG. 1 is a schematic layout diagram showing one embodiment of a dynamic RAM according to the present invention. In the figure, of the circuit blocks constituting the dynamic RAM, a portion related to the present invention is shown so as to be understood. It is formed on one semiconductor substrate.

In this embodiment, although not particularly limited, the memory array is divided into four as a whole. Two memory arrays are divided into two on the left and right sides with respect to the longitudinal direction of the semiconductor chip, and an address input circuit, a data input / output circuit, an input / output interface circuit including a bonding pad row, a power generation circuit, and the like are provided in the central portion 14. Can be Column decoder regions 13 are arranged in portions of both sides of the central portion 14 in contact with the memory array.

As described above, in each of the four memory arrays divided into two on the left and right sides and two on the upper and lower sides with respect to the longitudinal direction of the semiconductor chip, the main row decoder is disposed at the upper and lower central parts in the longitudinal direction. An area 11 is provided. Main word driver regions are formed above and below the main row decoder, and drive the main word lines of the memory array divided vertically.
Hereinafter, as shown in the enlarged view of the memory cell array,
With the memory cell array 15 interposed therebetween, the sense amplifier region 16,
The sub word driver region 17 is formed.
An intersection between the sense amplifier region and the sub-word driver region is an intersection region 18. The sense amplifiers provided in the sense amplifier area are configured by a shared sense method, and except for the sense amplifiers arranged at both ends of the memory cell array, complementary bit lines are provided on the left and right around the sense amplifier. Are selectively connected to the complementary bit lines of the memory cell array.

Although not particularly limited, the dynamic RAM of this embodiment has a storage capacity of about 64 M (mega) bits. As described above, four memory arrays are divided on the left and right sides with respect to the longitudinal direction of the semiconductor chip, and the address input circuit, data input / output circuit, etc. Are provided.

As described above, the memory arrays divided into four on the left and right sides in the longitudinal direction of the semiconductor chip are arranged in groups of two. As described above, the two memory arrays arranged in groups of two each have the main word driver 11 arranged at the center thereof. The main word driver 11 is provided corresponding to the two memory arrays that are divided up and down around the main word driver 11. The main word driver 11 generates a selection signal of a main word line extended so as to penetrate the one memory array.

One memory cell array 15 shown as an enlarged view has 256 sub-word lines (not shown),
The number of complementary bit lines (or data lines) orthogonal thereto is 256.
Paired. In the one memory array, 16 memory cell arrays 15 are provided in the word bit line direction. Therefore, the sub word lines as a whole are provided for about 4K, and 8 sub word lines are provided in the word line direction. A total of about 2K is provided. Since a total of eight such memory arrays are provided, a total of 8 ×
It has a large storage capacity such as 2K × 4K = 64M bits.

The one memory array is divided into eight in the main word line direction. A sub-word driver (sub-word line driving circuit) 17 is provided for each of the divided memory cell arrays 15. The sub-word driver 17 is divided into の 長 of the length of the main word line, and forms a sub-word line selection signal extending in parallel with the length. In this embodiment, in order to reduce the number of main word lines, in other words, to reduce the wiring pitch of the main word lines, there is no particular limitation. Are arranged four sub-word lines. In order to select one sub-word line from among the sub-word lines divided into eight in the main word line direction and four in the complementary bit line direction, a sub-word selection driver is used. Be placed. This sub-word selection driver is extended in the arrangement direction of the sub-word drivers.
A selection signal for selecting one of the sub-word selection lines is formed.

Thus, focusing on the one memory array, in a sub-word driver corresponding to one memory cell array including a memory cell to be selected among eight memory cell arrays allocated to one main word line, As a result of selecting one sub-word selection line, one sub-word line is selected from 8 × 4 = 32 sub-word lines belonging to one main word line.
As described above, 2K (2048) memory cells are provided in the main word line direction, so that 2048/8 = 256 memory cells are connected to one sub-word line. Although not particularly limited, in a refresh operation (for example, a self-refresh mode),
Eight sub-word lines corresponding to one main word line are selected.

As described above, one memory array has a storage capacity of 4K bits in the complementary bit line direction. However, if as many as 4K memory cells are connected to one complementary bit line, the parasitic capacitance of the complementary bit line increases, and a signal level that is read out cannot be obtained due to the capacitance ratio with a fine information storage capacitor. To
It is also divided into 16 in the complementary bit line direction. That is,
The complementary bit line is divided into 16 by the sense amplifier 16 indicated by a thick black line. Although not particularly limited, the sense amplifiers 16 are configured by a shared sense system, and are provided at both ends of the memory array.
Except for the above, complementary bit lines are provided on the left and right with respect to the sense amplifier 16, and are selectively connected to one of the left and right complementary bit lines.

FIG. 2 is a main block diagram for explaining the relationship between the main word lines and the sub word lines of the memory array. FIG. 14 shows two main word lines MWL0 and MWL for explaining a sub word line selecting operation.
WL1 is shown as a representative. These main word lines MWL0 are selected by a main word driver MWD0. The other main word line MWL1 is similarly selected by a main word driver similar to the above.

The one main word line MWL0 has:
Eight sets of sub-word lines are provided in the extending direction. FIG. 2 exemplarily shows two sets of the sub-word lines as representatives. The sub word line is even 0 to
A total of eight sub-word lines 6 and odd numbers 1 to 7 are alternately arranged in one memory cell array. Except for even numbers 0 to 6 adjacent to the main word driver and odd numbers 1 to 7 arranged on the far end side (opposite side of the word driver) of the main word line, the sub word drivers arranged between the memory cell arrays are , And a selection signal for the sub-word lines of the left and right memory cell arrays centered at the center.

Thus, although the memory cell array is divided into eight blocks as described above, the sub word lines corresponding to the two memory cell arrays are simultaneously selected by the sub word driver SWD substantially as described above. Specifically, the memory array is divided into four blocks. In the configuration in which the sub-word lines SWL are divided into even numbers 0 to 6 and even numbers 1 to 7 as described above, and the sub-word drivers SWD are arranged on both sides of the memory block, respectively, the sub-word lines SWD are densely arranged in accordance with the arrangement of the memory cells. The substantial pitch of the SWL can be relaxed twice in the sub-word driver SWD.
WD and sub-word line SWL can be efficiently laid out on a semiconductor chip.

In this embodiment, the sub-word driver SWD supplies a selection signal from the main word line MWL to four sub-word lines 0 to 6 (1 to 7) in common. A sub-word select line FXB for selecting one sub-word line from the four sub-word lines is provided. The sub-word selection lines are composed of eight lines FXB0 to FXB7, of which even-numbered FXB0 to FXB6 are supplied to the even-numbered sub-word drivers 0 to 6, and odd-numbered FXB1 to FXB7 are odd-numbered sub-word drivers 1 to 7 of the odd-numbered columns. Supplied to

The sub word select lines FXB0 to FXB7 are
At the periphery of the array, a first sub-word select line formed by a second metal wiring layer M2 and extending in parallel with main word lines MWL0 to MWLn also formed by the second metal wiring layer M2; , And a second sub-word selection line extending in a direction orthogonal thereto. Although not particularly limited, the second sub-word selection line is formed by a third-layer metal wiring layer M3 so as to intersect with the main word line MWL.

The sub-word driver SWD includes a main word line M as one of them is illustratively shown.
The input terminal is connected to WL, and the sub-word line S is connected to the output terminal.
P-channel MOSFET Q1 connected to WL and N
First CMOS comprising channel type MOSFET Q2
An inverter circuit, provided between the sub-word line SWL and the ground potential of the circuit, and connected to the sub-word selection signal FX;
It is composed of a switch MOSFET Q3 receiving B.
A second CMOS inverter circuit N1 for forming an inverted signal of the sub-word selection signal FXB is provided, and its output signal is supplied to a source terminal of a P-channel MOSFET Q1 which is an operating voltage terminal of the first CMOS inverter circuit. I do. Although not particularly limited, the second CMOS inverter circuit N1 is formed in the intersection area of FIG. 1, and is commonly used in correspondence with the plurality of sub-word drivers SWD.

In the above configuration, the main word line MW
When L is a high level such as a high voltage VPP corresponding to the word line selection level, the N-channel MOSFET Q2 of the first CMOS inverter circuit is turned on, and the sub-word line SWL is set to a low level such as the ground potential of the circuit. To At this time, even if the sub-word selection signal FXB becomes a selection level such as a low level such as the VPP and the output signal of the second CMOS inverter circuit N1 is set to a selection level corresponding to the VPP, the main word line MWL is not Since the P-channel MOSFET Q1 is in the OFF state due to the non-selection level, the sub-word line SWL is set to the non-selected state due to the ON state of the N-channel MOSFET Q2.

When the main word line MWL is at a low level such as the ground potential of a circuit corresponding to the non-selection level of the word line, the N-channel MOSFET Q2 of the first CMOS inverter circuit is turned off, and the P-channel MOSFET Q2 Is turned on. At this time,
If the sub-word selection signal FXB is a selection level such as the low level such as VPP, the output signal of the second CMOS inverter circuit N1 is set to the selection level corresponding to VPP, and the sub-word line SWL is set to the selection level such as VPP. To If the sub-word selection signal FXB is a non-selection level such as a high level, the second CMO
The output signal of the S inverter circuit N2 becomes low level,
At the same time, the N-channel MOSFET Q3 is turned on, and the sub-word line SWL is set to the low-level non-selection level.

FIG. 3 is a main part circuit diagram of one embodiment of the sense amplifier section of the dynamic RAM according to the present invention. FIG. 2 exemplarily shows a sense amplifier SA1 arranged between memory mats (same as the memory block) MAT0 and MAT1 and circuits related thereto. The memory mat MAT1 is shown as a black box, and has a sense amplifier SA provided at an end.
0 is also shown as a black box.

Four dynamic memory cells are exemplarily shown as representatives corresponding to the sub-word lines SWL provided in the memory mat MMAT0. The dynamic memory cell includes an address selection MOSFET Qm and an information storage capacitor Cs. Address selection M
The gate of the OSFET Qm is connected to the sub-word line SWL, the drain of the MOSFET Qm is connected to the bit line, and the source is connected to the information storage capacitor Cs. The other electrode of the information storage capacitor Cs is shared and receives a plate voltage. The above sub word line SWL
Is a high voltage VPP higher than the high level of the bit line by the threshold voltage of the address selection MOSFET Qm. For example, when the operation is performed at a power supply voltage VCC of a sense amplifier described later, the high level given to the bit line is equal to the power supply voltage V CC.
Since the level is set to a level corresponding to CC, the high voltage VPP corresponding to the selected level of the word line is set to VCC + Vth.

The pair of complementary bit lines are arranged in parallel as shown in the figure, and are appropriately crossed as necessary to balance the bit line capacitance. Such complementary bit lines are connected to input / output nodes of a unit circuit of the sense amplifier by shared switch MOSFETs Q1 and Q2. The unit circuit of the sense amplifier is an N-channel type MO in which a gate and a drain are cross-connected to form a latch.
SFET Q5, Q6 and P-channel MOSFET Q
7, Q8. N-channel type MOSFET
The sources of Q5 and Q6 are connected to a common source line CSN. The sources of the P-channel MOSFETs Q7 and Q8 are connected to a common source line CSP. The common source lines CSN and CSP have power switches MOSF of N-channel MOSFET and P-channel MOSFET.
ET are provided, and the power switch MOSFET is turned on by an activation signal of the sense amplifier, and a voltage supply required for operation of the sense amplifier, for example, VC
Supply C and VSS.

A MOSFET Q11 for short-circuiting a complementary bit line is provided at the input / output node of the unit circuit of the sense amplifier.
And a precharge circuit comprising switch MOSFETs Q9 and Q10 for supplying a half precharge voltage HVC to the complementary bit line. These MOSFET Q9
The precharge signal PCB is commonly supplied to the gates of Q11 to Q11.

The MOSFETs Q12 and Q13 form a column switch that is switch-controlled by a column selection signal YS. In this embodiment, one column selection signal YS
Thus, four pairs of bit lines can be selected. That is, a similar column switch is provided in the sense amplifier SA0 indicated by a black box. As described above, the two sense amplifiers SA0 and SA1 sandwich the memory mat MMAT0 to divide the complementary bit lines into the even-numbered bit lines and the odd-numbered bit lines so that the sense amplifiers SA0 and SA1 correspond to each other. is there. Therefore, the column selection signal YS has a total of four bits corresponding to the two pairs of bit lines exemplarily shown on the sense amplifier SA1 side and the remaining two pairs of bit lines (not shown) provided on the sense amplifier SA0 side. A pair of complementary bit lines can be selected. These two pairs of complementary bit lines are connected to the two pairs of common input / output lines I / O via the column switch.
Connected to.

The sense amplifier SA1 is connected to the memory mat MMA via shared switch MOSFETs Q3 and Q4.
It is connected to the complementary bit line of the similar odd column of T1. The complementary bit lines of the even-numbered columns of the memory mat MMAT1 are connected to a sense amplifier SA2 (not shown) arranged on the right side of the memory mat MMAT1 by the shared switch MOSFET.
Shared switch MOSFET corresponding to Q1 and Q2
Connected via With such a repetitive pattern, the memory array is connected to a sense amplifier provided between memory mats (the memory blocks) formed by dividing the memory array. For example, when the sub-word line SWL of the memory mat MMAT0 is selected, the shared switch MOSFET on the right side of the sense amplifier SA0 and the sense amplifier S
The left-side shared switch MOSFET of A1 is turned on. However, in the sense amplifier SA0 at the end, only the right shared switch MOSFET is provided. The signal SHRL is a left shared selection signal and a SHRR right shared selection signal.

FIG. 4 is a structural diagram for explaining an embodiment of a mask layer used for ion implantation for explaining a method of manufacturing the divided memory cell array portion and its peripheral circuit. . In this embodiment, a space is provided between the memory cell array (memory mat) MMAT and the sub-word driver SWD and the sense amplifier SA which are peripheral circuits.

P-channel type MOSF in the peripheral circuit section
When the ET is formed, a P-type impurity is ion-implanted.
A mask layer as shown by hatching is formed on the N-channel MOSFET in order to prevent it from being introduced into the SFET. Conversely, when an N-type impurity is ion-implanted in order to form an N-channel MOSFET, a max layer is formed on the P-channel MOSFET to prevent the ion implantation. In this embodiment, the space L between the P-channel MOSFET and the N-channel MOSFET is provided without providing a margin in consideration of the displacement of the mask layer for separately producing the P-channel MOSFET and the N-channel MOSFET. Is set according to the minimum processing size.

Therefore, the P-channel type MOSF
The mask layer for forming the ET may be shifted to the gate electrode FG side of the P-channel MOSFET due to a positional shift. However, N-channel type MOSFE
On the T side, a space is provided between the memory cell array portion having a larger area and the peripheral circuit portion, and the mask layer is separated here. Therefore, when the P-type impurity is ion-implanted, the mask layer has a potential due to the ionized P-type impurity, but has a large area with the mask layer of the peripheral circuit portion where the gate portion FG is exposed. Since the mask on the side of the memory cell array that accumulates a large amount of charge is separated, gate insulation breakdown occurs in a MOSFET in which P-type impurities are implanted into the gate FG due to a shift in the mask layer in the peripheral circuit section. The problem that it occurs does not occur.

When ion-implanting an N-type impurity to form an N-channel MOSFET, what is masked is the P-channel MOSFET in the peripheral circuit section.
There is no danger that the gate insulating film of the P-channel MOSFET, which is a mask layer having a small area formed thereon and which is masked by the ions captured by the mask layer, is broken down.

According to the estimation by the inventor of the present application, by applying the present invention to a dynamic RAM of 64 Mbits as described above, the space provided between the memory cell array section and the peripheral circuit section is subtracted. Also X and Y
The chip size can be reduced by about 90 μm in the direction.

FIG. 5 is a schematic sectional view of the element structure of a dynamic RAM to which the present invention is applied. Although not particularly limited, a P-type well region PW is formed in the outermost peripheral portion of the semiconductor chip, and a P-type region for ohmic contact formed by the same diffusion layer as the source and drain of the P-channel MOSFET is formed therein. Formed,
The ground line is provided in such a P-type region, and a ground potential PVS1 of the circuit is applied from a bonding pad or the like. Address selection MOSFET constituting the memory cell MC
Is surrounded by an N-type well region NW, which is also used as the space, and a deep N-type well region DW is formed therebelow to form a semiconductor substrate P-Su.
b, a negative substrate back bias voltage VBB is applied. Although not particularly limited, a boosted voltage VPP corresponding to a selected level of a word line is applied to the N-type wells NW and DW for isolation. When only the memory cell MC is formed in the separated P-type well region, if the highest voltage supplied to the source and drain of the address selection MOSFET is VCL, the applied V
CL or power supply voltage VCC is applied.

The P-channel MOSFET (P-SA) constituting the sense amplifier SA is formed in the N-type well region NW. When the operating voltage of the sense amplifier is set to the voltage VCL lower than the power supply voltage, the N-type well region NW may be configured to supply the VCL instead of the power supply voltage VCC. An N-channel MOSFET (N-SA) constituting the sense amplifier is formed in the P-type well region PW. The ground potential VSS of the circuit is applied to the P-type well region PW from the substrate P-Sub. Similarly, each of the P-channel MOSFETs constituting the peripheral circuit Peri and the peripheral circuit IO includes an N-type well region N
W, and the N-type well region has a power supply voltage VC.
C is applied. Each N-channel MOSFET constituting the peripheral circuit Peri and the peripheral circuit IO is formed in the P-type well region PW, and the ground potential VSS of the circuit is applied to the N-type well region.

In the figure, the N-channel MOSFET and the N-channel MOSFET of the peripheral circuit Peri are formed according to the minimum processing size in accordance with the memory cell array arranged regularly. On the other hand, unlike the input / output circuit IO, the arrangement of the memory cell array is not restricted and the portion where the arrangement is free has a relatively large area allowance. The element dimensions and intervals are set with allowance in consideration.

The operation and effect obtained from the above embodiment are as follows. (1) In the method of manufacturing a semiconductor memory device, a space is provided at a boundary between a peripheral circuit section and a memory cell array section, and a first conductivity type MOSFET and a second conductivity type MOSFET constituting the peripheral circuit section are ion-implanted. The second conductive type MOSFET is set according to the minimum processing size of the element ignoring the dimensional deviation forming the mask layer used for the
Forming a mask layer formed in a first conductivity type MOSFET portion used for ion implantation for forming a semiconductor device in a space portion between the peripheral circuit portion and a memory cell array portion formed of the first conductivity type MOSFET. By doing so, it is possible to obtain an effect that high integration can be realized while preventing the gate insulating film of the first conductivity type MOSFET from electrostatic breakdown.

(2) By applying to a dynamic RAM of a word line division system and a bit line division system,
Since the memory cell array is divided into many parts, the effect of reducing the size of the peripheral circuit portion can be increased.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention of the present application is not limited to the embodiment, and various modifications can be made without departing from the gist of the invention. Needless to say. For example, the configuration of a memory array or the arrangement of a plurality of memory arrays mounted on a semiconductor chip can employ various embodiments according to the storage capacity and the like. The present invention includes a main word line and a sub-word line, a memory cell array portion is formed of the same conductivity type MOSFET, and a divided word line type dynamic RAM or static RA.
It can be widely used for manufacturing various semiconductor memory devices such as M.

[0042]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, in the method for manufacturing a semiconductor memory device, a space portion is provided at the boundary between the peripheral circuit portion and the memory cell array portion, and the first conductivity type MO constituting the peripheral circuit portion is provided.
The SFET and the second conductivity type MOSFET are set according to the minimum processing size of the element ignoring the dimensional deviation forming the mask layer used for the ion implantation, and the second
A mask layer formed in a first conductivity type MOSFET portion used for ion implantation for forming a conductivity type MOSFET is separated by a space portion between the peripheral circuit portion and a memory cell array portion formed by the first conductivity type MOSFET. By forming the first conductive type MOSFET, high integration can be realized while preventing the gate insulating film of the first conductivity type MOSFET from electrostatic breakdown.

[Brief description of the drawings]

FIG. 1 is a layout diagram showing one embodiment of a dynamic RAM according to the present invention.

FIG. 2 is a main block diagram for explaining a relationship between a main word line and a sense amplifier of the memory array of FIG. 1;

FIG. 3 is a main part circuit diagram showing one embodiment of a sense amplifier section of the dynamic RAM according to the present invention.

FIG. 4 is a configuration diagram for explaining an embodiment of a mask layer used for ion implantation for explaining a method of manufacturing the divided memory cell array section and its peripheral circuit.

FIG. 5 is a sectional view of an element structure for explaining a dynamic RAM to which the present invention is applied.

FIG. 6 is a configuration diagram for explaining a mask layer used for ion implantation for describing a method of manufacturing a memory cell array portion and peripheral circuits developed prior to the present invention.

[Explanation of symbols]

10: memory chip, 11: main row decoder area,
12: Main word driver area, 13: Column decoder area, 14: Peripheral circuit, bonding pad area, 1
5: memory cell array, 16: sense amplifier area, 17
... sub word driver area, 18 ... intersection area, Q1-Q
13 ... MOSFET, CSP, CSN ... Common source line,
YS: column selection signal, HVC: half precharge voltage, SHRL, SHRR: shared selection line, I / O ...
Input / output lines, MMAT: memory cell array (memory mat), SWD: subword driver, SA: sense amplifier.

 ──────────────────────────────────────────────────の Continued on the front page (72) Inventor Tsutomu Takahashi 2326 Imai, Ome-shi, Tokyo Inside the Hitachi, Ltd.Device Development Center (72) Inventor Atsushi Tanaka 2326 Imai, Ome-shi, Tokyo Device Development Center, Hitachi, Ltd. (72) Inventor ▲ Taka ▼ Yasushi Hashi 5--20-1, Kamimizu Honcho, Kodaira-shi, Tokyo Inside Semiconductor Division, Hitachi, Ltd. (72) Inventor Shunichi Sukekawa 2350 Kihara, Miura-mura, Inashiki-gun, Ibaraki Nippon Texas・ Instruments Co., Ltd. In company

Claims (3)

[Claims] 1. A memory cell array section in which a plurality of memory cells each composed of a first conductivity type MOSFET are regularly arranged, and a first conductivity type MOSFET provided in the periphery of the memory cell array section. 2-conductivity type MOSFE
In a method of manufacturing a semiconductor memory device including a peripheral circuit portion constituted by T, a space portion is provided at a boundary between the peripheral circuit portion and a memory cell array portion, and a first conductivity type MOS constituting the peripheral circuit portion is provided.
The FET and the second conductivity type MOSFET are set in accordance with the minimum processing size of the element ignoring a dimensional deviation for forming a mask layer used for the ion implantation, and are used for ion implantation for forming the second conductivity type MOSFET. A method of manufacturing a semiconductor memory device, comprising: forming a mask layer formed in a first conductivity type MOSFET portion to be separated by a space portion of the peripheral circuit portion and a memory cell array portion. 2. The method according to claim 1, wherein the memory cell is a dynamic memory cell including an N-channel type address selection MOSFET and an information storage capacitor. 3. The semiconductor memory device according to claim 1, wherein said semiconductor memory device has a main word line, a length divided in an extension direction of said main word line, and a plurality of main word lines in a direction of complementary bit lines intersecting said main word line. The sub-word line arranged and connected to the plurality of memory cells, and the complementary bit line are divided into a plurality by a sense amplifier, and the one memory cell array is divided by the divided complementary bit line and the sub-word line. And the memory cells are arranged in a grid pattern on the semiconductor substrate corresponding to the number of divisions on the semiconductor substrate. The peripheral circuit section selects the sense amplifier and the sub word line. 3. The method for manufacturing a semiconductor memory device according to claim 1, further comprising a sub-word driver that performs the operation.