JPH10284602A - Semiconductor device and manufacture therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce dielectric constant and improve adhesion with a plane to be coated by forming an interlayer insulating film on a wiring layer, forming a space between adjoining SiO2 particles having a grain diameter within a specified range in the interlayer insulating film and setting its space rate to be within a specified range. SOLUTION: An interlayer insulating film 10 has a structure filled with silica (SiO2 ) particles 2, which are formed to have a diameter of 5-50 nm by hydrolyzing alkoxide, and the adjoining silica particles 2 are bonded by a bonding part 3 which is composed of silica. A bonding part 3 forms a neck part having a reduced diameter between the adjoining silica particles 2, and as a result, a void 4 surrounded by three or more silica particles 2 is formed in the interlayer insulating film 10. The void rate of the space 4 is set within a range of 13-42%. Thus, the dielectric constant is reduced, and adhesion with a plane to be coated is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to a semiconductor device and its manufacture, and more particularly to a semiconductor device having an interlayer insulating film having a low dielectric constant suitable for high-speed operation and a method of manufacturing the same.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit device in which a large number of semiconductor devices are integrated, a semiconductor integrated circuit device which performs a desired operation by electrically connecting a large number of semiconductor devices formed on a single substrate is known. To form it, a multilayer wiring structure is used. In the multilayer wiring structure, a wiring pattern forming the first layer is covered with an interlayer insulating film, and a wiring pattern of a second layer is formed on the interlayer insulating film. Further, a second-layer interlayer insulating film may be formed on the second-layer wiring pattern, and a third-layer wiring pattern may be formed thereon.

[0003] When such a multilayer wiring structure is applied to a logic integrated circuit or a high-speed memory device which requires high-speed operation, it is desirable that the dielectric constant of the insulating film forming the interlayer insulating film is as low as possible. In particular, in ultra-miniaturized semiconductor devices having a rule of 0.3 μm or less, an increase in impedance due to electrostatic induction between wiring patterns occurs due to a narrow wiring interval, and as a result, serious problems such as a delay in response speed and an increase in power consumption. Occurs.

On the other hand, since a wiring pattern is formed on an insulating film constituting such a multilayer wiring structure, it is desirable to form a flat structure so that the wiring pattern is not cut by a step. Such planarization of the interlayer insulating film is also necessary when a fine wiring pattern is formed using a high-resolution exposure system. Since the interlayer insulating film is formed so as to fill the lower wiring pattern, it is necessary to form the interlayer insulating film in a state of high fluidity so that the unevenness is not transferred to the surface.

[0005]

For this reason, the conventional S
iO ₂ is deposited so as to cover the wiring pattern by a plasma CVD method using high-density plasma, and this is subjected to chemical mechanical polishing (CMP) as necessary to form a flat interlayer insulating film. However, the relative dielectric constant of an insulating film formed by such a method is limited to about 3.5 even when a fluorine-doped silica film is used, and it is difficult to further reduce the dielectric constant.

On the other hand, it is known that a fluorine-added polyimide resin film or a fluorine resin film is formed by an application method instead of a CVD silica film as an interlayer insulating film. Although the relative dielectric constant can be reduced to around 2, there is a problem that the adhesion to the surface to be coated is insufficient and the film is easily peeled. Further, such an organic insulating material has a problem that it has poor adhesion to a resist used for fine processing of a wiring pattern, and is inferior in chemical resistance or oxygen plasma resistance.

Further, a silica-based coating liquid (so-called SOG) comprising a partial hydrolyzate of an alkoxysilane has been conventionally known. With such a coating solution, a silica coating having a relative dielectric constant of about 2.5 can be obtained, but in this case also, the obtained coating cannot overcome the problem of poor adhesion to the surface to be coated. For example, in a conventional coating solution containing only a hydrolyzate of an alkoxysilane or a halogenated silane as a film-forming component, Si- in a film formed by a hydrogen atom, a fluorine atom or an organic group bonded to a Si atom is used.
As a result of reducing the crosslink density of the O-Si bond, a low dielectric constant film can be obtained to some extent, but these functional groups have poor thermal stability and poor heat resistance, and provide a stable low dielectric film. Can not. Further, there is a problem that the adhesion to the surface to be coated is poor as described above.

Accordingly, it is a general object of the present invention to provide a semiconductor device and a method of manufacturing the same which have solved the above-mentioned problems. A more specific problem of the present invention is that the dielectric constant is low, the adhesiveness with the surface to be coated is excellent, the chemical resistance such as mechanical strength and alkali resistance is further improved, and the crack resistance is excellent. It is an object of the present invention to provide a semiconductor device having an interlayer insulating film capable of flattening unevenness, and a method for manufacturing such a semiconductor device.

[0009]

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems.
And a wiring pattern including the wiring pattern.
A wire layer, on the wiring layer, so as to cover the wiring pattern.
And an interlayer insulating film having a structure filled with particles.
In the semiconductor device, the particles have a size of 50 nm to 5 nm.
SiO having a particle size in the range of_TwoConsisting of particles, said interlayer
Voids are formed between adjacent particles in the insulating film.
And the porosity of the interlayer insulating film is 13 to 42.
% Or less.
Or as described in claim 2.
Has a structure filled with particles, and a gap between adjacent particles.
An interlayer insulating film having: a gap formed on the interlayer insulating film;
And a CVD oxide film formed without substantially filling the
Wherein the interlayer insulating film has a particle size in the range of 50 nm to 5 nm.
SiO with_TwoHaving a structure filled with particles, wherein the voids
Is formed between adjacent particles in the interlayer insulating film.
By a semiconductor device characterized by being performed, or
As described in claim 3, the particles have the general formula (I)
X_nSi (OR ')_4-n(Where X is a hydrogen atom, fluorine
An atom or an alkyl group having 1 to 8 carbon atoms, an allyl group or
A vinyl group, R 'is a hydrogen atom or an alkyl having 1 to 8 carbon atoms;
Represents an aryl group, an allyl group or a vinyl group, and n is an integer of 0 to 3.
The alkoxysilane or silica compound represented by
Of silica-based ultrafine particles obtained by hydrolysis and polycondensation
And the interlayer insulating film further includes the SiO 2_TwoParticles each other
A binder portion that adheres to the binder,
Is an alkoxysilane represented by the general formula (I),
Or general formula (II) X_nSix ' _4-n(Where X is hydrogen
Atom, fluorine atom or alkyl group having 1 to 8 carbon atoms,
Ryl or vinyl, X 'is a fluorine atom, a chlorine atom,
A halogen atom such as a bromine atom or an iodine atom, n is 0
Hydrolyzate of a halogenated silane represented by
3. A reaction product comprising:
According to the semiconductor device described above, or according to claim 4.
As shown in FIG._TwoContains particles and binder
A step of applying a coating liquid, and a structure in which the coating liquid is applied.
After heat treatment, the SiO_TwoInsulating film with voids between particles
Forming a semiconductor device.
And the SiO_TwoParticles having a particle size of 50 to 5 nm
Using the surrounding particles, the heat treatment step is performed at 350 ° C to 40 ° C.
In the range of 0 ° C, in an inert gas with an oxygen concentration of 1% or less
In the method of manufacturing a semiconductor device.
Or forming the interlayer insulating film as described in claim 5.
Forming a CVD insulating film on the interlayer insulating film
And a method of manufacturing a semiconductor device, comprising:
The step of forming the interlayer insulating film is performed in a range of a particle size of 50 to 5 nm.
Surrounding SiO_TwoApplying a coating solution containing particles and a binder
And heat treating the structure coated with the coating solution,
SiO_TwoForming an insulating film having voids between particles; and
Wherein the step of forming the CVD insulating film comprises:
The CVD insulating film does not substantially penetrate into the interlayer insulating film.
Semiconductor device manufacturing method characterized by forming
By the method or as set forth in claim 6.
The process is performed at a temperature between 350 ° C. and 400 ° C.
6. The method for manufacturing a semiconductor device according to claim 5, wherein
Or as described in claim 7, the impregnation
Characterized in that it is not more than twice the particle diameter of the particles.
The method of manufacturing a semiconductor device according to claim 5,
Forms the CVD insulating film as described in claim 8
Is performed by SiH_FourAnd N_TwoCVD using O as raw material
SiO_TwoForming a film, wherein said CVD-Si
O_TwoIn the step of forming a film, the CVD-SiO_TwoFine film
For optimal conditions when forming on a dense substrate, pressure and
And / or N_TwoO to increase the flow rate
6. The method of manufacturing a semiconductor device according to claim 5, wherein
Or the first interlayer, as described in claim 9.
Forming the first CVD film on an insulating film;
Forming a first opening in the first CVD film;
The second interlayer insulating film is formed on the first CVD film.
And a second CVD process on the second interlayer insulating film.
Forming a film; and forming the second CVD film in the second CVD film.
Larger than the first opening corresponding to the first opening
Forming a second opening, the second interlayer insulating film;
With respect to the second interlayer insulating film.
Performing light etching through the second opening,
A groove corresponding to the second opening in a second interlayer insulating film;
Is formed so that the groove penetrates the second interlayer insulating film.
Forming the first interlayer insulating film with respect to the first interlayer insulating film.
Dry etching selectively acting on one interlayer insulating film
Through the groove and the first opening,
A gap corresponding to the first opening is formed in the first interlayer insulating film.
Forming a through hole;
Filling the first layer with a conductive pattern.
Forming the through hole in the inter-insulating film,
Continuing with the step of forming the groove in the second interlayer insulating film
9. The semiconductor according to claim 5, which is executed.
According to the method of manufacturing the device or as described in claim 10.
Thus, the first CVD film is formed on the first interlayer insulating film.
Forming a second layer on the first CVD film.
Forming an interlayer insulating film; and forming the interlayer insulating film on the second interlayer insulating film.
Forming the second CVD film on the substrate;
VD film, the second interlayer insulating film thereunder,
The first CVD film and the first interlayer insulating film thereunder
Forming a through hole by passing through the
For the second CVD film and the second interlayer insulating film,
A groove corresponding to the second opening is formed in the first CVD film.
Perform dry etching as a etching stopper,
Forming a groove so as to penetrate the second interlayer insulating film;
9. The semiconductor according to claim 5, further comprising:
The problem is solved by a method of manufacturing the device.

Hereinafter, the principle of the present invention will be described with reference to FIG. However, FIG. 1 shows an enlarged view of the structure of the interlayer insulating film 10 according to the present invention. Referring to FIG. 1, an interlayer insulating film 10 has a structure in which silica (SiO ₂ ) particles 2 each having a diameter of 5 to 50 nm and formed by hydrolyzing an alkoxide are packed. They are connected to each other by a connecting portion 3 also made of silica. The bonding portion forms a neck portion having a reduced diameter between adjacent silica particles, and as a result, a void 4 surrounded by three or more silica particles is formed in the interlayer insulating film 10. In the present invention, the void ratio occupied by the voids 4 in the interlayer insulating film 10 reaches about 13 to 42%. In other words, the interlayer insulating film 10
Has a porous structure, and due to the presence of such voids, the dielectric constant is much lower than in the case of a dense SOG film.

For example, when the dielectric constant of SiO ₂ is 4.2 and the dielectric constant of the void portion is 1.0, in order for the dielectric constant of the entire film to be 3.0, the porosity is 13%, 2 It is 22% to reach 0.5 and 42% to reach 1.8.
The result of the actual measurement of the film density also confirmed that the porosity was 25% when the dielectric constant was 2.5. The silica particles 2 are, for example, of the general formula (I) X _n Si (OR ′)
_4-n (where X is a hydrogen atom, a fluorine atom or a carbon atom of 1
Alkoxysilane or silica represented by an alkyl group, an allyl group or a vinyl group of from 8 to 8; R 'represents a hydrogen atom or an alkyl group, an allyl group or a vinyl group of from 1 to 8 carbon atoms, and n is an integer of from 0 to 3) The silica-based ultrafine particles obtained by hydrolysis and polycondensation of a compound, and the bonding portion 3 is an alkoxysilane represented by the above general formula (I) or a general formula (II) X _n SiX ′ _4-n (formula Wherein X is a hydrogen atom, a fluorine atom or an alkyl group having 1 to 8 carbon atoms, an allyl group or a vinyl group, X ′ is a halogen atom such as a fluorine atom, a chlorine atom, a bromine atom or an iodine atom, and n is 0 to 3 (Integral) and a reaction product with a hydrolyzate of a halogenated silane.

The silica fine particles are formed by hydrolyzing and polycondensing an alkoxysilane or a halogenated silane with water,
It is formed by performing the reaction in the presence of an organic solvent and a catalyst. Examples of the alkoxysilane include tetramethoxysilane, tetraethoxysilane, tetraisopropoxysilane, tetrabutoxysilane, tetraoctylsilane, methyltrimethoxysilane, and methyltriisosilane. Propoxysilane, ethyltrimethoxysilane, ethyltriethoxysilane, ethyltriisopropoxysilane, octyltrimethoxysilane, octyltriethoxysilane, vinyltriethoxysilane, phenyltriethoxysilane, phenyltrimethoxysilane, trimethoxysilane, triethoxy Silane, triisopropoxysilane, fluorotrimethoxysilane, fluorotriethoxysilane, dimethylmethoxysilane, dimethylethoxysilane, dimethylmeth Shishiran, diethyl diethoxy silane, dimethoxy silane, difluoromethoxy silane, trifluoromethyl trimethoxy silane, should it use trifluoromethyl triethoxysilane. Also,
As the organic solvent, alcohols, ketones, ethers, and esters can be used. Alcohols include methanol, ethanol, propanol, butanol and the like, ketones include methyl ethyl ketone and methyl isobutyl ketone, and esters include methyl acetate, ethyl acetate, methyl lactate and ethyl lactate. Further, it is also possible to use glycols such as methyl cellosolve, ethyl cellosolve, propylene glycol and hexyl glycol. Further, as the catalyst, a compound exhibiting basicity such as ammonia, an amine, an alkali metal compound, a quaternary ammonium compound, and an amine-based coupling agent is used.

In the formation of the silica fine particles, water is used in a proportion of 0.5 to 50 mol, preferably 1 to 25 mol, per 1 mol of the Si—OR group constituting the alkoxysilane, and ammonia is used. For example, 0.01 to 1 mol, preferably 0.05 to 0.8 mol per 1 mol of SiO _2.
Used in mole proportions. The hydrolysis reaction is carried out at a temperature lower than the boiling point of the solvent, preferably at a temperature lower by 5 to 10 ° C. than the boiling point. As a result of the hydrolysis at such a low temperature, the polycondensation of the alkoxysilane proceeds three-dimensionally, and silica fine particles grow. The matured silica fine particles are further aged at the above-mentioned reaction temperature or higher temperature, whereby the polycondensation of the alkoxysilane further proceeds, and the inside of the obtained silica fine particles becomes dense.

The silica particles 2 and the binder constituting the bonding portion 3 are dispersed in a solvent composed of glycol ether to obtain a coating solution. Such a coating solution,
The insulating film 1 is coated on the substrate by spraying, spin coating, dip coating or roll coating, and further sintering the substrate coated with the coating liquid.
0 can be formed so that the relative dielectric constant is 3 or less.

FIG. 2 shows the relationship between the relative dielectric constant of the insulating film 10 thus formed and the particle size of the silica particles 2. Referring to FIG. 2, the relative dielectric constant of the film 10 decreases as the particle size decreases, but starts to increase around 10 nm (100 °). In that case, a relative dielectric constant of 3.0 or less can be obtained when the particle size is approximately 5 nm (50 °) or more. The relative dielectric constant is such that the particle size of the silica particles 2 is 100 nm (1
Even if it increases up to about 000 °), it is not more than 3.0, but if the particle size of the particles 2 becomes so large, the unevenness of the surface of the film 1 becomes severe, and therefore, the film 10 is used for a multilayer wiring structure. It is no longer suitable as an interlayer insulating film. For this reason, the upper limit of the particle size of the particles 2 is set to 50 nm based on 1/10 of the unevenness of about 500 nm generally accepted as an interlayer insulating film.
(500 °) is preferably set to be equal to or less than (500 °). The particle size of the particles 2 can be controlled by controlling the pH, temperature, time and the like during the hydrolysis.

As described above, the coating thus formed is further fired, and the binder sinters with the firing to form a strong neck-shaped joint 3. At this time, the adhesion between the substrate and the film 10 can be maximized by optimizing the firing conditions. FIG.
(A) and (B) show such a film 10 for the model structure.
Shows the firing of

Referring to FIG. 3A, an Al wiring pattern 1B is formed on a Si substrate 1 with a TiN film 1A for improving adhesion to the substrate 1 interposed therebetween. Is formed with another TiN film 1C. Further, the insulating film 10 shown in FIG.
On the structure (A), the wiring pattern 1B is formed as an interlayer insulating film by, for example, a spin coating method, and the structure is further baked to form the voids 4 in the insulating film.

Generally, the firing of such SOG coatings is 45
Although it is performed at a temperature of 0 ° C. or more, in the case of the interlayer insulating film according to the present invention, if the firing is performed at such a high temperature, the adhesion between the wiring pattern 1B and the interlayer insulating film 10 becomes poor,
It has been found that voids or gaps 1X occur. On the other hand, if the firing temperature is too low, the reaction of the film 10 does not proceed, the adhesion to the substrate 1 or the pattern 1B becomes poor, and voids are generated.

Table 1 below shows the structure of FIG.
The relationship between the sintering temperature and the adhesion when sintering is performed at various temperatures is shown.

[0020]

[Table 1]

Referring to Table 1, the firing temperature was 300 ° C.
Below or at 480 ° C. or more, significant voids are observed, and even at a firing temperature of 450 ° C., some voids are observed. On the other hand, when the firing temperature is 3
When the temperature was set in the range of 50 ° C. to 400 ° C., no void was generated, and it was confirmed that the film 10 exhibited excellent adhesion.

FIG. 4 shows that the atmosphere at the time of firing was the film 1
The effect on the relative permittivity of 0 is shown. Referring to FIG. 4, baking is performed in a nitrogen atmosphere, and it has been recognized that the relative dielectric constant of the film 10 increases as the oxygen concentration in the nitrogen atmosphere increases. This is because, in the structure of FIG. 1, the binder constituting the bonding portion 3 or the alkoxysilane or the halogenated SiH bonded to the surface of the silica particles 2
This is probably because the hydrolyzate of No. 4 was oxidized by oxygen and became in a state of easily adsorbing moisture.

From the relationship shown in FIG. 4, the relative dielectric constant of the film 10 is set to 3.
It can be seen that the oxygen concentration in the atmosphere at the time of firing needs to be suppressed to 1% or less in order to suppress it to 0 or less. However,
The relationship in FIG. 4 is based on the case where the firing temperature is 400 ° C., and the relative permittivity was measured by measuring the capacity of the coating 10 using a mercury probe. To summarize the above, a silica coating is formed from the coating liquid for forming a silica-based coating according to the present invention, and when this is fired at an optimum firing temperature and firing atmosphere, the obtained coating is formed of silica particles contained in the coating liquid. The voids formed at the grain boundaries make the porous material porous, and the hydrolyzate of alkoxysilane or halogenated silane bonded to the surface of the void prevents water from adsorbing to the void. The following stable silica-based coating having excellent heat resistance can be obtained. Further, the silica-based particles in the film exhibit an anchor effect on the underlayer, and therefore, the silica coating exhibits excellent adhesion to the underlayer. Further, the coating according to the present invention,
Excellent mechanical strength, excellent chemical resistance such as alkali resistance,
Also shows excellent crack resistance. The diameter of the silica particles is 5
Since it is 0 nm or less, the film surface becomes flat.

[0024]

BEST MODE FOR CARRYING OUT THE INVENTION

[First Embodiment] FIGS. 5A to 5C show a method of manufacturing a semiconductor device according to a first embodiment of the present invention and the structure of the obtained semiconductor device. Referring to FIG. 5 (A), on a Si substrate 11 on which a semiconductor element (not shown) is formed, A
Conductor pattern 1 made of l, W, polysilicon, etc.
2 is formed, and in the step of FIG.
In the structure of the formula, for example, the general formula (I) X _n Si (OR ′)
_4-n (where X is a hydrogen atom, a fluorine atom or a carbon atom of 1
Alkoxysilane or silica represented by an alkyl group, an allyl group or a vinyl group of from 8 to 8; R 'represents a hydrogen atom or an alkyl group, an allyl group or a vinyl group of from 1 to 8 carbon atoms, and n is an integer of from 0 to 3) A silica-based ultrafine particle obtained by hydrolysis and polycondensation of a compound and, as a binder, an alkoxysilane represented by the general formula (I) or a general formula (II) X _n SiX ′ _4-n (wherein X Is a hydrogen atom, a fluorine atom or an alkyl group having 1 to 8 carbon atoms, an allyl group or a vinyl group, X ′ is a halogen atom such as a fluorine atom, a chlorine atom, a bromine atom or an iodine atom, and n is an integer of 0 to 3) A coating liquid for forming a silica-based film containing a hydrolyzate of a halogenated silane represented by the formula (1) is applied. However, the Si substrate 11 has various diffusion regions formed in an active region defined by a field oxide film (not shown), and its surface is covered with a thinner thermal oxide film. The conductor pattern 12 forms an electrode or a wiring pattern. As a result of the application of the application liquid, as shown in FIG. 5B, a silica coating 13 is formed to a thickness of 0.1 to 0.25 μm as an interlayer insulating film filling the conductor pattern 12. The coating liquid has excellent fluidity, and as a result, the interlayer insulating film 13 has excellent flatness.

The structure shown in FIG. 5B further includes nitrogen or Ar having an oxygen concentration of 1% or less at 400 ° C. for 30 minutes.
And the like, so that the binder sinters around the silica particles to form a neck-like joint 3 similar to that shown in FIG. Accordingly, voids 4 are formed in the interlayer insulating film 13 at the grain boundaries of the silica particles.

Further, in the step of FIG. 5C, a contact hole 13A exposing the conductor pattern 12 is formed in the interlayer insulating film 13, and this is inserted into the conductor plug 1 such as W.
Fill with 4 Further, a second-layer conductor pattern 15 is formed on the interlayer insulating film 13 by the conductor plug 1.
4 is formed. Second Embodiment FIGS. 6A to 6D show a method of manufacturing a semiconductor device according to a second embodiment of the present invention, and the structure of the obtained semiconductor device.

Referring to FIG. 6A, a conductor pattern 22 made of Al, W, polysilicon or the like is formed on a Si substrate 21 on which a semiconductor element (not shown) is formed. In the step B), an SiO ₂ film 23 is formed on the structure of FIG. 6A by a CVD method so as to cover the conductor pattern 22. Next, FIG.
In the step (2), the same coating solution for forming a silica-based film as described in the first embodiment is applied onto the structure of FIG. 6 (B). However, the Si substrate 21 has various diffusion regions formed in an active region defined by a field oxide film (not shown), and its surface is covered with a thinner thermal oxide film. The conductor pattern 22 forms an electrode or a wiring pattern. As a result of the application of the application liquid, FIG.
As shown in FIG.
_As an interlayer insulating film covering the conductor pattern 22 covered with the _two films 23, it is formed to a thickness of 0.1 to 0.25 μm. The coating liquid has excellent fluidity, and as a result, the interlayer insulating film 24 has excellent flatness.

The structure shown in FIG. 6C further includes nitrogen or Ar having an oxygen concentration of 1% or less at 400 ° C. for 30 minutes.
And the like, so that the binder sinters around the silica particles to form a neck-like joint 3 similar to that shown in FIG. Accordingly, voids 4 are formed in the interlayer insulating film 24 at the grain boundaries of the silica particles.

Further, in the step of FIG. 6D, a contact hole 24A exposing the conductor pattern 22 is formed in the interlayer insulating film 24, and the contact hole 24A is
Fill with 5 Further, a second-layer conductor pattern 25 is formed on the interlayer insulating film 24 by the conductor plug 2.
5 is formed. Third Embodiment FIGS. 7A to 7D show a method of manufacturing a semiconductor device according to a third embodiment of the present invention, and the structure of the obtained semiconductor device.

Referring to FIG. 7A, a conductor pattern 32 made of Al, W, polysilicon or the like is formed on a Si substrate 31 on which a semiconductor element (not shown) is formed. 7), the same coating liquid for forming a silica-based film as described in the first embodiment is applied on the structure of FIG. 7A. However, the Si substrate 11 is provided in an active region defined by a field oxide film (not shown).
Various diffusion regions are formed, and the surface is further covered with a thin thermal oxide film. The conductor pattern 12 forms an electrode or a wiring pattern. As a result of the application of the coating solution, as shown in FIG. 7B, the silica coating 33 is used as an interlayer insulating film for filling the conductor pattern 32 with 0.1.
It is formed to a thickness of about 0.25 μm. The coating liquid has excellent fluidity, and as a result, the interlayer insulating film 33 has excellent flatness.

The structure shown in FIG. 7 (B) further comprises nitrogen or Ar having an oxygen concentration of 1% or less at 400 ° C. for 30 minutes.
And the like, so that the binder sinters around the silica particles to form a neck-like joint 3 similar to that shown in FIG. Accordingly, voids 4 are formed in the interlayer insulating film 33 at the grain boundaries of the silica particles.

Further, in the step shown in FIG. 7C, an SiO ₂ film 34 is formed on the interlayer insulating film 33 by CVD method.
The interlayer insulating film 33 and the CVD-SiO ₂ film 34 are formed in a thickness of 1 to 0.4 μm in the process of FIG.
, A contact hole 33A exposing the conductor pattern 12 is formed. The formed contact hole 33A is filled with a conductor plug 35 of W or the like, and a second-layer conductor pattern 36 is formed on the CVD-SiO ₂ film 34 so as to contact the conductor plug 35. Is done. Fourth Embodiment FIGS. 8A to 8E show a method of manufacturing a semiconductor device according to a fourth embodiment of the present invention, and the structure of the obtained semiconductor device.

Referring to FIG. 8A, a conductor pattern 42 made of Al, W, polysilicon or the like is formed on a Si substrate 41 on which a semiconductor element (not shown) is formed. In the step B), an SiO ₂ film 43 is formed on the structure of FIG. 8A by a CVD method so as to cover the conductor pattern 42. Next, FIG.
In the step (3), the same coating liquid for forming a silica-based film as described in the first embodiment is applied onto the structure of FIG. However, the Si substrate 41 has various diffusion regions formed in an active region defined by a field oxide film (not shown), and its surface is covered with a thinner thermal oxide film. The conductor pattern 42 forms an electrode or a wiring pattern. As a result of the application of the application liquid, FIG.
As shown in (C), the silica coating 44 is formed by the CVD-
An interlayer insulating film covering the conductor pattern 42 covered with the SiO ₂ film 43 is formed to a thickness of 0.1 to 0.25 μm. The coating liquid has excellent fluidity, and as a result, the interlayer insulating film 44 has excellent flatness.

The structure shown in FIG. 8C further includes nitrogen or Ar having an oxygen concentration of 1% or less at 400 ° C. for 30 minutes.
And the like, so that the binder sinters around the silica particles to form a neck-like joint 3 similar to that shown in FIG. Accordingly, voids 4 are formed in the interlayer insulating film 44 at the grain boundaries of the silica particles.

Next, in the step of FIG. 8D, an SiO ₂ film 45 is formed on the structure of FIG. 8C by a CVD method, typically to a thickness of 400 nm. In the step (E), the interlayer insulating film 44 and the CVD-SiO ₂
A contact hole 44A exposing the conductor pattern 42 is formed so as to penetrate the film 45. The contact hole 44A is filled with a conductor plug 46 such as W, and a second-layer conductor pattern 47 is formed on the interlayer insulating film 45 so as to contact the conductor plug 46.

In any of the embodiments of the present invention, the obtained interlayer insulating film has a relative dielectric constant of 3 or less, and therefore does not cause a problem such as a signal delay which causes a decrease in semiconductor operating speed. Also, the obtained interlayer insulating film is stable against moisture absorption,
Also, it shows excellent adhesion to the underlying structure including the wiring pattern. In each of the embodiments described above, the base is a Si substrate. However, the present invention is not limited to such a specific structure, and the base may have a similar multilayer wiring structure. In this case, the thickness of the interlayer insulating film is slightly thicker for flattening, and is preferably set to about 0.3 to 2.0 μm. [Fifth Embodiment] In the third and fourth embodiments,
In the case where the interlayer insulating film 34 or 45 is formed on the porous interlayer insulating film 33 or 45 having the gap by the plasma CVD method, the SiO ₂ film is formed on such a porous film by the plasma CVD method. However, there is a tendency that the CVD-SiO ₂ film invades the voids in the porous interlayer insulating film. See FIG. CVD-S
When the iO ₂ film enters, the dielectric constant of the porous interlayer insulating film increases.

Table 2 below shows deposition conditions when a CVD-SiO ₂ film is formed on the porous interlayer insulating film by a normal plasma CVD method.

[0038]

[Table 2]

Under the conditions shown in Table 2, C was deposited on the porous interlayer insulating film.
When a VD-SiO ₂ film is formed, the dielectric constant of the porous interlayer insulating film itself is 2.45 at a film thickness of 340 nm, and the dielectric constant of the CVD-SiO ₂ film itself is 4 at a film thickness of 220 nm. Whereas the dielectric constant of the structure in which the CVD-SiO ₂ film is formed on the porous interlayer insulating film is 3.9 when the total film thickness is 560 nm.
It was experimentally found to be 3. This is the CV
If the dielectric constant of D-SiO ₂ film itself and 4.69, the dielectric constant of the silica fine particles indicates that it is effectively increased to 4.56. This is because, as described above with reference to FIG. 9, a substantial amount of SiO ₂ is filled in the voids in the porous interlayer insulating film.
Is invading.

Therefore, in this embodiment, the CVD-Si
When depositing an O ₂ film using SiH ₄ and TEOS as raw materials, as shown in Table 3 below, the pressure is increased and the flow rate of N ₂ O gas is increased as compared with that used in a normal plasma CVD method. By doing so, penetration of the CVD-SiO ₂ film into the porous interlayer insulating film is minimized.

[0041]

[Table 3]

Under the conditions shown in Table 3, CVD-SiO_TwoPorous membrane
When formed on an interlayer insulating film, the porous interlayer insulating film
The dielectric constant of the body is 2.50 at a film thickness of 400 nm.
And the CVD-SiO_TwoThe dielectric constant of the film itself is
4.54 at 200 nm, whereas
CVD-SiO on a porous interlayer insulating film_TwoStructure with film formed
The dielectric constant of the structure is 3.19 when the total film thickness is 600 nm.
It was found that it was nothing more. This is the same as the CVD
-SiO_TwoWhen the dielectric constant of the film itself is 4.54,
The dielectric constant of the silica fine particles must be suppressed to 2.45
Is shown. This is substantially due to the voids in the porous interlayer insulating film.
Amount of SiO_TwoIndicates that has not entered. Table 3 conditions
In CVD-SiO_TwoWhen a film is deposited, the CV
D-SiO _TwoInfiltration of the film into the porous interlayer insulating film
Is considered to be less than twice the particle size of the silica fine particles.
You.

Of course, CVD on the porous interlayer insulating film
-The formation of the SiO ₂ film can also be performed by using a high-density plasma CVD method. Table 4 below shows examples of conditions for forming the CVD-SiO ₂ film by the high-density plasma CVD method.

[0044]

[Table 4]

When a CVD-SiO ₂ film is formed on the porous interlayer insulating film under the conditions shown in Table 4, the dielectric constant of the porous interlayer insulating film itself is 2.54 at a thickness of 400 nm, and -The dielectric constant of the SiO ₂ film itself is 4.54 at a thickness of 200 nm, whereas the dielectric constant of the structure in which the CVD-SiO ₂ film is formed on the porous interlayer insulating film has a total thickness of 2.52 for 600 nm
It was found that it was nothing more. This is the same as the CVD
When the dielectric constant of the SiO ₂ film itself is 4.54, the dielectric constant of the silica fine particles is suppressed to 2.45 or less. This indicates that a substantial amount of SiO ₂ has not entered the voids in the porous interlayer insulating film. When a CVD-SiO ₂ film is deposited under the conditions shown in Table 4, it is considered that the penetration of the CVD-SiO ₂ film into the porous interlayer insulating film is twice or less the particle diameter of the silica fine particles. Sixth Embodiment FIGS. 10A to 11E are views for explaining a method of forming a multilayer wiring structure 50 having a damascene structure according to a sixth embodiment of the present invention.

Referring to FIG. 10A, an SiO ₂ film 52A is formed on a substrate 51 by a normal CVD method.
Further, a porous interlayer insulating film 53 having the structure shown in FIG. 1 and including the gap 4 described in the previous embodiment is applied on the SiO ₂ film 52A by spin coating. Further, another SiO ₂ film 52B is formed on the porous interlayer insulating film 53 by the plasma CVD method under the conditions described in Table 3.

Next, in the step of FIG.
_A groove 53A is formed through the _two films 52A and 52B and the porous interlayer insulating film 53.
In the step (C), the C is filled so as to fill the groove 53A.
Barrier metal film 54A such as TiN on VD insulating film 52B
And a conductor film 54B made of Al _, Cu or W is deposited.

Further, in the step of FIG.
The conductor film 54B and the barrier metal film 54A on the D insulating film 52B are polished and removed by the CMP method, so that the conductor pattern 54 substantially buried in the interlayer insulating film 53 is formed. Furthermore, by repeating the above steps,
The multilayer wiring structure shown in FIG. 11E is formed. Seventh Embodiment FIGS. 12A to 13F are views for explaining a method of forming a multilayer wiring structure 60 having a damascene structure according to a seventh embodiment of the present invention.

Referring to FIG. 12A, in this embodiment, an SiO ₂ film 62A is formed on a substrate 61 by a normal CVD method or a plasma CVD method.
On the iO ₂ film 62A, the porous interlayer insulating film 63 having the structure shown in FIG. 1 and including the voids 4 described in the previous embodiment is applied by spin coating. Further, on the porous interlayer insulating film 63, under the conditions described above in Table 3,
Another SiO ₂ film 62B is formed by a plasma CVD method.

Next, in the step of FIG.
_The opening 62C is patterned on the _second film 62B, and in the step of FIG. 12C, another porous interlayer insulating film 64 is spin-coated on the SiO ₂ film 62B so as to fill the opening 62C. And another SiO ₂ film 64A is formed on the porous insulating film 64 by the Si.
Like the O ₂ film 62B, it is formed by a plasma CVD method.

Next, in the step of FIG.
₂₎ A resist pattern 65 having an opening is formed on the film 64A, and the resist pattern 65 is used as a mask to form the Si pattern.
The opening 64B is formed by patterning the O ₂ film 64A. Next, using the SiO ₂ film 64A as a mask, the porous interlayer insulating films 64 and 63 are successively subjected to dry etching in succession to form a groove 64C corresponding to the opening 64B in the interlayer insulating film 64. And the interlayer insulating film 63
A smaller diameter through hole 63A corresponding to the opening 62C is formed therein. At this time, the SiO ₂ film 6
2B functions as an etching stopper mask.

Further, by forming a conductor pattern so as to fill the through holes 63A and the grooves 64C, a multilayer wiring structure having the structure shown in FIG. 13F is formed. In this embodiment, since the film 62B is used as an etching stopper mask, the film 62B may be formed of, for example, SiN or the like which has etching resistance to dry etching of SiO ₂ . In this case, the dry etching process of FIG. 13E is performed by using, for example, C ₄ F ₈ and CH ₂ F ₂ as etching gases in an Ar atmosphere under a pressure of 5 mmTorr, a bias of 1000 W, and a source power of 1000 W. Is preferred. [Eighth Embodiment] FIGS. 14A to 15E are views for explaining a method of forming a multilayer wiring structure 70 having a damascene structure according to an eighth embodiment of the present invention.

Referring to FIG. 14A, in this embodiment, an SiO ₂ film 72A is formed on a substrate 71 by a normal CVD method or a plasma CVD method.
On the iO ₂ film 72A, the porous interlayer insulating film 73 having the structure shown in FIG. 1 and including the voids 4 described in the previous embodiment is applied by spin coating. Further, on the porous interlayer insulating film 73, under the conditions described above in Table 3,
Another SiO ₂ film 72B is formed by a plasma CVD method, and another porous interlayer insulating film 74 is applied on the SiO ₂ film 72B by spin coating.

Next, in the step of FIG. 14B, the porous interlayer insulating films 73 and 74 and the SiO ₂ films 72B and 74 are formed.
B is dry-etched to form a through hole 74
Form C. Further, in the step of FIG.
A resist pattern 75 having an opening 75A is formed on the O ₂ film 74B. Then, in the step of FIG. 15D, the resist pattern 75 is used as a mask to form the interlayer insulating film 74 and the SiO ₂ mask 74A thereon. A groove 74D is formed continuously to the through hole 74C extending in the interlayer insulating film 73.

Further, by depositing a conductive film so as to fill the through holes 74C and the grooves 74D, a multilayer wiring structure shown in FIG. 15E is obtained. Also in this embodiment, the film 72B may be a SiN film. At this time, in the dry etching step of FIG. 15D, dry etching is preferably performed under the conditions described above so that the maximum selectivity can be obtained between the SiN film 72B and the porous interlayer insulating film 74. . Ninth Embodiment FIGS. 16A to 17D are views for explaining a method of forming a multilayer wiring structure 80 having a damascene structure according to a ninth embodiment of the present invention.

Referring to FIG. 16A, in this embodiment, an SiO ₂ film 82A is formed on a substrate 81 by a normal CVD method or a plasma CVD method.
On the iO ₂ film 82A, the porous interlayer insulating film 83 having the structure shown in FIG. 1 and including the voids 4 described in the previous embodiment is applied by spin coating. Further, on the porous interlayer insulating film 83, under the conditions described above in Table 3,
Another SiO ₂ film 82B is formed by a plasma CVD method.

Next, in the step of FIG.
Dry etching is performed on the _second film 82B and the porous interlayer insulating film 83 thereunder, and a groove 83A whose bottom surface is located above the bottom surface of the layer 83 is formed in the interlayer insulating film 83.
Further, in the step of FIG. 17C, a resist pattern 84 having an opening 84A corresponding to the groove 83A is formed on the structure of FIG. 16B, and in the step of FIG. By performing dry etching using the mask 84 as a mask, a contact hole 82C is formed in the groove 83A.

Further, by filling the groove 83A and the contact hole 82C with a conductive pattern, a multilayer wiring structure similar to that described above can be obtained. As described above, the present invention has been described with respect to the preferred embodiments. However, the present invention is not limited to such specific embodiments, and various modifications and changes can be made within the gist of the present invention.

[0059]

According to the first and second aspects of the present invention, there is provided a wiring layer including a wiring pattern, and a structure formed on the wiring layer so as to cover the wiring pattern and filled with particles. In a semiconductor device having an interlayer insulating film, the particles are formed from SiO ₂ particles having a particle size in a range of 50 nm to 5 nm, and a void is formed between adjacent particles in the interlayer insulating film. By setting the porosity of the interlayer insulating film in the range of 13 to 42%, the dielectric constant of the interlayer insulating film can be reduced without impairing the flatness.

According to the features of the present invention described in claim 3,
The particles are represented by the general formula (I) X_nSi (OR ')_4-n(formula
Wherein X is a hydrogen atom, a fluorine atom or an alkyl group having 1 to 8 carbon atoms.
Alkyl, allyl or vinyl, and R 'is hydrogen
Or an alkyl group having 1 to 8 carbon atoms, an allyl group or vinyl
And n represents an integer of 0 to 3)
Obtained by hydrolyzing / polycondensing a run or silica compound
And the interlayer insulating film is
Notation SiO _TwoIncludes a binder that bonds the particles together
And the binder is represented by the general formula (I).
Alkoxysilane represented by the general formula (II) X_nSi
X '_4-n(Wherein X is a hydrogen atom, a fluorine atom or a carbon atom
An alkyl group of formulas 1 to 8, an allyl group or a vinyl group, X '
Is a fluorine, chlorine, bromine or iodine atom
Any halogen atom, n is an integer of 0 to 3)
Forming from the reaction product of hydrolyzate of genosilane
As a result, the moisture on the surface of the void formed in the interlayer insulating film
Adsorption is suppressed, and dielectric constant increases due to moisture absorption of interlayer insulating film
Is avoided.

According to a fourth aspect of the present invention, a step of applying a coating solution containing SiO ₂ particles and a binder on the underlayer structure, and heat-treating the structure coated with the coating solution, Forming an insulating film having voids between SiO ₂ particles.
As the iO ₂ particles, particles having a particle size in the range of 50 to 5 nm are used, and the heat treatment step is performed in the range of 350 ° C. to 400 ° C. in an inert gas having an oxygen concentration of 1% or less. The planarized low dielectric constant interlayer insulating film can be formed with good adhesion to the underlying structure.

According to a fifth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: a step of forming an interlayer insulating film; and a step of forming a CVD insulating film on the interlayer insulating film. The step of forming the interlayer insulating film includes a step of applying a coating liquid containing SiO ₂ particles having a particle size in a range of 50 to ₅ nm and a binder, and a step of heat-treating the structure coated with the coating liquid to form the SiO ₂ Forming the CVD insulating film, including forming an insulating film having voids between particles, by forming the CVD insulating film so as not to substantially penetrate into the interlayer insulating film. The dielectric constant of the interlayer insulating film including the CVD insulating film can be minimized.

According to the features of the present invention, a multilayer wiring structure having a so-called damascene structure in which a wiring pattern or a contact hole is buried in a porous interlayer insulating film including voids can be obtained.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a diagram showing the relationship between the dielectric constant of the insulating film of FIG. 1 and the particle size of silica particles constituting the insulating film.

FIG. 3 is a diagram illustrating the adhesion of an insulating film of the present invention.

FIG. 4 is a diagram showing a relationship between a dielectric constant of an insulating film of the present invention and an oxygen concentration in an atmosphere used in a curing process.

FIG. 5 is a diagram illustrating a method of manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 6 is a view illustrating a method of manufacturing a semiconductor device according to a second embodiment of the present invention.

FIG. 7 is a view illustrating a method of manufacturing a semiconductor device according to a third embodiment of the present invention.

FIG. 8 is a view illustrating a method of manufacturing a semiconductor device according to a fourth embodiment of the present invention.

FIG. 9 is a diagram illustrating a problem of seepage of the CVD interlayer insulating film into the porous interlayer insulating film which occurs when the interlayer insulating film is formed on the porous interlayer insulating film by a conventional CVD method.

FIGS. 10A to 10C are diagrams illustrating a step of forming a multilayer wiring structure according to a sixth embodiment of the present invention (Part 1).

FIGS. 11D to 11E are diagrams (part 2) for explaining a step of forming a multilayer wiring structure according to a sixth embodiment of the present invention;

FIGS. 12A to 12C are diagrams (part 1) for explaining a step of forming a multilayer wiring structure according to a seventh embodiment of the present invention;

FIGS. 13D to 13F are diagrams (part 2) for explaining a step of forming a multilayer wiring structure according to a seventh embodiment of the present invention.

FIGS. 14A to 14C are diagrams (part 1) for explaining a step of forming a multilayer wiring structure according to an eighth embodiment of the present invention;

FIGS. 15 (D) to (E) are diagrams illustrating a step of forming a multilayer wiring structure according to an eighth embodiment of the present invention (Part 2). FIGS.

FIGS. 16A and 16B are diagrams (part 1) for explaining a step of forming a multilayer wiring structure according to a ninth embodiment of the present invention;

FIGS. 17D to 17E are views (part 2) for explaining a step of forming a multilayer wiring structure according to the ninth embodiment of the present invention;

[Explanation of symbols]

1.11.21.31.41, 51, 61, 71, 81
Substrate 2 TiN film 2X Void 3 Al film 10,13,24,33,44,53,63,64,7
3, 74, 83 Porous interlayer insulating film 12, 22, 32, 42, 54 Conductor pattern 13A, 24A, 33A, 44A, 63A, 74C, 8
2C Contact hole 14, 25, 25, 46, 54 Conductor plug 23, 34, 45 CVD-SiO ₂ film 64C, 74D, 83A Groove

Claims (10)

[Claims] 1. A semiconductor device comprising: a wiring layer including a wiring pattern; and an interlayer insulating film formed on the wiring layer so as to cover the wiring pattern and filled with particles. S having a particle size in the range of 50 nm to 5 nm
iO consists ₂ particles, wherein in the interlayer insulating film, between the adjacent particles and particles that voids are formed, the porosity of the interlayer insulating film is in the range of 1 3-42% 3. The semiconductor device according to claim 1, wherein: 2. An interlayer insulating film having a structure filled with particles and having a gap between adjacent particles, a CVD oxide film formed on the interlayer insulating film without substantially filling the gap. Wherein the interlayer insulating film has a structure filled with SiO ₂ particles having a particle size in the range of 50 nm to 5 nm, and the voids are formed between adjacent particles in the interlayer insulating film. A semiconductor device. 3. The particles of the general formula (I) X _n Si (O
R ′) _4-n (wherein X is a hydrogen atom, a fluorine atom or an alkyl group having 1 to 8 carbon atoms, an allyl group or a vinyl group,
R ′ represents a hydrogen atom or an alkyl group having 1 to 8 carbon atoms, an allyl group or a vinyl group, and n is an integer of 0 to 3).
The interlayer insulating film is made of ultrafine silica particles obtained by polycondensation. The interlayer insulating film further includes a binder portion for bonding the SiO ₂ particles to each other, and the binder is an alkoxysilane represented by the general formula (I). Or a general formula (II) X _n SiX ′ _4-n (wherein X is a hydrogen atom, a fluorine atom or an alkyl group having 1 to 8 carbon atoms, an allyl group or a vinyl group, X ′ is a fluorine atom, a chlorine atom, A halogen atom such as a bromine atom or an iodine atom, n is an integer of 0 to 3)
3. The semiconductor device according to claim 1, comprising a reaction product with a hydrolysis product of a halogenated silane represented by the formula: 4. A step of applying a coating liquid containing SiO ₂ particles and a binder on the underlayer structure, and heat treating the structure coated with the coating liquid to form an insulating film having voids between the SiO ₂ particles. Forming the SiO ₂ particles, wherein the SiO ₂ particles have a particle size in a range of 50 to 5 nm, and the heat treatment step is performed in a range of 350 ° C. to 400 ° C.
A method for manufacturing a semiconductor device, wherein the method is performed in an inert gas having an oxygen concentration of 1% or less. 5. A method for manufacturing a semiconductor device, comprising: a step of forming an interlayer insulating film; and a step of forming a CVD insulating film on the interlayer insulating film. A step of applying a coating solution containing SiO ₂ particles in a range of 50 to ₅ nm and a binder, and heat treating the structure coated with the coating solution to form the SiO ₂
Forming an insulating film having voids between particles, wherein the step of forming the CVD insulating film is performed so that the CVD insulating film does not substantially penetrate into the interlayer insulating film. Manufacturing method of a semiconductor device. 6. The heat treatment step is performed at 350 ° C. to 400 ° C.
The method according to claim 5, wherein the method is performed at a temperature of ° C. 7. The method according to claim 1, wherein the permeation is a particle diameter of 2
6. The method for manufacturing a semiconductor device according to claim 5, wherein the number is twice or less. 8. The method of forming a CVD insulating film according to claim 1, wherein
a step of forming a CVD-SiO ₂ film using iH ₄ and N ₂ O as raw materials. The step of forming the CVD-SiO ₂ film is performed when the CVD-SiO ₂ film is formed on a dense substrate. Pressure and / or N for optimal conditions
6. The method of manufacturing a semiconductor device according to claim 5, wherein the method is performed by increasing the flow rate of ₂ O. 9. The method according to claim 9, wherein the first C layer is formed on the first interlayer insulating film.
Forming a VD film; forming a first opening in the first CVD film; forming a second interlayer insulating film on the first CVD film; Forming a second CVD film on a second interlayer insulating film; and forming a second CVD film in the second CVD film corresponding to the first opening and larger than the first opening. Forming a second opening; and performing dry etching on the second interlayer insulating film through the second opening to selectively act on the second interlayer insulating film. In the second interlayer insulating film, the second
Forming a groove corresponding to the opening of the first interlayer insulating film so that the groove penetrates the second interlayer insulating film; and selectively forming the first interlayer insulating film with respect to the first interlayer insulating film. Forming a through hole corresponding to the first opening in the first interlayer insulating film by performing dry etching acting on the groove through the groove and the first opening; And a step of filling the through hole with a conductive pattern. The step of forming the through hole in the first interlayer insulating film is continuous with the step of forming the groove in the second interlayer insulating film. 9. The method according to claim 5, wherein the step is executed.
The manufacturing method of the semiconductor device described in the above. 10. A step of forming the first CVD film on the first interlayer insulating film; a step of forming the second interlayer insulating film on the first CVD film; Forming the second CVD film on the second interlayer insulating film, the second CVD film, the second interlayer insulating film thereunder, and the first CVD film thereunder; The first under it
Forming a through hole by penetrating through the interlayer insulating film, and forming a groove corresponding to the second opening with respect to the second CVD film and the second interlayer insulating film. First CV
9. The method according to claim 5, further comprising the step of: performing dry etching using the D film as an etching stopper to form the groove so as to penetrate the second interlayer insulating film.