JPH10283250A - Memory access controller, memory access control method and storage medium storing program readable by computer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To accelerate the transfer speed of data to a memory without changing the wait number of system clocks to a CPU by switching the frequency of the system clocks to be selected based on a computed data transfer speed. SOLUTION: A crystal oscillator 52 which is a signal generation means and a clock generation part 54 generate the selectable plural system clocks of the different frequencies. A decoder 57 which is a detection means detects the specification information (information of 4 bits for instance of memory sense signals 61) of a memory chip (DRAM) added to RAM slots 55 and 56 which are extension slots. A gate array 51 which is an arithmetic means computes the data transfer speed for each selectable system clock based on the specification information detected by the detection means. Then, a PLL clock generation part 53 which is a control means switches and controls the frequency of the system clock to be selected based on the data transfer speed computed by the arithmetic means.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory access control device, a memory access control method, and a storage medium in which a computer readable program can be added, by which a memory device can be expanded by connecting a memory device via an expansion slot. Things.

[0002]

2. Description of the Related Art Conventionally, a data processing device capable of expanding a memory by expanding and connecting a memory device (SIMM, DIMM, etc.) through an expansion slot has been put to practical use. In this case, an additional RAM-
There is a signal that informs the system of the access speed to the SIMM (DIMM), and it is prohibited to change the weight of the RAM-SIMM based on the speed or to use the RAM-SIMM whose speed is less than the specified speed. .

[0003]

SUMMARY OF THE INVENTION For example, a RAM-SIMM having a low access speed (for example, 70 nsec)
When the memory bank is mounted, the memory bank becomes slow, and if the frequency of accessing the area increases, the performance decreases.

On the other hand, when a memory about 10 ns slower than the standard product is mounted with a capacity twice that of the standard memory, for example, the PL
It may be higher in terms of total performance if the frequency of the system clock composed of L is slightly lowered and all RAM areas are accessed with the same number of waits. That is, it may be better not to add the number of waits of the RAM by changing the system clock constituted by the PLL based on the capacity and access speed of the memory mounted by the user.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to change the frequency of a system clock to a lower frequency side in accordance with the specification of an added memory chip. Another object of the present invention is to provide a memory access control device and a memory access control method capable of improving a data transfer speed to a memory without changing the number of system clock waits for a CPU, and a storage medium storing a computer-readable program.

[0006]

According to a first aspect of the present invention, there is provided a signal generating means for generating a plurality of selectable system clocks having different frequencies and detecting specification information of a memory chip added to an expansion slot. Detecting means for calculating, a calculating means for calculating a data transfer rate for each selectable system clock based on the specification information detected by the detecting means, and a system to be selected based on the data transfer rate calculated by the calculating means Control means for switching and controlling the frequency of the clock.

According to a second aspect of the present invention, the memory chip comprises an extended RAM memory.

A third invention according to the present invention is a memory access control method for controlling access to a memory added to an expansion slot based on a plurality of selectable system clocks of different frequencies generated, A detecting step of detecting specification information of a memory chip added to the expansion slot; a calculating step of calculating a data transfer rate for each selectable system clock based on the detected specification information; and a calculated data transfer rate Switching the frequency of the system clock to be selected based on the

A fourth invention according to the present invention stores a computer-readable program for controlling access to a memory added to an expansion slot based on a plurality of system clocks having different selectable frequencies to be generated. A detecting step of detecting specification information of a memory chip added to an expansion slot, and a calculating step of calculating a data transfer rate for each selectable system clock based on the detected specification information. And a switching step of switching a frequency of a system clock to be selected based on the calculated data transfer speed. The computer-readable program is stored in a storage medium.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Before describing the configuration of the present embodiment, the configurations of a laser beam printer and an ink jet printer suitable for applying the present embodiment will be described with reference to FIGS.
This will be described with reference to FIG. The printer to which the present embodiment is applied is not limited to a laser beam printer and an ink jet printer, and it goes without saying that a printer of another printing method may be used.

FIG. 1 is a cross-sectional view showing the structure of a first output device to which the present invention can be applied, for example, a case of a laser beam printer (LBP).

In FIG. 1, reference numeral 1500 denotes an LBP main body, which inputs and stores print information (character codes, etc.), form information, microinstructions, and the like supplied from an externally connected host computer, and stores these information. , A corresponding character pattern, form pattern, or the like is created, and an image is formed on a recording medium such as a recording sheet. An operation panel 1501 includes switches for operation, an LED display, and the like.

A printer control unit 1000 controls the entire LBP body 1500 and analyzes character information and the like supplied from a host computer.

The printer control unit 1000 mainly converts the video signal into a video signal having a character pattern corresponding to the character information and outputs the video signal to the laser driver 1502. The laser driver 1502 is a circuit for driving the semiconductor laser 1503, and switches on / off a laser beam 1504 emitted from the semiconductor laser 1503 according to an input video signal. The laser beam 1504 is a rotary polygon mirror 1505
The scanning exposure is performed on the electrostatic drum 1506 by swinging in the horizontal direction.

As a result, an electrostatic latent image of a character pattern is formed on the electrostatic drum 1506. This latent image is developed by a developing unit 1507 provided around the electrostatic drum 1506, and then transferred to a recording sheet.
A cut sheet is used for the recording paper, and the cut sheet recording paper is a paper cassette 150 mounted on the LBP body 1500.
The sheet is then taken in the apparatus by a paper feed roller 1509, a conveyance roller 1510, and a conveyance roller 1511, and supplied to an electrostatic drum 1506. Also, L
The BP main body 1500 has at least one or more card slots (not shown), and is configured so that an optional font card and a control card (emulation card) having a different language system can be connected in addition to the built-in font.

FIG. 2 is an external view showing the configuration of a second output device to which the present invention can be applied, and shows, for example, the case of an ink jet recording device (IJRA).

In the figure, a helical groove 5004 of a mode screw 5005 that rotates via driving force transmission gears 5011 and 5009 in conjunction with forward and reverse rotation of a driving motor 5013.
The carriage HC that engages with a pin (not shown)
And is reciprocated in the directions of arrows a and b via the guide rail 5003. An ink jet cartridge IJC including an ink jet IT and an ink jet head IJH is mounted on the carriage HC.

Reference numeral 5002 denotes a paper pressing plate, which presses paper against the plantain 5000 in the carriage moving direction. Reference numerals 5007 and 5008 denote photocouplers, which function as home position detecting means for confirming the presence of the carriage lever 5006 in this region and switching the rotation direction of the drive motor 5013. Reference numeral 5016 denotes a member that supports a cap member 5022 that caps the entire surface of the recording head. Reference numeral 5015 denotes a suction unit that suctions the inside of the cap, and performs suction recovery of the recording head through an opening 5023 in the cap. Reference numeral 5017 denotes a cleaning blade which can be moved in the front-rear direction by a member 5019. Reference numeral 5018 denotes a main body support plate that supports the cleaning blade 5017 and the member 5019.

Reference numeral 5012 denotes a lever for starting suction for recovery of suction. The lever 5012 moves with the movement of the cam 5020 engaged with the carriage HC, and the driving force from the drive motor 5013 is transmitted by a known transmission means such as clutch switching. Movement is controlled.

The capping, cleaning, and suction recovery are configured so that when the carriage HC comes to the home position side area, desired operations can be performed at the corresponding positions by the action of the lead screw 5005. What is necessary is just to be comprised so that a desired operation | movement may be performed at a timing.

FIG. 3 is a block diagram illustrating a control configuration of the second output device shown in FIG.

In the figure, 1700 is an interface for inputting a recording signal, 1701 is an MPU, and 1702 is an RO
M stores a control program executed by the MPU 1701, host print information, and the like. 1703 is DRAM
To store various data (the recording signal and recording data supplied to the head). Reference numeral 1704 denotes a gate array that controls supply of output data to the print head 1708, and includes an interface 1700, an MPU 1701,
Data transfer between the DRAMs 1703 is also controlled.

Reference numeral 1710 denotes a carrier motor which conveys the recording head 1708. A conveyance motor 1709 conveys a recording sheet. A head driver 1705 drives the recording head (inkjet head IJH). Reference numeral 1706 denotes a motor driver,
09 is driven. A motor driver 1707 drives the carrier motor 1710.

In the above-described recording apparatus, when input information is input from a host computer 100 to be described later via the interface 1700, the input information is output between the gate array 1704 and the MPU 1701 as output information for printing. Is converted to Then, the motor drivers 1706 and 1707 are driven, and the recording head is driven according to the output information sent to the head driver 1705 to execute printing.

Note that the MPU 1702 is interface 1
Communication processing with the host computer 100 described below is possible via the network 700, and the host computer 100, which will be described later, can be notified of memory information and resource data related to the DRAM 1703 and host print information in the ROM 1702.

FIG. 4 is a block diagram of a printer control system to which a memory access control device according to an embodiment of the present invention can be applied. For example, a laser printer (see FIG. 1)
Will be described as an example. If this function is executed, the present invention can be applied to a single device, a system including a plurality of devices, and a system in which processing is performed via a network such as a LAN. Needless to say.

In the figure, reference numeral 3000 denotes a host computer which executes document processing in which graphics, images, characters, tables (including spreadsheets, etc.) are mixed based on a document processing program or the like stored in a program ROM of the ROM 3. C
The CPU 1 has a PU 1 and controls each device connected to the system bus 4 as a whole.

The program ROM of the ROM 3
Stores a control program of the CPU 1 and the like.
The font ROM stores font data and the like used in the above-described document processing, and the data ROM of the ROM 3 stores various programs used in the above-described document processing and the like. Reference numeral 2 denotes a RAM, which functions as a main memory, a work area, and the like of the CPU 1.

5 is a keyboard controller (KBC)
Controls the key input from the keyboard 9 or a pointing device (not shown). 6 is a CRT controller (C
RTC) controls the display on a CRT display (CRT) 10. 7 is a disk controller (DKC)
It controls access to an external memory 11 such as a hard disk (HD) or a floppy disk (FD) that stores a boot program, various applications, photo data, user files, edited files, and the like. Reference numeral 8 denotes a printer controller (PRTC), which is connected to a printer 150 via a predetermined bidirectional interface (interface) 21.
0 to execute communication control processing with the printer 1500.

The CPU 1 executes, for example, a process of rasterizing an outline font in the display information RAM set on the RAM 2, and executes the process on the CRT 10.
YSIWYG is possible. Further, the CPU 1
Various registered windows are opened based on a command specified by a mouse cursor or the like (not shown) on the RT 10,
Perform various data processing.

In the printer 1500, reference numeral 12 denotes a printer CPU, which controls various devices connected to the system bus 15 based on a control program or the like stored in a program ROM of the ROM 13 or a control program or the like stored in the external memory 14. Control access to
An image signal is output as output information to a printing unit (printer engine) 17 connected via a printing unit interface 16. The program ROM of the ROM 13
Stores a control program of the printer CPU 12 as shown in the flowcharts of FIGS.

The font ROM of the ROM 13 stores font data and the like used for generating the output information. Further, in the case of a printer having no external memory 14 such as a hard disk in the data ROM of the ROM 13, Stores information used on the host computer.

The printer CPU 12 is capable of communicating with the host computer 3000 via the input unit 18 and transmits information and the like in the printer to the host computer 30.
00 is configured to be notified. 19 is the CPU 1
RAM functioning as main memory, work area, etc.
The memory capacity can be expanded by an optional RAM connected to an expansion port (an expansion slot on the motherboard) not shown. In addition,
The RAM 19 is used for an output information development area, an environment data storage area, an NVRAM, and the like. The RAM 19 is provided with a RAM mounted from the beginning and an optional RAM (RAM-DIMM, RAM-RAM- SIMM, etc.), and has an interface for accessing them.

The external memory 14 such as a hard disk (HD) or an IC card is provided with a disk controller (D
KC) 20 controls access. External memory 1
Reference numeral 4 is connected as an option and stores font data, emulation programs, form data, and the like. The operation panel 1501 is provided with switches for operation, an LED display, and the like.

The above-mentioned external memory is not limited to one, and at least one external memory is provided. In addition to the built-in fonts, an optional font card and a plurality of external memories storing programs for interpreting printer control languages of different languages are connected. It may be configured to be able to do so. Further, an NVRAM (not shown) may be provided to store the printer mode setting information from the operation panel 1501.

FIG. 5 is a block diagram showing an example of the access control circuit of the RAM 19 shown in FIG. 4, and the same components as those in FIG. 4 are denoted by the same reference numerals.

In the figure, reference numeral 51 denotes a gate array,
An L clock generator 54, a PLL clock divider 53, and a decoder 57 are provided. A crystal oscillator 52 oscillates a clock having a predetermined frequency. The clock generation unit 54
The clock divider 53 generates a system clock 58 from the divided clock. Reference numerals 55 and 56 denote RAM slots in which a RAM-SIMM having a predetermined capacity is mounted.

The RAM slots 55, 56 and R
The AM 19 is configured so that the memory space can be expanded so that it can be accessed by a continuous address via the address bus 59.
The address bus 59 is a time-division row address,
The column address is output.

Reference numeral 60 denotes an nRAS signal for controlling each bank. The RAM 19 serving as a standard RAM is controlled by RAS0, the RAM slot 55 (SLOT1) is controlled by RAS1, and the RAM slot 56 (SLOT2) is controlled by RAS2.

Reference numeral 61 denotes a memory sense signal of each SLOT.
There are four slots per slot, two of which represent speed and the other two represent memory capacity. 62 is a data bus, 6
Numeral 3 denotes a column strobe signal common to each RAM, which is composed of column strobe signals CAS3 to CAS0.

In the memory control circuit thus configured, each SLO input to the gate array (GA) 51
The memory sense signal 61 of T is transmitted to the gate array (GA) 5
1 is decoded by a decoder unit 57 composed of internal hardware, a frequency-divided clock of the PLL is determined by a data signal of the decoder unit 57, a system clock 58 is generated by a clock generation unit 54, and the system clock 58 is generated.
Then, the whole system operates.

In this embodiment, the case where the frequency division ratio of the PLL clock frequency divider 53 is determined based on a hardware decode signal has been described. The clock division ratio of the PLL clock division unit 53 may be determined by IO writing.

Further, the user may be configured so that whether to change the speed of the system clock 58 can be performed from an external operation panel.

FIGS. 6 and 7 are timing charts for explaining access timing to the RAM 19 shown in FIG. FIG. 6 shows that the system frequency is 25, for example.
MHz system clock (one stage 40 ns)
In the case where the cycle of the CPU 12 starts and data is taken in every clock in the burst access four clocks after the first access, a total of seven clocks are required for "4, 1, 1, 1" to take in four words. 280 ns
Such a memory medium is used. Figure 7 shows 10ns slow RAM
-Corresponds to the timing when one weight is added to data because the SIMM is mounted.

Here, the RAM-SIM worn by the user
Since M is a module that is 10 ns slower than the standard RAM, assuming that 5 ns is not enough for burst access, it takes "400" ns to access the same 4-word read by "4, 2, 2, 2".

If the system frequency is 22.22
MHz (one stage 45 ns), this RAM can be accessed with the same number of waits.
4 words are possible in 5 "ns, and this RAM-SIMM
If it is limited to this, this will be faster.

Here, assuming that the standard 4 MB and the RAM-SIMM are 4 MB, in this system, 30% in the standard RAM, 30% in the extended RAM, 10% in the ROM,
Assume that the cache is accessed by 20% and the other hardware is accessed by 10%. The fact that the standard RAM having the faster access speed has the same ratio means that the standard RA
This means that M has a high access frequency.

In this case, all are operated by the system clock, which is all 1.125 times slower. Only the slow RAM-SIMM is 0.7875 times faster, but the overall system is about 2% slower.

However, here, the RAM-SIMM is 16M.
B, RAM 10 ns slower than the same standard installed earlier
For example, if the access ratio is 15% in the standard RAM and 5% in the
It is assumed that 0%, 7% of ROM, 18% of CPU cache, and 10% of other hardware are accessed. In this case, if the frequency of the entire system is lowered, the calculation becomes about 4.5% systemically faster.

Hereinafter, a characteristic configuration of the present embodiment will be described with reference to FIG.

In the memory access control device configured as described above, the signal generating means (the crystal oscillator 5) for generating a plurality of selectable system clocks of different frequencies.
2, a clock generation unit 54) and a memory chip (DRA) added to an expansion slot (RAM slot 55, 56).
M) detecting means (decoder 57) for detecting specification information (for example, 4-bit information of the memory sense signal 61);
A calculating means (gate array 51) for calculating a data transfer rate for each selectable system clock based on the specification information detected by the detecting means, and a system to be selected based on the data transfer rate calculated by the calculating means Since it has control means (PLL clock generation unit 53) for switching and controlling the frequency of the clock, it has a simple configuration in which the frequency of the system clock is changed to a lower frequency in accordance with the specification of the memory chip to be added. The data transfer speed to the memory can be improved without changing the number of waits of the system clock.

The operation of changing the memory access environment of the memory access control device according to the present invention will be described below with reference to the flowchart shown in FIG.

FIG. 8 is a flowchart showing an example of a memory access environment change processing procedure of the memory access control device according to the present invention. Note that (1) to (6) indicate each step.

First, it is determined from the capacitance sense signal set in the RAM-SIMM whether or not the RAM-SIMM is optional (1). If it is determined that the RAM-SIMM is mounted, a signal for determining the speed of the RAM-SIMM is provided. And whether the access speed is lower than the access speed of the standard RAM (2).
It is determined whether the capacity of the IMM is larger than a predetermined value (3). If it is determined that the capacity is larger, the access time is calculated (4), and whether the access time is shorter by changing the frequency of the system clock is determined. Is determined (5), and YES
If so, the system clock is changed (6), and the process returns.

On the other hand, if NO is determined in steps (1) to (3) and step (5), the process returns.

Thus, the RAM-S to be extendedly mounted is
If the IMM has a large capacity and the performance is rather improved even if the system clock is slowed, the access time can be improved by changing the system clock to an appropriate speed.

Hereinafter, the characteristic configuration of this embodiment will be described with reference to FIG.

Access to a memory (for example, a DRAM-SIMM) added to an expansion slot (RAM slots 55 and 56) based on a plurality of system clocks having different frequencies which can be selected and generated as described above. A memory access control method for controlling, or a computer controlling access to a memory (for example, DRAM-SIMM) added to an expansion slot based on a plurality of system clocks of different selectable frequencies generated. Detecting the specification information of the memory chip added to the expansion slot in the storage medium storing the various programs (steps (1) to (1) in FIG. 8).
(3)), an operation step of calculating a data transfer rate for each system clock selectable based on the detected specification information (step (4) in FIG. 8), and based on the calculated data transfer rate. A switching step of switching the frequency of the system clock to be selected (step (5) in FIG. 8,
(6)), the system has a simple configuration in which the frequency of the system clock is changed to a lower frequency in accordance with the specifications of the memory chip to be added, without changing the number of waits of the system clock for the CPU. Data transfer speed can be improved.

Hereinafter, the configuration of a data processing program that can be read by the memory access control device according to the present invention will be described with reference to a memory map shown in FIG.

FIG. 9 is a view for explaining a memory map of a storage medium for storing various data processing programs readable by the memory access control device according to the present invention.

Although not shown, information for managing a group of programs stored in the storage medium, for example, version information, a creator, etc. is also stored, and information dependent on the OS or the like on the program reading side, for example, a program is An icon or the like for identification display may also be stored.

Further, data dependent on various programs is also managed in the directory. In addition, a program for installing various programs on a computer or a program for decompressing a program to be installed when the program to be installed is compressed may be stored.

The functions shown in FIG. 7 in this embodiment may be performed by a host computer by a program installed from the outside. In this case, the present invention is applied even when a group of information including a program is supplied to the output device from a storage medium such as a CD-ROM, a flash memory, or an FD, or from an external storage medium via a network. Things.

As described above, the storage medium storing the program codes of the software for realizing the functions of the above-described embodiments is supplied to the system or the apparatus, and the computer (or CPU or MP) of the system or the apparatus is supplied.
It goes without saying that the object of the present invention is also achieved when U) reads and executes the program code stored in the storage medium.

In this case, the program code itself read from the storage medium realizes the novel function of the present invention, and the storage medium storing the program code constitutes the present invention.

As a storage medium for supplying the program code, for example, a floppy disk, hard disk, optical disk, magneto-optical disk, CD-ROM, C
DR, magnetic tape, nonvolatile memory card, RO
M, EEPROM and the like can be used.

When the computer executes the readout program code, not only the functions of the above-described embodiment are realized, but also the OS (Operating System) running on the computer based on the instruction of the program code. ) And the like perform part or all of the actual processing, and the processing realizes the functions of the above-described embodiments.

Further, after the program code read from the storage medium is written into a memory provided in a function expansion board inserted into the computer or a function expansion unit connected to the computer, based on the instructions of the program code, The CPU provided in the function expansion board or function expansion unit performs part or all of the actual processing,
It goes without saying that a case where the function of the above-described embodiment is realized by the processing is also included.

[0069]

As described above, according to the first and second aspects of the present invention, a signal generating means for generating a plurality of selectable system clocks having different frequencies and an expansion slot are provided. Detecting means for detecting specification information of the memory chip; calculating means for calculating a data transfer rate for each selectable system clock based on the specification information detected by the detecting means; and data transfer rate calculated by the calculating means Control means for switching the frequency of the system clock to be selected based on the memory clock. Therefore, a simple configuration in which the frequency of the system clock is changed to a lower frequency side in accordance with the specifications of the memory chip to be added is provided.
The data transfer speed to the memory can be improved without changing the number of waits of the system clock for the PU.

According to the third and fourth inventions, there is provided a memory access control method for controlling access to a memory added to an expansion slot based on a plurality of selectable system clocks having different frequencies. Or a computer-readable storage medium storing a computer-readable program for controlling access to a memory added to an expansion slot based on a plurality of system clocks of different frequencies that can be selected and generated. A detecting step of detecting specification information of a memory chip to be performed; a calculating step of calculating a data transfer rate for each selectable system clock based on the detected specification information; and a selecting step based on the calculated data transfer rate. And a switching step of switching the frequency of the system clock to be added. In a simple configuration of changing the frequency of the system clock to the low frequency side in accordance with the specifications of Richippu, it is possible to improve the data transfer speed to the memory without changing the weight of the system clock to the CPU.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a configuration of a first output device to which the present invention can be applied.

FIG. 2 is an external view showing a configuration of a second output device to which the present invention can be applied.

FIG. 3 is a block diagram illustrating a control configuration of a second output device illustrated in FIG.

FIG. 4 is a block diagram of a printer control system to which a memory access control device according to an embodiment of the present invention can be applied.

FIG. 5 is a block diagram illustrating an example of an access control circuit of the RAM illustrated in FIG. 4;

FIG. 6 is a timing chart illustrating access timing to the RAM shown in FIG. 5;

FIG. 7 is a timing chart illustrating access timing to the RAM shown in FIG. 5;

FIG. 8 is a flowchart illustrating an example of a memory access environment change processing procedure of the memory access control device according to the present invention.

FIG. 9 is a diagram illustrating a memory map of a storage medium that stores various data processing programs that can be read by the memory access control device according to the present invention.

[Explanation of symbols]

 12 Printer CPU 19 RAM 51 Gate Array 52 Crystal Oscillator 53 PLL Clock Divider 57 Decoder 58 System Clock

Claims (4)

[Claims] 1. A signal generating means for generating a plurality of selectable system clocks of different frequencies, a detecting means for detecting specification information of a memory chip added to an expansion slot, and the specification information detected by the detecting means Computing means for computing a data transfer rate for each selectable system clock based on the following: and control means for switching and controlling the frequency of a system clock to be selected based on the data transfer rate computed by the computing means. A memory access control device characterized by the above-mentioned. 2. The memory access control device according to claim 1, wherein said memory chip comprises an extended RAM memory. 3. A memory access control method for controlling access to a memory added to an expansion slot based on a plurality of system clocks of different frequencies that can be selected, wherein the memory chip is added to the expansion slot. A detecting step of detecting the specification information of the above; a calculating step of calculating a data transfer rate for each selectable system clock based on the detected specification information; and a system clock to be selected based on the calculated data transfer rate. And a switching step of switching the frequency of the memory access. 4. A storage medium storing a computer-readable program for controlling access to a memory added to an expansion slot based on a plurality of system clocks having different selectable frequencies generated, the program comprising: A detecting step of detecting specification information of a memory chip added to the slot; a calculating step of calculating a data transfer rate for each selectable system clock based on the detected specification information; And a switching step of switching a frequency of a system clock to be selected based on the computer-readable program.