JPH102820A - Semiconductor pressure converter - Google Patents

Semiconductor pressure converter

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Publication number
JPH102820A
JPH102820A JP15198696A JP15198696A JPH102820A JP H102820 A JPH102820 A JP H102820A JP 15198696 A JP15198696 A JP 15198696A JP 15198696 A JP15198696 A JP 15198696A JP H102820 A JPH102820 A JP H102820A
Authority
JP
Japan
Prior art keywords
resistor
resistance
pressure transducer
terminal
semiconductor pressure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15198696A
Other languages
Japanese (ja)
Inventor
Kazuyuki Kato
和之 加藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP15198696A priority Critical patent/JPH102820A/en
Publication of JPH102820A publication Critical patent/JPH102820A/en
Pending legal-status Critical Current

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Abstract

PROBLEM TO BE SOLVED: To regulate the sensitivity and zero point of a pressure converter by providing a plurality of resistance networks within a processing circuit for strain gauge bridge output, selectively connecting a regulating resistance of every column by an external signal, and varying the output current of the resistance networks. SOLUTION: This device has resistance networks RM1-RMd of the same structure in which input terminals I1-I3 are connected to a bridge piece side output Vg, a power source Vcc, and a ground Gnd, respectively, output terminals O1-O3 are connected to the reversion input terminal of an arithmetic amplifier OP1, and current bypassing terminals A1-A3 are connected to the output of a buffer arithmetic amplifier OP3. The network RM1 has a start end resistance Rag, unit serial resistances Ra1-Ra4 having a resistance value ρ1 , a terminal serial resistance Ra5 having a resistance value 2ρ1 , regulating resistances of every column ra1-ra5, and switches Sa1-Sa5 for selectively connecting resistances ra1-ra5 to the terminal O1 or A1 by an external signal. The sensitivity can be regulated with a resolution of 25 in the network RM1, and the zero point potential is regulated in the networks RM2, RM3.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は例えば自動車用な
ど、小型,軽量で高精度の特性が要求される用途に適し
た半導体圧力変換器であって、特にその出力信号の感度
や零点電位の調整、その温度特性の補償等を外部からの
デジタル信号によって容易に行える回路を内蔵した半導
体圧力変換器に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor pressure transducer suitable for applications requiring small, lightweight and high-precision characteristics, such as for automobiles, and more particularly to the adjustment of the sensitivity of output signals and the zero-point potential. The present invention relates to a semiconductor pressure transducer having a built-in circuit for easily compensating its temperature characteristics and the like by using an external digital signal.

【0002】なお以下各図において同一の符号は同一も
しくは相当部分を示す。
[0002] In the drawings, the same reference numerals indicate the same or corresponding parts.

【0003】[0003]

【従来の技術】一般に半導体圧力変換器は歪みゲージの
出力を増幅する回路を内蔵し、且つ圧力感度の調整,零
点電位の調整をした状態で用いられる。特に自動車用な
ど温度変化の大きい環境下で使われる場合、前記感度や
零点電位の温度特性の補償が必要となる。
2. Description of the Related Art In general, a semiconductor pressure transducer has a built-in circuit for amplifying the output of a strain gauge, and is used in a state where a pressure sensitivity is adjusted and a zero point potential is adjusted. In particular, when used in an environment with a large temperature change, such as for an automobile, it is necessary to compensate for the temperature characteristics of the sensitivity and the zero point potential.

【0004】モノリシックICやハイブリッドICから
なる小型軽量の圧力変換器において、これらの調整や補
償を行うために広く用いられている方法としては、レー
ザやサンドブラストによる抵抗のトリミングが挙げられ
る。このトリミングは図4に示すように、半導体圧力変
換器内の信号処理回路中の例えば導体電極1の間にトリ
ミングできる大きさを持つ厚膜もしくは薄膜の抵抗体2
を設けて置き、この抵抗体2の一部をレーザビーム4に
よる熱で気化もしくは絶縁物化したり、又はサンドブラ
ストで機械的に削ることにより、抵抗値をアナログ的に
変化させて目標の特性になるようにするものである。な
お図4の3はこのトリミングによって除去もしくは絶縁
物化された抵抗体2の一部である。
[0004] In a small and light pressure transducer composed of a monolithic IC or a hybrid IC, a widely used method for adjusting or compensating them is trimming of a resistor by laser or sandblast. This trimming is, as shown in FIG. 4, a thick-film or thin-film resistor 2 having a size that can be trimmed between, for example, conductor electrodes 1 in a signal processing circuit in a semiconductor pressure transducer.
Is provided, and a part of the resistor 2 is vaporized or insulated by the heat of the laser beam 4 or mechanically cut by sand blast to change the resistance value in an analog manner to obtain the target characteristic. Is to do so. Note that reference numeral 3 in FIG. 4 denotes a part of the resistor 2 removed or converted into an insulator by the trimming.

【0005】[0005]

【発明が解決しようする課題】上述した従来のトリミン
グ方法では抵抗値をアナログ的に変化させるため、特に
LカットやWカットなどの手法を用いることにより、調
整の分解能を容易に上げることができる。しかしながら
このトリミング方法には以下のような問題がある。 (1)微細なパタ−ンの加工を行うため、事前に半導体
圧力変換器のチップ又は回路基板の位置合わせが必要で
あり、また精度を向上させる程、加工に時間が掛かる。 (2)トリミングされた部分との境界の抵抗体部分は材
質的に不安定であり、そのため抵抗が経時変化し易い。 (3)トリミングの際は、チップもしくは回路基板がむ
きだしの状態になるため、これに汚れや傷が付き易い。
In the conventional trimming method described above, since the resistance value is changed in an analog manner, the resolution of the adjustment can be easily increased, particularly by using a method such as L-cut or W-cut. However, this trimming method has the following problems. (1) In order to process a fine pattern, it is necessary to align a chip or a circuit board of a semiconductor pressure transducer in advance, and it takes more time to improve the accuracy. (2) The resistor portion at the boundary with the trimmed portion is unstable in material, so that the resistance is liable to change with time. (3) At the time of trimming, the chip or the circuit board is exposed, so that the chip or the circuit board is easily damaged or damaged.

【0006】そこで本発明はこのような問題を解消し、
事前の位置合わせを必要とせず、精度に無関係に短時間
でのトリミングが可能であり、また抵抗の経時変化も少
なく、実装が完了した状態でのトリミングが可能な、そ
して比較的簡単な回路で構成した半導体圧力変換器を提
供することを課題とする。
Accordingly, the present invention solves such a problem,
It does not require pre-positioning, can be trimmed in a short time regardless of accuracy, has little change in resistance over time, can be trimmed after mounting is completed, and is a relatively simple circuit. An object of the present invention is to provide a semiconductor pressure transducer having the above structure.

【0007】[0007]

【課題を解決するための手段】前記の課題を解決するた
めに請求項1の半導体圧力変換器では、シリコンダイヤ
フラム上に拡散により形成配置され、所定の電源電圧
(Vcc)及び接地電位(Gnd)が夫々所定の端子に
与えられ、複数個からなる歪みゲージ(RG1〜RG
4)と、ダイヤフラムに加わる圧力に応じて発生した歪
みゲージの出力電圧(Vg)に対応する電流をその反転
入力端子と出力端子とを結ぶ帰還抵抗(Rf)に流して
電圧に変換し、この半導体圧力変換器の出力電圧(Vo
ut)とする演算増幅器(OP1)を設けられ、歪みゲ
ージの出力電圧の増幅,調整を行う信号処理回路とを、
抵抗基板を含み得る同一もしくは複数のシリコンチップ
上に備えた半導体圧力変換器において、前記信号処理回
路内に、夫々第1,第2,第3の3つの回路網端子を持
ち、第1の回路網端子(入力端子I1など)にはこの半
導体圧力変換器内に存在又は発生する固定又は可変の電
位であって前記第2又は第3の回路網端子の入力電位と
は異なる所定の1又は複数の電位の何れかが入力され、
第2の回路網端子(出力端子O1など)は前記演算増幅
器の反転入力端子に接続され、第3の回路網端子(電流
バイパス用端子A1など)は(演算増幅器OP3からな
るバッファ回路などを介し)第2の回路網端子と略同電
位で、前記演算増幅器とは独立した部位に接続されてな
る抵抗回路網であって、第1の回路網端子(入力端子I
1など)と第3の回路網端子との間に、少なくとも第1
の回路網端子側より順に同一抵抗値(ρ1 など)を有す
る複数の単位直列抵抗(Ra1〜Ra4など)及び、こ
の単位直列抵抗の倍の抵抗値(2ρ1 など)を有する終
端直列抵抗(Ra5など)が1つずつ直列に接続された
抵抗直列回路を持ち、更にこの抵抗直列回路を成す複数
の単位直列抵抗及び終端直列抵抗の夫々の第1の回路網
端子側の端に、1対1に前記単位直列抵抗の倍の抵抗値
(2ρ1 など)を有する桁別調整抵抗(ra1〜ra5
など)の夫々の一方の端が接続され、この各桁別調整抵
抗の他方の端が第2又は第3の回路網端子の何れかに選
択的に接続されるような1又は複数の抵抗回路網(RM
1〜RM5など)と、外部からのデジタル信号に応じて
前記の各抵抗回路網の各桁別調整抵抗の選択的な接続
を、電源の消失時にもこの接続が記憶されるように行う
選択接続手段とを設け、前記演算増幅器の反転入力端子
において前記の各抵抗回路網の第2の回路網端子に選択
接続された桁別調整抵抗から入力された電流が加算さ
れ、前記帰還抵抗により電圧に変換されてこの半導体圧
力変換器の前記出力電圧に重畳されるようにする。
According to a first aspect of the present invention, there is provided a semiconductor pressure transducer which is formed on a silicon diaphragm by diffusion, and has a predetermined power supply voltage (Vcc) and a ground potential (Gnd). Are given to predetermined terminals, respectively, and a plurality of strain gauges (RG1 to RG
4) and a current corresponding to the output voltage (Vg) of the strain gauge generated according to the pressure applied to the diaphragm is passed through a feedback resistor (Rf) connecting the inverting input terminal and the output terminal to be converted into a voltage. Output voltage of semiconductor pressure transducer (Vo
ut), and a signal processing circuit for amplifying and adjusting the output voltage of the strain gauge,
A semiconductor pressure transducer provided on the same or a plurality of silicon chips that may include a resistance substrate, wherein the signal processing circuit has first, second, and third three network terminals, respectively, A predetermined or one or more fixed or variable potentials existing or generated in the semiconductor pressure transducer and different from the input potentials of the second or third network terminals are provided to the network terminal (such as the input terminal I1). Is input,
A second network terminal (such as an output terminal O1) is connected to the inverting input terminal of the operational amplifier, and a third network terminal (such as a current bypass terminal A1) is connected via a buffer circuit composed of an operational amplifier OP3. A) a resistor network connected to a portion independent of the operational amplifier at substantially the same potential as the second network terminal, the first network terminal (input terminal I
1) and the third network terminal
A plurality of unit series resistor having the same resistance value in order from the network terminal side (such as [rho 1) (such as Ra1~Ra4) and, terminating the series resistor having a fold resistance of the unit series resistance (such 2.rho 1) ( Ra5, etc.) are connected in series one by one, and one end of each of a plurality of unit series resistors and a terminating series resistor forming the resistor series circuit on the first network terminal side. The digitized adjusting resistors (ra1 to ra5) each having a resistance value (such as 2ρ1) twice the unit series resistance as 1
Or one or more resistor circuits, one end of each of which is connected, and the other end of each digit-wise adjustment resistor is selectively connected to either the second or third network terminal. Net (RM
1 to RM5) and a selective connection for selectively connecting each digit-adjustment resistor of each of the resistor networks according to an external digital signal so that the connection is stored even when the power is cut off. Means, and at the inverting input terminal of the operational amplifier, a current input from a digit-by-digit adjustment resistor selectively connected to a second network terminal of each of the resistor networks is added, and a voltage is added to the voltage by the feedback resistor. It is converted so as to be superimposed on the output voltage of the semiconductor pressure transducer.

【0008】また請求項2の半導体圧力変換器では、請
求項1に記載の半導体圧力変換器において、前記第1の
回路網端子に入力する電位を、前記圧力に応じて発生し
た歪みゲージの出力電位又は(演算増幅器OP2からな
るバッファ回路などを介し)この出力電位を信号処理し
た該出力電位に対応する電位、前記電源電圧、前記接地
電位の何れかとし、この半導体圧力変換器の出力電圧の
歪みゲージの圧力信号に対する感度又は(及び)零点電
位を前記外部からのデジタル信号に応じて調整し得るよ
うする。
According to a second aspect of the present invention, there is provided the semiconductor pressure transducer according to the first aspect, wherein a potential input to the first network terminal is output from a strain gauge generated according to the pressure. The potential or the potential corresponding to the output potential obtained through signal processing of the output potential (via a buffer circuit including an operational amplifier OP2), the power supply voltage, or the ground potential. The sensitivity or / and zero potential of the strain gauge to the pressure signal can be adjusted according to the external digital signal.

【0009】また請求項3の半導体圧力変換器では請求
項1又は2に記載の半導体圧力変換器において、前記帰
還抵抗が正の大きな温度依存性を有する抵抗(Rft)
を含み、この半導体圧力変換器の前記出力電圧の感度温
度特性を補償し得るようにする。また請求項4の半導体
圧力変換器では、請求項1ないし3の何れかに記載の半
導体圧力変換器において、前記抵抗回路網のうちの少な
くとも何れか1又は複数の抵抗回路網(RM4,RM5
など)の第1の回路網端子と抵抗直列回路との間に夫々
直列に温度依存性の大きい始端直列抵抗(Rdt,Re
tなど)が挿入され、この半導体圧力変換器の前記出力
電圧の感度温度特性又は(及び)零点電位の温度特性を
補償し得るようにする。
According to a third aspect of the present invention, in the semiconductor pressure transducer according to the first or second aspect, the feedback resistor has a large positive temperature dependency (Rft).
To compensate for the sensitivity-temperature characteristic of the output voltage of the semiconductor pressure transducer. According to a fourth aspect of the present invention, in the semiconductor pressure transducer according to any one of the first to third aspects, at least one or a plurality of resistance networks (RM4, RM5) among the resistance networks are provided.
Etc.) between the first network terminal and the resistor series circuit in series with each other.
t, etc.), so that the sensitivity temperature characteristic of the output voltage or / and the temperature characteristic of the zero potential of the semiconductor pressure transducer can be compensated.

【0010】また請求項5の半導体圧力変換器では、請
求項1ないし4の何れかに記載の半導体圧力変換器にお
いて、前記抵抗回路網のうちの少なくとも何れか1又は
複数の抵抗回路網の第1の回路網端子と第2の回路網端
子との間に夫々温度依存性の大きい始端抵抗(Ra0〜
Rc0などに対応する抵抗)が挿入され、この半導体圧
力変換器の前記出力電圧の感度温度特性又は(及び)零
点電位の温度特性を補償し得るようにする。
According to a fifth aspect of the present invention, there is provided a semiconductor pressure transducer according to any one of the first to fourth aspects, wherein at least one of the resistance networks or a plurality of the resistance networks is provided. The first end resistances (Ra0 to Ra0) having a large temperature dependency between the first network terminal and the second network terminal, respectively.
A resistance corresponding to Rc0 or the like is inserted so that the sensitivity temperature characteristic of the output voltage or the temperature characteristic of the zero-point potential of the semiconductor pressure transducer can be compensated.

【0011】本発明の作用は次の如くである。即ちシリ
コンダイヤフラム上の歪みゲージブリッジRG1〜RG
4の信号出力端子のうちの基準電位側端子G1と非反転
入力端子が同電位とされ、帰還抵抗Rfに歪みゲージブ
リッジの信号出力電圧Vgに比例した電流を流し、出力
端子にVgを増幅した変換器出力電圧Voutを発生す
る演算増幅器OP1を持つ半導体圧力変換器において、
その信号処理回路内に外部からのデジタル信号によって
スイッチを介し選択接続され、圧力変換器内の以下に述
べる各部位の電位を入力とする回路網入力端子から回路
網出力端子へ、少なくとも単位直列抵抗及び終端直列抵
抗からなる抵抗直列回路を介し、夫々2N (但しNは当
該の抵抗回路網内での当該の桁別調整抵抗が存在する段
(桁)の番号)の比率の電流を引き出す複数の桁別調整
抵抗を持つ抵抗回路網を1又は複数設け、その回路網出
力端子を演算増幅器OP1の反転入力端子に接続し、回
路網出力端子の電流を帰還抵抗Rfの電流に重畳して半
導体圧力変換器の出力電圧Voutを調整する。
The operation of the present invention is as follows. That is, the strain gauge bridges RG1 to RG on the silicon diaphragm
4, the reference potential side terminal G1 and the non-inverting input terminal among the signal output terminals are set to the same potential, a current proportional to the signal output voltage Vg of the strain gauge bridge flows through the feedback resistor Rf, and Vg is amplified at the output terminal. In a semiconductor pressure converter having an operational amplifier OP1 for generating a converter output voltage Vout,
The signal processing circuit is selectively connected by a digital signal from the outside via a switch, and receives at least a unit series resistance from a network input terminal to which a potential of each part described below in the pressure transducer is input to a network output terminal. And 2 N (where N is the number of the stage (digit) where the digit-specific adjustment resistor is present in the resistor network) through a resistor series circuit composed of a resistor and a series resistor. One or a plurality of resistor networks each having a digit-by-digit adjustment resistor are provided, the network output terminal of which is connected to the inverting input terminal of the operational amplifier OP1, and the current of the network output terminal is superimposed on the current of the feedback resistor Rf. Adjust the output voltage Vout of the pressure transducer.

【0012】このようにして抵抗回路網のうち、その回
路網入力端子の電位を歪みゲージブリッジの出力信号の
電位とした抵抗回路網RM1によって圧力変換器出力電
圧Voutの感度調整を行い、その回路網入力端子の電
位を電源電圧Vccとした抵抗回路網RM2、又は接地
電位Gndとした抵抗回路網RM3によって圧力変換器
出力電圧Voutの零点電位調整を行う。なお実施例で
は桁別調整抵抗が存在する段(桁)の全数(換言すれば
当該の抵抗回路網内の桁別調整抵抗又はスイッチの全
数)は5つであり、2-5の分解能での調整が可能とな
る。
In this way, in the resistance network, the sensitivity of the pressure transducer output voltage Vout is adjusted by the resistance network RM1 in which the potential of the network input terminal is set to the potential of the output signal of the strain gauge bridge. The zero point potential of the pressure transducer output voltage Vout is adjusted by a resistor network RM2 in which the potential of the network input terminal is the power supply voltage Vcc or a resistor network RM3 in which the potential of the network input terminal is the ground potential Gnd. In the embodiment, the total number of stages (digits) in which the digit-by-digit adjustment resistors exist (in other words, the total number of digit-by-digit adjustment resistors or switches in the resistor network concerned) is five, and the resolution at a resolution of 2 -5 is obtained. Adjustment is possible.

【0013】また演算増幅器OP1の帰還抵抗を正の大
きな温度依存性を持つ帰還抵抗Rftとしたり、前記回
路網入力端子と抵抗直列回路との間に直列に夫々温度依
存性の大きい始端直列抵抗Rdt,Ret等を挿入した
抵抗回路網RM4,RM5等を用いることで、圧力変換
器出力電圧Voutの感度や零点電位の温度特性を補償
する。
The feedback resistor of the operational amplifier OP1 may be a feedback resistor Rft having a large positive temperature dependency, or a start-point series resistor Rdt having a large temperature dependency may be connected in series between the network input terminal and the resistor series circuit. , Ret, etc., are used to compensate for the sensitivity of the pressure transducer output voltage Vout and the temperature characteristic of the zero point potential.

【0014】[0014]

【発明の実施の形態】BEST MODE FOR CARRYING OUT THE INVENTION

(実施例1)図1は本発明の第1の実施例としての回路
構成を示す。同図においてRG1〜RG4はシリコンダ
イヤフラム上に拡散処理により分散配置して作られた半
導体歪みゲージであり、ホィートストンブリッジの形に
構成されている。ここでVccはその駆動電圧、Gnd
は接地電位である。シリコンダイヤフラムが加圧により
変形すると歪みゲージブリッジの電圧検出側の接続点G
1,G2間に差動出力電圧Vgが発生する。
(Embodiment 1) FIG. 1 shows a circuit configuration as a first embodiment of the present invention. In the figure, reference numerals RG1 to RG4 denote semiconductor strain gauges which are dispersed and arranged on a silicon diaphragm by a diffusion process, and are configured in the form of a Wheatstone bridge. Here, Vcc is the drive voltage, Gnd
Is the ground potential. When the silicon diaphragm is deformed by pressure, the connection point G on the voltage detection side of the strain gauge bridge
A differential output voltage Vg is generated between 1 and G2.

【0015】RM1,RM2,RM3は抵抗回路網であ
る。抵抗回路網RM1の入力端子I1には歪みゲージブ
リッジ出力の片側の電位Vg- を演算増幅器OP2から
なるバッファ回路を介してインピーダンス変換した電位
が入力され、抵抗回路網RM2の入力端子I2には電源
電圧Vccが入力され、また抵抗回路網RM3の入力端
子I3には接地電位Gndが入力される。
RM1, RM2 and RM3 are resistance networks. The input terminal I1 distortion on one side of the potential of the gauge bridge output Vg of the resistor network RM1 - and impedance conversion via a buffer circuit composed of the operational amplifier OP2 potential is input, the power supply to the input terminal I2 of the resistor network RM2 Voltage Vcc is input, and ground potential Gnd is input to input terminal I3 of resistance network RM3.

【0016】他方、各抵抗回路網RM1〜RM3の出力
端子O1〜O3は全て演算増幅器OP1の反転入力端子
に接続され、この演算増幅器OP1の反転入力端子と出
力端子Voutとの間には帰還抵抗Rfが接続される。
歪みゲージブリッジ出力のもう片側の電位Vg+ は、抵
抗Ri1を介して演算増幅器OP1の非反転入力端子に
入力されるほか、抵抗Ri2を介してバッファ回路を構
成する演算増幅器OP3の非反転入力端子にも入力され
る。
On the other hand, the output terminals O1 to O3 of each of the resistor networks RM1 to RM3 are all connected to the inverting input terminal of the operational amplifier OP1, and a feedback resistor is provided between the inverting input terminal of the operational amplifier OP1 and the output terminal Vout. Rf is connected.
The potential Vg + on the other side of the output of the strain gauge bridge is input to the non-inverting input terminal of the operational amplifier OP1 via the resistor Ri1, and the non-inverting input terminal of the operational amplifier OP3 forming a buffer circuit via the resistor Ri2. Is also entered.

【0017】A1,A2,A3は夫々抵抗回路網RM
1,RM2,RM3の電流バイパス用端子であり、全て
このバッファ回路を構成する演算増幅器OP3の出力端
子に接続される。以上の構成において、抵抗回路網RM
1〜RM3及び図1の回路全体の動作について説明す
る。
A1, A2 and A3 are respectively a resistance network RM.
1, RM2 and RM3 are current bypass terminals, all of which are connected to the output terminal of the operational amplifier OP3 constituting this buffer circuit. In the above configuration, the resistance network RM
1 to RM3 and the operation of the entire circuit of FIG. 1 will be described.

【0018】図2は抵抗回路網RM1とその周辺部を示
す回路図である。同図に示すように抵抗回路網RM1
は、入力端子I1と出力端子O1とを直接結ぶ始端抵抗
Ra0と、入力端子I1と電流バイパス用端子A1との
間に入力端子I1側から順に、この例では5段直列に接
続された単位直列抵抗Ra1,Ra2,・・・Ra4及
び終端直列抵抗Ra5からなる直列抵抗回路と、この各
直列抵抗Ra1,Ra2,・・・Ra5の入力端子I1
側の端子に夫々一端が接続された桁別調整抵抗ra1,
ra2,・・・ra5と、この各桁別調整抵抗ra1,
ra2,・・・ra5の他端を夫々出力端子O1側又は
電流バイパス用端子A1の何れかに切替えるように予め
設定されるスイッチSa1,Sa2,・・・Sa5とか
らなる。
FIG. 2 is a circuit diagram showing the resistance network RM1 and its peripheral portion. As shown in FIG.
Is a unit series resistor connected in series in the example from the input terminal I1 side to the start terminal resistor Ra0 directly connecting the input terminal I1 and the output terminal O1, and the input terminal I1 between the input terminal I1 and the current bypass terminal A1. .., Ra4 and a terminating series resistor Ra5, and an input terminal I1 of each of the series resistors Ra1, Ra2,.
Digit-adjustment resistors ra1, one ends of which are connected to the
.., ra5, and the digit-by-digit adjustment resistors ra1,
.., and Sa5. The switches Sa1, Sa2,..., Sa5 are set in advance so that the other ends of the ra2,... ra5 are respectively switched to the output terminal O1 side or the current bypass terminal A1.

【0019】この図2の回路で前述のように歪みゲージ
ブリッジ出力の+側電位Vg+ が、抵抗Ri1を介して
演算増幅器OP1の非反転入力端子に、また抵抗Ri2
を介して演算増幅器OP3の非反転入力端子に夫々入力
される。ここで抵抗Ri1,Ri2は演算増幅器OP
1,OP3の入力インピーダンスに比較して充分小さい
ものとし、またOP1,OP3のオフセット電圧,オフ
セット電流は無視できるものとすると、抵抗回路網RM
1の出力端子O1と電流バイパス用端子A1の電位はい
ずれもVg+ となる。
As described above, in the circuit of FIG. 2, the positive potential Vg + of the strain gauge bridge output is supplied to the non-inverting input terminal of the operational amplifier OP1 via the resistor Ri1 and to the resistor Ri2.
Through the non-inverting input terminal of the operational amplifier OP3. Here, the resistors Ri1 and Ri2 are connected to the operational amplifier OP
If the input impedance of OP1 and OP3 is sufficiently small and the offset voltage and offset current of OP1 and OP3 are negligible, the resistance network RM
The potentials of the output terminal O1 and the current bypass terminal A1 are both Vg + .

【0020】従ってスイッチSa1〜Sa5が端子O1
側に導通した場合と、端子A1側に導通した場合の、何
れも各桁別調整抵抗ra1〜ra5のスイッチSa1〜
Sa5側の電位は変わらず、この各桁別調整抵抗ra1
〜ra5を流れる電流は変化しない。ここで各単位直列
抵抗Ra1〜Ra4の抵抗値がρ1 、また最終段の終端
直列抵抗Ra5及び各桁別調整抵抗ra1〜ra5の抵
抗値が2ρ1 になるようにすると、この回路では次式
(1)が成り立つ。
Therefore, the switches Sa1 to Sa5 are connected to the terminal O1.
The switch Sa1 of each digit-adjustment resistor ra1 to ra5 in the case of conduction to the terminal A1 and the case of conduction to the terminal A1.
The potential on the Sa5 side does not change, and this digit-by-digit adjustment resistor ra1
The current flowing through ra5 does not change. Following formula where one resistance ρ of the unit series resistance Ra1~Ra4, also the resistance of the terminating series resistor Ra5 and each digit by adjusting the resistance ra1~ra5 the final stage is set to be in 2.rho 1, in this circuit (1) holds.

【0021】[0021]

【数1】 i5=i5’=i4’/2 i4=i4’=i3’/2 i3=i3’=i2’/2 i2=i2’=i1’/2 i1=i1’ ・・・(1) 但し i1’〜i5’:各直列抵抗Ra1〜Ra5の電
流 i1〜i5 :各桁別調整抵抗ra1〜ra5の電流 また始端抵抗Ra0は前述の通り、スイッチを介さず直
接に端子I1とO1間に接続されており、この電流をi
0とする。
I1 = i5 ′ = i4 ′ / 2 i4 = i4 ′ = i3 ′ / 2 i3 = i3 ′ = i2 ′ / 2 i2 = i2 ′ = i1 ′ / 2 i1 = i1 ′ (1) However, i1 'to i5': current of each series resistor Ra1 to Ra5 i1 to i5: current of each digit adjusting resistor ra1 to ra5 As described above, the starting resistor Ra0 is directly connected between the terminals I1 and O1 without using a switch as described above. Connected, and this current is
Set to 0.

【0022】従って出力端子O1を流れる抵抗回路網R
M1の電流iaは次式(2)で表される。
Accordingly, the resistance network R flowing through the output terminal O1
The current ia of M1 is represented by the following equation (2).

【0023】[0023]

【数2】 ia=i0+i1+i2+i3+i4+i5 =i0+i1× 5Σx=1 X ・2-(x-1) ・・(2) =(Vg- −Vg+ )/Ra0 +〔(Vg- −Vg+ )/2ρ1 〕× 5Σx=1 X ・2-(x-1) ・・(3) ここでAX (x=1〜5)は、パラメータxによりスイ
ッチSa1〜Sa5を一般的に表したSax(x=1〜
5)が端子O1側のときAX =1、端子A1側のときA
X =0である。
[Number 2] ia = i0 + i1 + i2 + i3 + i4 + i5 = i0 + i1 × 5 Σ x = 1 A X · 2 - (x-1) ·· (2) = (Vg - -Vg +) / Ra0 + [(Vg - -Vg +) / 2.rho 1] × 5 Σ x = 1 a X · 2 - (x-1) ·· (3) where a X (x = 1~5) were generally represents a switch Sa1~Sa5 the parameter x Sax (x = 1 to
5) When the terminal O1 side A X = 1, when the terminal A1 side A
X = 0.

【0024】式(3)の第1項はスイッチSa1〜Sa
5の選択切替えとは無関係な一定電流であり、第2項は
スイッチSa1〜Sa5の接続選択により次式(4)の
範囲で変化させることが可能である。
The first term of the equation (3) is the switches Sa1 to Sa
5 is a constant current unrelated to the selection switching, and the second term can be changed in the range of the following equation (4) by selecting the connection of the switches Sa1 to Sa5.

【0025】[0025]

【数3】 0<〔(Vg- −Vg+ )/2ρ1 〕× 5Σx=1 X ・2-(x-1) <(31/32)・(Vg- −Vg+ )/ρ1 ・・・(4) この電流変化の最小単位は次式(5)で示される。Equation 3] 0 <[(Vg - -Vg +) / 2ρ 1 ] × 5 Σ x = 1 A X · 2 - (x-1) <(31/32) · (Vg - -Vg +) / ρ 1 ... (4) The minimum unit of this current change is expressed by the following equation (5).

【0026】[0026]

【数4】 (1/32)・(Vg- −Vg+ )/ρ1 =(1/25 )・(Vg- −Vg+ )/ρ1 ・・・(5) 即ちスイッチが5つで2-5の分解能の調整が可能であ
る。同様に抵抗回路網RM2の出力端子O2を流れる電
流ibは次式(6)で表される。なお抵抗回路網RM2
の構成はこの例では抵抗回路網RM1の構成と同様で、
構成手段及び抵抗値,印加電圧の一部の符号(記号)の
みが異なる。
(1/32) · (Vg −Vg + ) / ρ 1 = (1/2 5 ) · (Vg −Vg + ) / ρ 1 (5) That is, with five switches 2-5 resolution adjustment is possible. Similarly, the current ib flowing through the output terminal O2 of the resistance network RM2 is expressed by the following equation (6). Note that the resistance network RM2
Is similar to the configuration of the resistance network RM1 in this example.
Only the constituent means, the resistance value, and some of the signs (symbols) of the applied voltage are different.

【0027】即ち抵抗回路網RM2では抵抗回路網RM
1における入力端子電圧Vg- がVccに、始端抵抗R
a0がRb0に、単位直列抵抗Ra1〜Ra4がRb1
〜Rb4に、終端直列抵抗Ra5がRb5に、桁別調整
抵抗ra1〜ra5がrb1〜rb5に、抵抗値ρ1
ρ2 に、スイッチSa1〜Sa5がSb1〜Sb5に、
夫々置換わる。
That is, in the resistance network RM2, the resistance network RM
Input terminal voltage Vg at 1 - to the Vcc, starting resistor R
a0 is Rb0 and unit series resistances Ra1 to Ra4 are Rb1.
The ~Rb4, the termination series resistor Ra5 is Rb5, digits by adjusting resistor ra1~ra5 is Rb1~rb5, the resistance value [rho 1 is [rho 2, the switch Sa1~Sa5 is SB1 to SB5,
Replace each one.

【0028】[0028]

【数5】 ib=(Vcc−Vg+ )/Rb0 +〔(Vcc−Vg+ )/2ρ2 〕× 5Σy=1 y ・2-(y-1) ・・(6) ここでBy (y=1〜5)は、パラメータyによりスイ
ッチSb1〜Sb5を一般的に表したスイッチSby
(y=1〜5)が端子O2側のときBy =1、端子A2
側のときBy =0である。
Equation 5] ib = (Vcc-Vg +) / Rb0 + [(Vcc-Vg +) / 2ρ 2 ] × 5 Σ y = 1 B y · 2 - (y-1) ·· (6) where B y (y = 1 to 5) is a switch Sby that generally represents the switches Sb1 to Sb5 by the parameter y.
When (y = 1 to 5) is on the terminal O2 side, B y = 1 and the terminal A2
On the other hand, B y = 0.

【0029】同様に抵抗回路網RM3の出力端子O3を
流れる電流icは次式(7)で表される。なお抵抗回路
網RM3の構成はこの例では抵抗回路網RM1の構成と
同様で、構成手段及び抵抗値の符号(記号),印加電圧
の一部のみが異なる。即ち抵抗回路網RM3では抵抗回
路網RM1における入力端子電圧Vg- が0に、始端抵
抗Ra0がRc0に、単位直列抵抗Ra1〜Ra4がR
c1〜Rc4に、終端直列抵抗Ra5がRc5に、桁別
調整抵抗ra1〜ra5がrc1〜rc5に、抵抗値ρ
1 がρ3 に、スイッチSa1〜Sa5がSc1〜Sc5
に、夫々置換わる。
Similarly, the current ic flowing through the output terminal O3 of the resistance network RM3 is expressed by the following equation (7). Note that the configuration of the resistance network RM3 is the same as the configuration of the resistance network RM1 in this example, and only the configuration means, the sign (symbol) of the resistance value, and a part of the applied voltage are different. That input terminal voltage Vg of the resistor network RM3 the resistor network RM1 - to 0, the starting resistor Ra0 is Rc0, the unit series resistance Ra1~Ra4 is R
c1 to Rc4, the termination series resistor Ra5 to Rc5, the digit-by-digit adjustment resistors ra1 to ra5 to rc1 to rc5, and the resistance value ρ
To 1 ρ 3, switch Sa1~Sa5 is Sc1~Sc5
, Respectively.

【0030】[0030]

【数6】 ic=(−1)×Vg+ /Rc0 +〔(−1)×Vg+ /2ρ3 〕× 5Σz=1 z ・2-(z-1) ・・・(7) ここでCz (z=1〜5)は、パラメータzによりスイ
ッチSc1〜Sc5を一般的に表したスイッチScz
(z=1〜5)が端子O3側のときCz =1、端子A3
側のときCz =0である。
[6] ic = (- 1) × Vg + / Rc0 + [(- 1) × Vg + / 2ρ 3 ] × 5 Σ z = 1 C z · 2 - (z-1) ··· (7) Here, C z (z = 1 to 5) is a switch Scz that generally represents the switches Sc1 to Sc5 by the parameter z.
When (z = 1 to 5) is on the terminal O3 side, C z = 1, terminal A3
On the side, C z = 0.

【0031】ところで演算増幅器OP1の出力電圧はこ
の半導体圧力変換器の出力電圧Voutであり、次式
(8)で表される。
The output voltage of the operational amplifier OP1 is the output voltage Vout of the semiconductor pressure transducer, and is represented by the following equation (8).

【0032】[0032]

【数7】 Vout =Vg+ −(ia+ib+ic)×Rf =Vg+ +(Vg+ −Vg- ) ×〔(Rf/Ra0)+(Rf/2ρ1 )× 5Σx=1 X ・2-(x-1)〕 −(Vcc−Vg+ ) ×〔(Rf/Rb0)+(Rf/2ρ2 )× 5Σy=1 y ・2-(y-1)〕 +Vg+ ×〔(Rf/Rc0)+(Rf/2ρ3 )× 5Σz=1 z ・2-(z-1)〕 ・・・(8) 上式で(Vg+ −Vg- )は歪みゲージブリッジの差動
出力Vgである。また簡単のため歪みゲージブリッジの
片側出力Vg+ が圧力ゼロのときVcc/2であり、ま
た加圧によるVg+ の変化がVcc/2に比較して充分
小さいと仮定した場合、式(8)は以下の式(9)のよ
うに近似できる。
Equation 7] Vout = Vg + - (ia + ib + ic) × Rf = Vg + + (Vg + -Vg -) × [(Rf / Ra0) + (Rf / 2ρ 1) × 5 Σ x = 1 A X · 2 - (x-1)] - (Vcc-Vg +) × [(Rf / Rb0) + (Rf / 2ρ 2) × 5 Σ y = 1 B y · 2 - (y-1) ] + Vg + × [(Rf / Rc0) + (Rf / 2ρ 3) × 5 Σ z = 1 C z · 2 - (z-1) ] (8) where (Vg + -Vg -) is a strain gauge bridge differential Output Vg. For the sake of simplicity, assuming that one-side output Vg + of the strain gauge bridge is Vcc / 2 when the pressure is zero, and that the change in Vg + due to pressurization is sufficiently small compared to Vcc / 2, equation (8) Can be approximated as in the following equation (9).

【0033】[0033]

【数8】 Vout ≒Vg×Rf〔(1/Ra0)+(1/2ρ1 )× 5Σx=1 X ・2-(x-1)〕 +(Vcc/2)×Rf ×〔−(1/Rb0)−(1/2ρ2 )× 5Σy=1 y ・2-(y-1) +(1/Rc0)+(1/2ρ3 )× 5Σz=1 z ・2-(z-1)〕 +(Vcc/2) ・・・(9) この式(9)の右辺第1項は圧力変換器出力電圧Vou
t中の圧力信号電圧成分であり、スイッチSa1〜Sa
5の接続を選択することにより歪みゲージブリッジの差
動出力Vgの係数値を、従ってこの圧力変換器の感度を
変化することが可能である。また式(9)の右辺第2項
はオフセット電圧成分であり、スイッチSb1〜Sb5
及びSc1〜Sc5の接続を選択することによりこのオ
フセット成分の値を、従って出力電圧Voutの零点電
位を正負両方向に変化させることができる。
Vout {Vg × Rf [(1 / Ra0) + (1 / 2ρ 1 ) × 5 } x = 1 A X −2− (x−1) ] + (Vcc / 2) × Rf × [− (1 / Rb0) - (1 / 2ρ 2) × 5 Σ y = 1 B y · 2 - (y-1) + (1 / Rc0) + (1 / 2ρ 3) × 5 Σ z = 1 C z · 2- (z-1) ] + (Vcc / 2) (9) The first term on the right side of the equation (9) is the pressure transducer output voltage Vou.
t is the pressure signal voltage component during t, and the switches Sa1 to Sa
By selecting the connection of 5, it is possible to change the coefficient value of the differential output Vg of the strain gauge bridge and thus the sensitivity of this pressure transducer. The second term on the right side of the equation (9) is an offset voltage component, and the switches Sb1 to Sb5
And the connection of Sc1 to Sc5, it is possible to change the value of this offset component, that is, the zero-point potential of the output voltage Vout in both positive and negative directions.

【0034】スイッチSa1〜Sa5,Sb1〜Sb
5,Sc1〜Sc5はアナログスイッチや電流スイッチ
等からなり、トランジスタを用いて集積化可能である。
そしてこのスイッチはこの圧力変換器の外部からのシリ
アル信号,BCD信号などを圧力変換器内のデコーダに
よりパラレルのバイナリ信号に変換した駆動信号で駆動
される。
Switches Sa1 to Sa5, Sb1 to Sb
5, Sc1 to Sc5 are composed of analog switches, current switches, and the like, and can be integrated using transistors.
The switch is driven by a drive signal obtained by converting a serial signal, a BCD signal or the like from outside the pressure transducer into a parallel binary signal by a decoder in the pressure transducer.

【0035】また上記スイッチの接続選択による、従来
の抵抗のトリミングに相当する機能を持たせるために、
これらのスイッチの駆動状態はEPROM,E2 PRO
M,ツエナーザップ,ヒューズ(アンチヒューズを含
む)等を用いて電源オフの状態でも記憶されるような回
路構成にする。以上の圧力変換器の回路全体は、抵抗と
して拡散抵抗や薄膜抵抗を用いることにより、同一もし
くは複数のチップ上に集積化することが可能である。ま
た当然、厚膜や薄膜の抵抗基板を含むハイブリッドIC
としても実現できる。
In order to provide a function equivalent to the conventional trimming of a resistor by selecting the connection of the switch,
The driving states of these switches are EPROM, E 2 PRO
The circuit configuration is such that data is stored even when the power is off by using an M, a zener zap, a fuse (including an antifuse), and the like. The entire circuit of the above pressure transducer can be integrated on the same or a plurality of chips by using a diffusion resistor or a thin film resistor as a resistor. Of course, hybrid ICs including thick or thin resistive substrates
It can also be realized as

【0036】(実施例2)図3は本発明の第2の実施例
としての回路構成を示す。同図においては図1に対し温
度補償用の抵抗回路網RM4,RM5が夫々抵抗回路網
RM2,RM3に並設され、演算増幅器OP1の帰還抵
抗が正の大きな温度依存性を持った抵抗Rftに置換え
られている。
(Embodiment 2) FIG. 3 shows a circuit configuration as a second embodiment of the present invention. In this figure, temperature-compensating resistance networks RM4 and RM5 are provided in parallel with the resistance networks RM2 and RM3, respectively, as compared with FIG. 1, and the feedback resistance of the operational amplifier OP1 is replaced by a resistance Rft having a large positive temperature dependency. Has been replaced.

【0037】ここで抵抗回路網RM4は、その入力端子
I4と電流バイパス用端子A4の間に入力端子I4側か
ら順に設けられた温度依存性の大きな、例えば拡散抵抗
等からなる始端直列抵抗Rdt並びに、この例では5段
直列の単位直列抵抗Rd1〜Rd4及び終端直列抵抗R
d5からなる抵抗直列回路と、この各直列抵抗Rd1〜
Rd5の入力端子I4側の端子に夫々一端が接続された
桁別調整抵抗rd1〜rd5と、この各桁別調整抵抗r
d1〜rd5の他端を夫々出力端子O4側又は電流バイ
パス用端子A4の何れかに切替えるように予め設定され
るスイッチSd1〜Sd5とからなる。また各単位直列
抵抗Rd1〜Rd4の抵抗値をρ4 、また最終段の終端
直列抵抗Rd5及び各桁別調整抵抗rd1〜rd5の抵
抗値を2ρ4 とする。
Here, the resistor network RM4 is formed of an input terminal I4 and a current bypass terminal A4 in order from the input terminal I4 side. In this example, the unit series resistances Rd1 to Rd4 and the terminal series resistance R
d5, and each series resistor Rd1.
Digit-by-digit adjustment resistors rd1 to rd5 each having one end connected to the input terminal I4 side terminal of Rd5;
Switches Sd1 to Sd5 are set in advance so that the other ends of d1 to rd5 are respectively switched to the output terminal O4 side or the current bypass terminal A4. Further, the resistance value of each unit series resistor Rd1 to Rd4 is ρ 4 , and the resistance value of the terminal serial resistor Rd5 in the final stage and the adjustment resistor rd1 to rd5 for each digit is 2ρ 4 .

【0038】同様に抵抗回路網RM5は、その入力端子
I5と電流バイパス用端子A5の間に入力端子I5側か
ら順に設けられた温度依存性の大きな、例えば拡散抵抗
等からなる始端直列抵抗Ret並びに、この例では5段
直列の単位直列抵抗Re1〜Re4及び終端直列抵抗R
e5からなる直列抵抗回路と、この各直列抵抗Re1〜
Re5の入力端子I5側の端子に夫々一端が接続された
桁別調整抵抗re1〜re5と、この各桁別調整抵抗r
e1〜re5の他端を夫々出力端子O5側又は電流バイ
パス用端子A5の何れかに切替えるように予め設定され
るスイッチSe1〜Se5とからなる。また各単位直列
抵抗Re1〜Re4の抵抗値をρ5 、また最終段の終端
直列抵抗Rq5及び各桁別調整抵抗re1〜re5の抵
抗値を2ρ5 とする。
Similarly, the resistor network RM5 includes a start-point series resistor Ret composed of, for example, a diffused resistor, which has a large temperature dependency and is provided between the input terminal I5 and the current bypass terminal A5 in order from the input terminal I5 side. In this example, the unit series resistances Re1 to Re4 and the terminal series resistance R
e5 and the series resistors Re1 to
Digit-by-digit adjustment resistors re1 to re5 each having one end connected to a terminal on the input terminal I5 side of Re5;
Switches Se1 to Se5 are set in advance so that the other ends of e1 to re5 are respectively switched to the output terminal O5 side or the current bypass terminal A5. The resistance value [rho 5 of the unit series resistance Re1~Re4, also the resistance of the terminating series resistor Rq5 and each digit by adjusting the resistance re1~re5 the final stage and 2.rho 5.

【0039】つぎに図3の回路動作を説明する。桁別調
整抵抗rd1を流れる電流id1は次式(10)で表さ
れる。
Next, the operation of the circuit shown in FIG. 3 will be described. The current id1 flowing through the digit-by-digit adjustment resistor rd1 is expressed by the following equation (10).

【0040】[0040]

【数9】 id1=(Vcc−Vg+ )/2(Rdt+ρ4 ) ・・・(10) 従って抵抗回路網RM4の出力端子O4を流れる電流i
dは次式(11)で表される。
Equation 9] id1 = (Vcc-Vg +) / 2 (Rdt + ρ 4) ··· (10) Thus the current flowing through the output terminal O4 of the resistor network RM4 i
d is represented by the following equation (11).

【0041】[0041]

【数10】 id =〔(Vcc−Vg+ )/2(Rdt+ρ4 )〕× 5Σm=1 m ・2-(m-1) ・・・(11) ここでDm (m=1〜5)は、パラメータmによりスイ
ッチSd1〜Sd5を一般的に表したスイッチSdm
(m=1〜5)が端子O4側のときDm =1、端子A4
側のときDm =0である。
Equation 10] id = [(Vcc-Vg +) / 2 (Rdt + ρ 4) ] × 5 Σ m = 1 D m · 2 - (m-1) ··· (11) where D m (m = 1 To 5) are switches Sdm that generally represent the switches Sd1 to Sd5 by the parameter m.
When (m = 1 to 5) is on the terminal O4 side, D m = 1 and the terminal A4
D m = 0 at the side.

【0042】同様に抵抗回路網RM5の出力端子O5を
流れる電流ieは次式(12)で表される。
Similarly, the current ie flowing through the output terminal O5 of the resistance network RM5 is expressed by the following equation (12).

【0043】[0043]

【数11】 ie=(−1)×〔Vg+ /2(Ret+ρ5 )〕× 5Σn=1 n ・2-(n-1) ・・・(12) ここでEn (n=1〜5)は、パラメータnによりスイ
ッチSe1〜Se5を一般的に表したスイッチSdn
(n=1〜5)が端子O5側のときEn =1、端子A5
側のときEn =0である。
Equation 11] ie = (- 1) × [Vg + / 2 (Ret + ρ 5) ] × 5 Σ n = 1 E n · 2 - (n-1) ··· (12) where E n (n = 1-5) are switches Sdn that generally represent the switches Se1-Se5 by the parameter n.
(N = 1 to 5) is E n = 1 when the terminal O5 side terminal A5
On the side, En = 0.

【0044】ここで実施例1と同様な近似を用い、さら
に抵抗回路網RM1〜RM3による圧力信号,零点電位
を付加して、この半導体圧力変換器の出力電圧Vout
を求めると式(13)のように表される。
Here, using the same approximation as in the first embodiment, and further adding the pressure signal and the zero point potential by the resistance network RM1 to RM3, the output voltage Vout of this semiconductor pressure converter is obtained.
Is obtained as shown in Expression (13).

【0045】[0045]

【数12】 Vout =Vg+ −(ia+ib+ic+id+ie)×Rft ≒Vg×Rft〔(1/Ra0)+(1/2ρ1 )× 5Σx=1 X ・2-(x-1)〕 +(Vcc/2)×Rft ×〔−(1/Rb0)−(1/2ρ2 )× 5Σy=1 y ・2-(y-1) +(1/Rc0)+(1/2ρ3 )× 5Σz=1 z ・2-(z-1)〕 +(Vcc/2)×(Rft/2) ×〔−〔1/(Rdt+ρ4 )〕× 5Σm=1 m ・2-(m-1) +〔1/(Ret+ρ5 )〕× 5Σn=1 n ・2-(n-1)〕 +(Vcc/2) ・・・(13) この式(13)の右辺第1項は圧力感度成分、第2項,
第3項はオフセット成分である。通常、半導体歪みゲー
ジの出力電圧Vgは負の温度依存性を持つが、それを帰
還抵抗Rftの正の温度依存性により補償して感度温度
特性の補償を行う。
Equation 12] Vout = Vg + - (ia + ib + ic + id + ie) × Rft ≒ Vg × Rft [(1 / Ra0) + (1 / 2ρ 1) × 5 Σ x = 1 A X · 2 - (x-1) ] + ( vcc / 2) × Rft × [- (1 / Rb0) - ( 1 / 2ρ 2) × 5 Σ y = 1 B y · 2 - (y-1) + (1 / Rc0) + (1 / 2ρ 3) × 5 Σ z = 1 C z · 2- (z-1) ] + (Vcc / 2) × (Rft / 2) × [-[1 / (Rdt + ρ 4 )] × 5 Σ m = 1 D m · 2 - the (n-1)] + (Vcc / 2) ··· ( 13) this equation (13) - (m-1 ) + [1 / (Ret + ρ 5)] × 5 Σ n = 1 E n · 2 The first term on the right side is the pressure sensitivity component, the second term,
The third term is an offset component. Normally, the output voltage Vg of the semiconductor strain gauge has a negative temperature dependency, which is compensated for by the positive temperature dependency of the feedback resistor Rft to compensate for the sensitivity temperature characteristic.

【0046】また圧力ゼロの時の圧力変換器出力電圧、
つまり零点電位の温度特性については、式(13)の右
辺第1項(圧力ゼロの時、この第1項の半導体歪みゲー
ジ出力電圧Vgは必ずしも0ではない)及び第2項の温
度特性のバラツキに応じて、抵抗回路網RM4,RM5
のスイッチSd1〜Sd5,Se1〜Se5の接続を選
択し、式(13)の右辺第3項のDm (D1〜D5),
n (E1〜E5)の値を選ぶことにより、右辺第3
項の温度依存性が右辺第1項,第2項の温度依存性を打
ち消し合って温度依存性を補償することが可能である。
このようにして本実施例2により感度及び零点電位の調
整機能のみならず、感度及び零点電位の温度特性の補償
機能を持つ半導体圧力変換器を実現することができる。
The output voltage of the pressure transducer when the pressure is zero,
That is, with respect to the temperature characteristic of the zero-point potential, the first term on the right side of the equation (13) (when the pressure is zero, the semiconductor strain gauge output voltage Vg of the first term is not always 0) and the temperature characteristic of the second term vary. RM4, RM5
Of the switches Sd1 to Sd5, Se1 to Se5, and the third term D m (D1 to D5),
By choosing the values of E n (E1~E5), the right side third
It is possible to compensate for the temperature dependency of the term by canceling out the temperature dependency of the first and second terms on the right side.
As described above, according to the second embodiment, it is possible to realize a semiconductor pressure transducer having not only the function of adjusting the sensitivity and the zero-point potential but also the function of compensating the temperature characteristics of the sensitivity and the zero-point potential.

【0047】なお感度温度特性の補償を行うには、上述
の方法以外に図1の抵抗回路網RM1の入力端子I1と
前記直列抵抗回路との間に温度依存性の大きな抵抗を挿
入する方法を用いることもできる。また以上の方法とは
別に図1の抵抗回路網RM1〜RM3の始端抵抗Ra0
〜Rc0を温度依存性の大きな抵抗と組合わせて構成す
ることにより、感度及び零点電位の温度特性の補償を行
うことができる。
In order to compensate the sensitivity temperature characteristic, a method of inserting a resistor having a large temperature dependency between the input terminal I1 of the resistance network RM1 and the series resistance circuit in addition to the above-described method is used. It can also be used. Apart from the above method, the starting resistor Ra0 of the resistor network RM1 to RM3 in FIG.
By configuring .about.Rc0 in combination with a resistor having a large temperature dependency, it is possible to compensate for the temperature characteristics of sensitivity and zero potential.

【0048】[0048]

【発明の効果】本発明によれば少なくとも複数の単位直
列抵抗(Ra1〜Ra4など)及び終端直列抵抗(Ra
5など)からなる抵抗直列回路上の抵抗接続点から引き
出され、夫々他端がスイッチ(Sa1〜Sa5など)に
より選択される複数の桁別調整抵抗(ra1〜ra5な
ど)を持つ1又は複数の抵抗回路網(RM1〜RM5な
ど)を、歪みゲージブリッジの出力信号Vgの増幅,調
整を行う信号処理回路内に設け、 外部から与えるデジ
タル信号により桁別調整抵抗の接続選択を行うことで、
抵抗回路網の出力電流を2-n(但しnはスイッチの個
数)の分解能で可変設定し、半導体圧力変換器出力電圧
の感度や零点電位の調整ができるようにしたので、従来
の抵抗体トリミングを行う方式と比較して以下のような
効果を得ることができる。 (1)回路調整がデジタル信号で瞬時に行えるため、調
整のためのチップや回路基板の位置合わせが不要であ
り、調整の所要時間を大幅に短縮することができる。 (2)チップや回路基板を実装した後の状態でも、パッ
ケージの入力端子に調整用のデジタル信号を入力するこ
とで調整ができるため、チップや回路基板が汚れたり傷
付いたりする心配がない。 (3)抵抗回路網からの調整用の電流を加算し電圧に変
換する演算増幅器OP1を含んだ回路は歪みゲージブリ
ッジ出力の圧力信号の増幅及びインピーダンス変換の機
能も兼ね備えており、その結果、少ない素子数でデジタ
ル信号による調整が可能な圧力変換器を実現することが
できる。
According to the present invention, at least a plurality of unit series resistors (Ra1 to Ra4, etc.) and a terminating series resistor (Ra) are used.
5) having one or more digitized adjusting resistors (ra1 to ra5, etc.) selected from switches at the other end by switches (Sa1 to Sa5, etc.). A resistance network (RM1 to RM5, etc.) is provided in a signal processing circuit for amplifying and adjusting the output signal Vg of the strain gauge bridge, and the connection of the adjustment resistor for each digit is selected by a digital signal supplied from the outside, thereby
Since the output current of the resistor network is variably set at a resolution of 2 -n (where n is the number of switches), the sensitivity of the output voltage of the semiconductor pressure transducer and the zero-point potential can be adjusted. The following effects can be obtained as compared with the method of performing the above. (1) Since the circuit adjustment can be performed instantaneously with a digital signal, it is not necessary to align a chip or a circuit board for the adjustment, and the time required for the adjustment can be greatly reduced. (2) Even after the chip or the circuit board is mounted, the adjustment can be performed by inputting the digital signal for adjustment to the input terminal of the package, so that there is no fear that the chip or the circuit board becomes dirty or damaged. (3) The circuit including the operational amplifier OP1 that adds the current for adjustment from the resistance network and converts it into a voltage also has the functions of amplifying the pressure signal output from the strain gauge bridge and converting the impedance, and as a result, the number is small. A pressure transducer that can be adjusted by a digital signal with the number of elements can be realized.

【0049】また、歪みゲージブリッジの出力信号Vg
の増幅を行う演算増幅器OP1の帰還抵抗を正の大きな
温度依存性を持つ帰還抵抗Rftとしたり、温度依存性
の大きな始端直列抵抗Rdt,Ret等を含み、前記の
ようにスイッチの接続選択で出力電流を調整できる抵抗
回路網RM4,RM5等を用いるようにしたので(請求
項3〜5)、圧力変換器出力電圧の感度温度特性及び零
点電位温度特性の補償を容易に行うことができ、広い温
度範囲で高精度が要求される用途の半導体圧力変換器を
容易に得ることができる。
The output signal Vg of the strain gauge bridge
The feedback resistance of the operational amplifier OP1 for amplifying the input signal includes a feedback resistance Rft having a large positive temperature dependency, a starting series resistance Rdt and Ret having a large temperature dependency, and the like. Since the resistor networks RM4, RM5 and the like that can adjust the current are used (claims 3 to 5), the sensitivity temperature characteristic and the zero-point potential temperature characteristic of the pressure transducer output voltage can be easily compensated, and a wide range can be obtained. A semiconductor pressure transducer for applications requiring high accuracy in a temperature range can be easily obtained.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の第1の実施例としての構成を示す回路
FIG. 1 is a circuit diagram showing a configuration as a first embodiment of the present invention;

【図2】図1の抵抗回路網RM1の説明図FIG. 2 is an explanatory diagram of a resistance network RM1 in FIG. 1;

【図3】本発明の第2の実施例としての構成を示す回路
FIG. 3 is a circuit diagram showing a configuration as a second embodiment of the present invention;

【図4】従来の抵抗体トリミングの説明図FIG. 4 is an explanatory diagram of conventional resistor trimming.

【符号の説明】[Explanation of symbols]

RG1〜RG4 半導体歪みゲージ G1,G2 歪みゲージブリッジの出力端子 Vcc 電源電圧 Vout 半導体圧力変換器の出力電圧 Gnd 接地電位 Vg+ ,Vg- 歪みゲージブリッジの片側出力電位 Vg 歪みゲージブリッジの差動出力電圧 OP1〜OP3 演算増幅器 Rf 帰還抵抗 Rft 正の大きな温度依存性を持つ帰還抵
抗 RM1〜RM5 抵抗回路網 I1〜I5 抵抗回路網の入力端子 O1〜O5 抵抗回路網の出力端子 A1〜A5 抵抗回路網の電流バイパス用端子 Ra0〜Rc0 始端抵抗 Rdt,Ret 温度依存性の大きな抵抗(始端直列
抵抗) Ra1〜Ra4,Rb1〜Rb4,Rc1〜Rc4,R
d1〜Rd4 Re1〜Re5 単位直列抵抗 Ra5,Rb5,Rc5,Rd5,Re5 終端直列
抵抗 ra1〜ra5,rb1〜rb5,rc1〜rc5,r
d1〜rd5 re1〜re5 桁別調整抵抗 Sa1〜Sa5,Sb1〜Sb5,Sc1〜Sc5,S
d1〜Sd5 Se1〜Se5 スイッチ ρ1 ,ρ2 ,ρ3 ,ρ4 ,ρ5 抵抗値
RG1~RG4 semiconductor strain gauges G1, G2 strain gauge bridge output terminal Vcc supply voltage Vout semiconductor pressure transducer output voltage Gnd ground potential Vg +, Vg - strain gauge bridge side output potential Vg strain gauge bridge differential output voltage OP1 to OP3 Operational amplifier Rf Feedback resistor Rft Feedback resistor having a large positive temperature dependency RM1 to RM5 Resistive network I1 to I5 Input terminal of resistive network O1 to O5 Output terminal of resistive network A1 to A5 Current bypass terminals Ra0 to Rc0 Starting end resistors Rdt, Ret Resistances with large temperature dependence (starting end series resistances) Ra1 to Ra4, Rb1 to Rb4, Rc1 to Rc4, R
d1 to Rd4 Re1 to Re5 Unit series resistance Ra5, Rb5, Rc5, Rd5, Re5 Termination series resistance ra1 to ra5, rb1 to rb5, rc1 to rc5, r
d1 to rd5 re1 to re5 Digit-based adjustment resistors Sa1 to Sa5, Sb1 to Sb5, Sc1 to Sc5, S
d1 to Sd5 Se1 to Se5 switches ρ 1 , ρ 2 , ρ 3 , ρ 4 , ρ 5 resistance values

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】シリコンダイヤフラム上に拡散により形成
配置され、所定の電源電圧及び接地電位が夫々所定の端
子に与えられ、複数個からなる歪みゲージと、 ダイヤフラムに加わる圧力に応じて発生した歪みゲージ
の出力電圧に対応する電流をその反転入力端子と出力端
子とを結ぶ帰還抵抗に流して電圧に変換し、この半導体
圧力変換器の出力電圧とする演算増幅器を設けられ、歪
みゲージの出力電圧の増幅,調整を行う信号処理回路と
を、抵抗基板を含み得る同一もしくは複数のシリコンチ
ップ上に備えた半導体圧力変換器において、 前記信号処理回路内に、夫々第1,第2,第3の3つの
回路網端子を持ち、 第1の回路網端子にはこの半導体圧力変換器内に存在又
は発生する固定又は可変の電位であって前記第2又は第
3の回路網端子の入力電位とは異なる所定の1又は複数
の電位の何れかが入力され、 第2の回路網端子は前記演算増幅器の反転入力端子に接
続され、 第3の回路網端子は第2の回路網端子と略同電位で、前
記演算増幅器とは独立した部位に接続されてなる抵抗回
路網であって、 第1の回路網端子と第3の回路網端子との間に、少なく
とも第1の回路網端子側より順に同一抵抗値を有する複
数の単位直列抵抗及び、この単位直列抵抗の倍の抵抗値
を有する終端直列抵抗が1つずつ直列に接続された抵抗
直列回路を持ち、更にこの抵抗直列回路を成す複数の単
位直列抵抗及び終端直列抵抗の夫々の第1の回路網端子
側の端に、1対1に前記単位直列抵抗の倍の抵抗値を有
する桁別調整抵抗の夫々の一方の端が接続され、この各
桁別調整抵抗の他方の端が第2又は第3の回路網端子の
何れかに選択的に接続されるような1又は複数の抵抗回
路網と、 外部からのデジタル信号に応じて前記の各抵抗回路網の
各桁別調整抵抗の選択的な接続を、電源の消失時にもこ
の接続が記憶されるように行う選択接続手段とを設け、 前記演算増幅器の反転入力端子において前記の各抵抗回
路網の第2の回路網端子に選択接続された桁別調整抵抗
から入力された電流が加算され、前記帰還抵抗により電
圧に変換されてこの半導体圧力変換器の前記出力電圧に
重畳されるようにしたことを特徴とする半導体圧力変換
器。
1. A plurality of strain gauges formed and arranged on a silicon diaphragm by diffusion, given a predetermined power supply voltage and a ground potential to respective predetermined terminals, and a strain gauge generated in accordance with a pressure applied to the diaphragm. A current corresponding to the output voltage is supplied to a feedback resistor connecting the inverting input terminal and the output terminal to convert the current into a voltage, and an operational amplifier is provided as an output voltage of the semiconductor pressure transducer. In a semiconductor pressure transducer provided with a signal processing circuit for performing amplification and adjustment on the same or a plurality of silicon chips that can include a resistance substrate, the signal processing circuit includes first, second, and third signals, respectively. A first network terminal having a fixed or variable potential present or occurring in the semiconductor pressure transducer, said second or third network terminal; One of a predetermined potential or a plurality of potentials different from the input potential is input, a second network terminal is connected to an inverting input terminal of the operational amplifier, and a third network terminal is a second network terminal. A resistor network connected at a potential substantially the same as that of the operational amplifier and independent of the operational amplifier, wherein at least a first network is connected between a first network terminal and a third network terminal. A resistor series circuit in which a plurality of unit series resistors having the same resistance value in order from the terminal side and a terminating series resistor having a resistance value twice the unit series resistance are connected in series one by one; Each of the plurality of unit series resistors and the terminating series resistor has, at one end on the first network terminal side, one end of a digit-by-digit adjustment resistor having a resistance value that is twice the unit series resistance in a one-to-one relationship. Is connected, and the other end of each digit adjustment resistor is connected to the second or One or more resistor networks selectively connected to any one of the third network terminals; and selectively adjusting digit-by-digit adjustment resistors of each of the resistor networks in response to an external digital signal. Selective connection means for making a proper connection even when the power supply is lost, and selectively connecting to the second network terminal of each of the resistor networks at the inverting input terminal of the operational amplifier. The semiconductor pressure transducer is characterized in that currents input from the digitized adjustment resistors are added, converted into a voltage by the feedback resistor, and superimposed on the output voltage of the semiconductor pressure transducer.
【請求項2】請求項1に記載の半導体圧力変換器におい
て、 前記第1の回路網端子に入力する電位を、前記圧力に応
じて発生した歪みゲージの出力電位又はこの出力電位を
信号処理した該出力電位に対応する電位、前記電源電
圧、前記接地電位の何れかとし、この半導体圧力変換器
の出力電圧の歪みゲージの圧力信号に対する感度又は
(及び)零点電位を前記外部からのデジタル信号に応じ
て調整し得るようにしたことを特徴とする半導体圧力変
換器。
2. The semiconductor pressure transducer according to claim 1, wherein a potential input to said first network terminal is output from a strain gauge generated according to said pressure, or said output potential is subjected to signal processing. Any one of the potential corresponding to the output potential, the power supply voltage, and the ground potential, and the sensitivity of the output voltage of the semiconductor pressure transducer to the pressure signal of the strain gauge or (and) the zero potential is converted to the external digital signal. A semiconductor pressure transducer characterized in that it can be adjusted accordingly.
【請求項3】請求項1又は2に記載の半導体圧力変換器
において、 前記帰還抵抗が正の大きな温度依存性を有する抵抗を含
み、この半導体圧力変換器の前記出力電圧の感度温度特
性を補償し得ることを特徴とする半導体圧力変換器。
3. The semiconductor pressure transducer according to claim 1, wherein the feedback resistor includes a resistor having a large positive temperature dependency, and compensates for the sensitivity temperature characteristic of the output voltage of the semiconductor pressure transducer. Semiconductor pressure transducer.
【請求項4】請求項1ないし3の何れかに記載の半導体
圧力変換器において、前記抵抗回路網のうちの少なくと
も何れか1又は複数の抵抗回路網の第1の回路網端子と
抵抗直列回路との間に夫々直列に温度依存性の大きい始
端直列抵抗が挿入され、この半導体圧力変換器の前記出
力電圧の感度温度特性又は(及び)零点電位の温度特性
を補償し得ることを特徴とする半導体圧力変換器。
4. A semiconductor pressure transducer according to claim 1, wherein a first network terminal of at least one of the resistance networks or a plurality of resistance networks and a resistance series circuit. And a series resistor having a large temperature dependency is inserted in series between them so as to compensate for the sensitivity temperature characteristic of the output voltage and / or the temperature characteristic of the zero point potential of the semiconductor pressure transducer. Semiconductor pressure transducer.
【請求項5】請求項1ないし4の何れかに記載の半導体
圧力変換器において、前記抵抗回路網のうちの少なくと
も何れか1又は複数の抵抗回路網の第1の回路網端子と
第2の回路網端子との間に夫々温度依存性の大きい始端
抵抗が挿入され、この半導体圧力変換器の前記出力電圧
の感度温度特性又は(及び)零点電位の温度特性を補償
し得ることを特徴とする半導体圧力変換器。
5. The semiconductor pressure transducer according to claim 1, wherein a first network terminal of at least one or a plurality of resistance networks of said resistance networks and a second network terminal are connected to each other. A temperature-dependent starting resistor is inserted between the terminal and the network terminal to compensate for the sensitivity temperature characteristic of the output voltage and / or the zero-point potential temperature characteristic of the semiconductor pressure transducer. Semiconductor pressure transducer.
JP15198696A 1996-06-13 1996-06-13 Semiconductor pressure converter Pending JPH102820A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15198696A JPH102820A (en) 1996-06-13 1996-06-13 Semiconductor pressure converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15198696A JPH102820A (en) 1996-06-13 1996-06-13 Semiconductor pressure converter

Publications (1)

Publication Number Publication Date
JPH102820A true JPH102820A (en) 1998-01-06

Family

ID=15530570

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15198696A Pending JPH102820A (en) 1996-06-13 1996-06-13 Semiconductor pressure converter

Country Status (1)

Country Link
JP (1) JPH102820A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7333250B2 (en) 2002-01-31 2008-02-19 Hewlett-Packard Development Company, L.P. Image scanner with a single motor providing two-dimensional movement of photosensors
US7777565B2 (en) 2007-10-15 2010-08-17 Denso Corporation Differential amplification circuit and manufacturing method thereof
CN115808284A (en) * 2023-02-09 2023-03-17 中国空气动力研究与发展中心设备设计与测试技术研究所 Wind tunnel multi-working condition modeling method based on neural network parameter scheduling

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7333250B2 (en) 2002-01-31 2008-02-19 Hewlett-Packard Development Company, L.P. Image scanner with a single motor providing two-dimensional movement of photosensors
US7777565B2 (en) 2007-10-15 2010-08-17 Denso Corporation Differential amplification circuit and manufacturing method thereof
CN115808284A (en) * 2023-02-09 2023-03-17 中国空气动力研究与发展中心设备设计与测试技术研究所 Wind tunnel multi-working condition modeling method based on neural network parameter scheduling

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