JPH1027912A - Structure of electrode buried within layer and formation thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for forming an electrode buried within a substrate of an silicon-on-insulator(SOI) structure or an insulating film while eliminating the need for cutting a silicon thin film of the SOI structure. SOLUTION: A MOS FET 10 having an SOI structure includes a substrate 1, a buried oxide film 12 formed on the substrate 1, a wiring layer 14 buried within the buried oxide film 12, a silicon thin film (SOI layer) 13 on the buried oxide film 12, and a gate electrode 17 and an oxide film 18 formed thereon. Formed in the silicon thin film 13 at both its ends are a source region 15 and a drain region 16. Further provided are electrodes 19 in continuity with the source and drain regions 15 and 16, an island 20 of the silicon thin film formed as a connector between the electrode 22 and wiring layer 14 to be in electrical continuity with the wiring layer 14, and electrode metals 22 electrically connected with the island 20.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an electrode structure of an embedded layer, and more particularly to an electrode structure of an embedded layer embedded in a substrate or an insulating film having an SOI structure and a method of forming the same. The present invention relates to an electrode structure with a small number of steps and a high product yield, particularly an electrode structure of a buried in-layer body which is optimal for a MOSFET having an SOI structure, and a method for forming the same.

[0002]

2. Description of the Related Art An SOI (Silicon On Insulator) structure is formed by forming a thin single crystal layer of silicon on an insulating substrate,
It is a structure obtained by removing an excess portion of the silicon layer while leaving an island for forming an element, and is said to be a structure that facilitates element isolation and can eliminate a parasitic MOS. By the way, S
Since the method of forming the OI structure itself is under development, SOI
A method for extracting an electrode from a substrate having a structure or an embedded layer embedded in an insulating film is also in a development stage and has not yet been established. Therefore, for example, as shown in FIG. 7 (b), except that an example of forming an electrode conducting to a buried body in a layer close to the surface of a silicon thin film through a through hole in an oxide film has been reported. Very few research cases have been conducted.

Here, a conventional example in which an electrode is provided in an embedded body having an SOI structure will be described with reference to FIG. FIG.
(A) is a MOSFET having an SOI structure in which a buried body in a layer, that is, a wiring 14 is buried in a buried oxide film 12.
1 shows a layer structure of the present invention. MOSFE with SOI structure
T70 includes a buried oxide film 12, a wiring 14 buried in the buried oxide film 12, and a silicon thin film (SOI layer) 13 on the buried oxide film 12 on a substrate 11, and further a gate electrode 17 And an oxide film 18. The silicon thin film 13 has a source region 15 and a drain region 16 at both end regions. FIG.
7B shows the wiring 14 and the source region 15 shown in FIG.
Also, an example in which an electrode 19 is provided in the drain region 16 is shown.

[0004]

As shown in FIG. 7B, to form electrodes on source / drain and wiring,
It is necessary to open the contact hole by etching the oxide film 18 and the buried oxide film 12. By the way, in order to form the contact holes for forming the source / drain and wiring electrodes in the same step, it is necessary to use etching conditions in which the etching rate of silicon is lower than the etching rate of the oxide film during the etching process. is necessary. However, with the miniaturization of semiconductor devices,
Because silicon is becoming thinner, for example, 0.18
In the μm rule generation, since the thickness of silicon is 30 nm, it is difficult to sufficiently control the etching only by adjusting the etching conditions. M shown in FIG.
In the example of the OSFET, the depth of the contact hole for forming the electrode of the wiring 14 is deeper than the contact hole for forming the electrode of the source 15 / drain 16, and the source 1
5 / The oxide film 18 on the drain 16
Is thick. Therefore, if the contact holes for the electrodes of the source / drain portion and the electrodes of the wiring are to be simultaneously opened in the oxide film 18, it is difficult to control the etching rate, and as shown in FIG. The contact hole for the electrode of the drain 16 is deepened,
The silicon thin film is excessively shaved, and the thickness of the silicon thin film is reduced.

[0005] When the silicon of the silicon thin film is removed, the resistance of the remaining silicon film increases, and as a result, the parasitic resistance of the source increases and the current driving capability of the MOSFET decreases. It also causes a contact failure. Although the example of the wiring is shown and described as the buried structure, the MOSFE
Even if another element such as a lower electrode of T or a capacitor is embedded, the structure of the extraction electrode connected to the extraction electrode by wiring is the same, so that the other elements also have the same problem as the above-described example.

[0006] In light of the above problems, an object of the present invention is to:
To provide an electrode structure of an embedded layer body and a method of forming the same so as not to cut a silicon thin film having an SOI structure when forming an electrode of the embedded layer embedded in a substrate or an insulating film having an SOI structure. It is.

[0007]

Means for Solving the Problems By the way, when forming an electrode of a buried layer, for example, when forming an electrode on the above-mentioned MOSFET wiring, an electrode forming process has a small number of process steps, and A process with a large process margin is preferable in terms of product quality control and productivity. Therefore, the present inventor has considered that the following conditions should be satisfied in the process of forming the electrode structure of the embedded layer. (1) Elements in an upper silicon thin film, for example, MOSFE
In the case of T, forming the electrode of the buried body of the SOI structure in the same process as the formation of the source / drain electrodes, thereby reducing the overall number of process steps. (2) With the miniaturization of semiconductor devices, the thickness of the upper silicon thin film has become thinner, so that when opening a contact hole for forming an electrode, the amount of over-etching of the insulating film is reduced, and the silicon layer becomes thinner. Try to minimize the amount that is etched. The inventor has considered that in order to achieve (1) and (2), for example, in the case of a MOSFET, the source / drain electrodes and the buried electrode have the same structure including the base.

To achieve the above object, based on the above findings, the electrode structure of the embedded layer according to the present invention has the following features:
S formed by forming a silicon thin film on a substrate via an insulating film
An electrode structure of an in-layer embedded body formed in a substrate or an insulating film having an OI structure, wherein the electrode structure is electrically connected to the embedded body.
In addition, the semiconductor device is provided with a connection portion formed of a silicon thin film formed simultaneously with the silicon thin film having the SOI structure, and an electrode that is electrically connected to the connection portion.

According to the present invention, the connecting portion made of the silicon thin film is an island of the silicon thin film for the electrode formed on the insulating film, and contacts the island with the buried layer.
By forming an electrode on the island with which the contact was made, an electrode of the embedded layer is formed.

The substrate may be made of SiC, SiC,
The substrate may be a substrate made of a compound semiconductor such as GaAs or InP, the insulating film may be SiO ₂ or SiN, and the embedded layer may be a lower electrode of a MOSFET, a passive element including a wiring and a capacitor, or a TFT. Including any of the active elements. Further, instead of the silicon thin film having the SOI structure, the thin film may be a compound semiconductor thin film.

[0011] A method according to the present invention for forming an electrode on a substrate having an SOI structure in which a silicon thin film is formed on a substrate via an insulating film or an in-layer embedded body formed in the insulating film,
A silicon layer, a buried oxide film formed on the silicon layer, and an in-layer buried body formed in the buried oxide film so as to be electrically connected to an electrode region defined in a predetermined region of the silicon layer; And forming a first wafer comprising a poly-Si film formed on the buried oxide film;
With the surface of the poly-Si film of the first wafer as an interface, the first wafer and the second wafer made of silicon are united by a wafer bonding method, and
Sequentially forming a combined wafer comprising a poly-Si film, a buried oxide film, and a silicon layer of a first wafer;
By leaving the silicon thin film constituting the I structure,
Polishing the silicon layer of the wafer to simultaneously form an electrode region of the silicon thin film and a silicon thin film constituting the SOI structure on the buried oxide film; and forming an electrode conducting to the electrode region of the silicon thin film. It is characterized by:

According to the method of the present invention, an electrode region made of a silicon thin film for forming an electrode of an embedded body is formed simultaneously with a silicon thin film having an SOI structure without using an additional process. The embedded electrode can be formed in the same processing step as the drain electrode. Further, since the silicon thin film in the source / drain regions is not subjected to excessive etching, a good electrode can be formed without deteriorating the characteristics of the semiconductor device and without deteriorating the contact characteristics. In the step of forming the first wafer, an element isolation region can be formed by etching a silicon layer to provide a step, and then forming a buried oxide film.

[0013]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. Embodiment 1 This embodiment is an example in which an electrode structure of an embedded layer according to the present invention is applied to a MOSFET having an SOI structure.
FIG. 1 is a schematic sectional view showing the layer structure of the MOSFET of this embodiment. 1 to 6, the same parts and parts as those in FIG. 7 are denoted by the same reference numerals. MOS of this embodiment
In the FET 10, the electrode structure of the wiring 14 is different from the MOSFET shown in FIG. This MOSFE
The electrode structure of the wiring 14 of T10 is formed as a connection portion between the electrode 22 and the wiring 14 and includes an island 20 of a silicon thin film electrically connected to the wiring 14 and an electrode metal 22 electrically connected to the island 20. It is configured. As described below,
The island 20 is formed in the same process as the silicon thin film 13 in the MOSFET portion. According to the conductivity type of the buried layer,
By implanting impurities simultaneously with the formation of the source / drain of the P-MOSFET or N-MOSFET,
0 has a small contact resistance. Island 20
As described later, an oxide film is formed on the substrate 30, an opening is formed in the oxide film, the wiring 14 is formed, and an oxide film is formed thereon, and the contact between the buried wiring 14 and the buried wiring 14 is formed. This can be realized by forming the oxide film 12.

The present MOSFET 10 has exactly the same structure as the source / drain when the electrode metal of the wiring 14 is formed. Generally, a gate contact is also formed at the same time. However, since the gate is located at a higher position, an oxide film thickness on the gate is reduced by global flattening or the like, so that an optimal source / drain contact is obtained. It is possible to process under conditions.

Embodiment 2 Hereinafter, a method of forming an electrode of the buried wiring 14 of the MOSFET 10 of Embodiment 1 will be described with reference to FIGS. The present embodiment is an example of a process using both the wafer bonding method and the selective polishing method. FIG.
(A) and (b) and FIGS. 3 (c) to (f) show the first embodiment.
FIG. 4 is a cross-sectional view of the substrate in each step when forming the SOI structure of FIG. 2 and 3, the wiring and the embedded structure of the transistor are not shown for convenience. First, FIG.
As shown in (a), a 725 μm-thick 200 mm diameter T
A first silicon substrate 30 having a low TV is prepared, and FIG.
As shown in FIG. 1, the surface of the first silicon substrate 30 is subjected to etching to form a step 32 having a height difference of 0.06 μm, and then a silicon oxide film 34 having a thickness of 0.06 μm is formed. In order to form the wiring 14 shown in FIG. 1, after forming the silicon oxide film 34, the silicon oxide film 34 is etched to open an electrode formation region, and then a wiring layer is formed and patterned. To form Thus, the wiring 14 is exposed in the electrode formation region. Then, a buried oxide film 12 shown in FIG. 1 can be formed by forming a silicon oxide film (not shown) of 0.3 μm. Further, a 5 μm poly-Si film 3 is formed thereon.
6 is formed. The concave portion 32b of the silicon oxide film 34 shown in FIG. 2B is formed by selective polishing shown in FIG.
In this case, it has a function of a stopper and serves as an element isolation region for isolating islands (element formation regions) of the silicon thin film. The area under the protrusion 32a of the silicon oxide film 34 is an element formation region.

Next, as shown in FIG.
The surface of the i-film 36 is polished by a CMP method or the like to be a smooth surface. The second silicon substrate 38 which is the same as the first silicon substrate 30
Then, as shown in FIG. 3D, the smooth surface of the poly-Si film 36 of the first silicon substrate 30 and the surface of the second silicon substrate 38 are bonded to form a united wafer 40.
To form Next, as shown in FIG. 3E, the periphery of the united wafer 40 is ground to form a united wafer 40 having a trapezoidal cross section.
To form Further, as shown in FIG. 3F, the first silicon 30 substrate of the united wafer 40 is selectively polished so that the silicon layer 42 of 0.03 μm is left on the silicon oxide film 34. For polishing, for example, a chemical polishing method is used. The silicon layer 42 corresponds to the silicon thin film 13 in FIG.

Through the above steps, an SOI structure can be formed on the united wafer 40. Next, when a gate oxide film is formed, a gate electrode is formed, and the oxide film 18 is further formed, a wafer 44 having a buried structure as shown in FIG. 4A can be manufactured. Then, FIG.
As shown in FIG. 1B, when the contact holes 46 for the source / drain electrodes and the contact holes 48 for the wiring electrodes are simultaneously opened in the oxide film 18 and the electrodes 19 and 22 are further formed, the SOI structure shown in FIG. MOSFE with
T10 can be obtained.

Embodiment 3 This embodiment is another example of the method for forming the electrodes of the buried wiring 14 of the MOSFET 10 of the embodiment 1. In forming the SOI structure, only the wafer bonding method is used and the selective polishing method is used. This is an example that does not use. FIGS. 5A to 5E are cross-sectional views of the substrate in each step of forming an SOI structure in this embodiment. In FIG. 5, the wiring and the embedded structure of the transistor are not shown for convenience. First, as shown in FIG. 5 (a), a first silicon substrate 50 having a thickness of 725 μm and a diameter of 200 mm and having a low TTV is prepared, and the film thickness is formed on the first silicon substrate 50 as shown in FIG. 5 (b). A silicon oxide film 52 of 0.06 μm is formed. In order to form the wiring 14 shown in FIG. 1, the silicon oxide film 52 is etched to open an electrode formation region, and then a wiring layer is formed and patterned to form the wiring 14. Thus, the wiring 14 is exposed in the electrode formation region. Then, a buried oxide film 12 shown in FIG. 1 can be formed by forming a silicon oxide film (not shown) of 0.3 μm.
Next, a 5 μm poly-Si film 54 is formed thereon, and then the surface of the poly-Si film 54 is polished by a CMP method or the like to a smooth surface.

A second silicon substrate 56, which is the same as the first silicon substrate 50, is prepared. Subsequently, as shown in FIG.
The smooth surface of the poly-Si film 54 of the first silicon substrate 50 and the surface of the second silicon substrate 56 are bonded to form a united wafer 58. Next, as shown in FIG. 5D, the periphery of the united wafer 58 is ground to form a united wafer 58 having a trapezoidal cross section. Further, as shown in FIG. 5E, the first silicon 50 substrate of the united wafer 58 is polished so as to leave the silicon layer 60 of 0.03 μm on the silicon oxide film 52. For the polishing, for example, a CMP method or a chemical polishing method is used. The silicon layer 60 corresponds to the silicon thin film 13 in FIG. In this embodiment, since the silicon thin film is connected on the entire surface of the wafer, the LOCOS or T
Element isolation is performed by the trench method. Also, the poly-Si film 54
Is a layer added to facilitate the flattening of the bonding surface, and is not necessarily required in the present embodiment.

Through the above steps, an SOI structure can be formed. Next, a gate oxide film is formed, a gate electrode is formed, and an oxide film 18 is further formed.
A wafer having the embedded structure shown in (a) can be manufactured. Then, in the same manner as in Example 2, FIG.
As shown in FIG. 1B, when the contact holes 46 for the source / drain electrodes and the contact holes 48 for the wiring electrodes are simultaneously opened in the oxide film 18 and the electrodes 19 and 22 are further formed, the SOI structure shown in FIG. MOSFE with
T10 can be obtained.

COMPARATIVE EXAMPLE This comparative example is an MO having the SOI structure shown in FIG.
This is a method of forming an electrode of an SFET wiring. FIGS. 6A and 6B are cross-sectional views of the substrate in each step for forming an electrode, following FIG. 7A. First, as shown in FIG. 6A, as a first etching step, the oxide film 18 and the buried oxide film 12 on the contact formation portion of the wiring 14 are etched, and the thickness of the buried oxide film 12 at the bottom of the hole is formed. A first windowing step is performed to form a first windowing hole 62 whose thickness is less than or equal to the thickness of oxide film 18 on the source / drain contacts. Next, as shown in FIG. 6B, a contact hole for a source / drain contact and a contact hole for a wiring contact are simultaneously formed, and then electrodes 64 and 66 are formed.

In this comparative example, the contact hole for forming the source / drain contact is formed by performing the first windowing step without shaving the silicon thin film 13 having the SOI structure, and thus without deteriorating the characteristics of the FET. In addition, a contact hole for forming a wiring contact can be opened. However, in this comparative example, since the number of windowing steps is one more than in the second and third embodiments, the number of photolithography and etching processes is increased by one each. Therefore, the manufacturing cost increases, the quality control becomes complicated, and the product yield decreases accordingly. On the other hand, Example 2
In the third embodiment, the process of contacting the SOI layer from the embedded layer, for example, the embedded wiring, is an additional process, except for the case where the embedded layer is only the lower electrode of the MOSFET. It does not increase. For example, in the case where the wiring is formed as an embedded layer, since there is a portion connected to the source or drain of the MOSFET, it can be formed simultaneously.

[0023]

According to the structure of the present invention, there are provided a connection portion made of a silicon thin film which is electrically connected to the buried body and formed simultaneously with the silicon thin film having the SOI structure, and an electrode which is electrically connected to the connection portion. Thus, for example, in the case of a MOSFET having an SOI structure, the electrode of the embedded layer can be formed without deteriorating the characteristics of the MOSFET and without increasing the number of process steps. In addition, the process latitude in forming the electrodes is large.
The electrode structure according to the present invention has a structure including S
A semiconductor chip having an OI structure, particularly a low power supply voltage circuit,
Most suitable for electrode structure of semiconductor chip for low power consumption circuit. Further, the electrode forming method according to the present invention is most suitable for forming the electrode structure according to the present invention.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view illustrating a layer structure of a MOSFET according to an embodiment.

FIGS. 2A and 2B are cross-sectional views of a substrate at each step of a method of Example 2 for forming an SOI structure of Example 1. FIGS.

FIGS. 3 (c) to 3 (f) are cross-sectional views of the substrate at each step of the method of Example 2 for forming the SOI structure of Example 1, following FIG. 2 (b).

FIGS. 4 (a) and 4 (b) are cross-sectional views of the substrate at each step when forming the MOSFET of Example 1 having an SOI structure, following FIG. 3 (f).

5 (a) to 5 (e) are cross-sectional views of a substrate in each step of a third embodiment method for forming the SOI structure of the first embodiment.

FIGS. 6A and 6B are cross-sectional views of a substrate in each step of a comparative example method.

7 (a) and 7 (b) are cross-sectional views of a substrate at respective steps of a conventional method for forming an electrode of an embedded body having an SOI structure.

[Explanation of symbols]

Reference numeral 10: MOSFET having an electrode structure of an embedded layer according to the present invention, 11: substrate, 12: buried oxide film, 13: silicon thin film, 14: wiring, 15: source region, 16 ... ... Drain region, 17 ... Gate electrode, 18 ... Oxide film, 19 ... Electrode, 20 ... Silicon thin film island (connection), 22 ... Electrode metal, 30 ... First silicon substrate, 32 ... Step, 32a ... Projection, 32
b: recess, 34: silicon oxide film, 36: poly S
i-film, 38 second silicon substrate, 40 united wafer, 44 wafer 46, contact hole for source / drain electrode, 48 contact hole for electrode for wiring, 50 first silicon Substrate, 52: silicon oxide film, 54: poly-Si film, 56: second silicon substrate, 58: united wafer, 60: silicon thin film, 62
... First window, 64, electrode, 66, electrode, 70
... MOSFET with conventional electrode structure.

Claims (7)

[Claims] 1. An electrode structure of a SOI structure substrate or an embedded layer formed in an insulating film formed by forming a silicon thin film on a substrate via an insulating film, and electrically connected to the embedded member. An electrode structure of a buried-layered body, comprising: a connecting portion made of a silicon thin film formed simultaneously with a silicon thin film having an SOI structure; and an electrode conducting to the connecting portion. 2. The electrode structure of an embedded layer body according to claim 1, wherein the substrate is a substrate made of Si or a substrate made of a compound semiconductor. 3. The electrode structure according to claim 1, wherein the insulating film is made of SiO ₂ or SiN. 4. The passive element including a bottom electrode of a MOSFET, a wiring, and a capacitor,
4. The electrode structure of the embedded layer body according to claim 1, wherein the electrode structure is any one of an active element including a TFT. 5. 5. The semiconductor device according to claim 1, wherein the thin film is a compound semiconductor thin film instead of the silicon thin film having the SOI structure.
5. The electrode structure of the in-layer embedded body according to any one of items 1 to 4. 6. A method of forming an electrode on a substrate having an SOI structure in which a silicon thin film is formed on a substrate with an insulating film interposed therebetween or an embedded material in a layer formed in the insulating film, comprising: a silicon layer; A buried oxide film formed on the silicon layer, an in-layer buried body formed in the buried oxide film so as to be electrically connected to an electrode region defined in a predetermined region of the silicon layer, and a buried oxide film Forming a first wafer having a poly-Si film formed thereon; and bonding the first wafer and a second wafer made of silicon with the surface of the poly-Si film of the first wafer as an interface. By the method, on the silicon layer of the second wafer,
Forming a combined wafer comprising a poly-Si film, a buried oxide film, and a silicon layer of the first wafer, and leaving a silicon thin film constituting an SOI structure,
Polishing the silicon layer of the first wafer to simultaneously form an electrode region of the silicon thin film and a silicon thin film constituting the SOI structure on the buried oxide film; and forming an electrode conducting to the electrode region of the silicon thin film. A method for forming an electrode structure of an in-layer embedded body, comprising: 7. The electrode according to claim 6, wherein in the step of forming the first wafer, a step is formed by etching the silicon layer, and then a buried oxide film is formed. The method of forming the structure.