JPH10276198A - Distributed shared memory network device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To maintain a network system by conducting monitor of a state of a memory and a communication equipment, providing an RAS section that bypasses packets to other node and disconnecting a node on the occurrence of a fault including a power failure from the network. SOLUTION: The device diagnoses, and monitors a state of RMU 12a-12c and each of the RMU 12a-12c is provided with each of RAS sections 14a-14c which bypass a packet received by link control sections 17a-17c to other node directly on the occurrence of a fault including power failure. Thus, data are copied and shared in common without notifying communication by CPU 11a-11c and a network ring is maintained even on the occurrence of a fault of a node or a power failure, then other node utilizes the RMU 12a-12c independently of the fault.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a network connection between memory boards of a distributed shared memory unit, transmission of rewriting of a memory value of a certain node to a network,
The present invention relates to a distributed shared memory network device for sharing data by causing each node to reflect received contents in its own memory.

[0002]

2. Description of the Related Art FIG. 28 is a block diagram showing a conventional distributed shared memory network device disclosed in, for example, Japanese Patent Application Laid-Open No. 6-68047, and FIG. FIG. 1 is an explanatory diagram, in which 1 is a network, 2 to 5 are nodes, and 6 to 9 are network access control units connected to the network 1 and the nodes 2 to 5. In the network access controllers 6 to 9, 6a to 9a are communication means, and 6b to 9b
Denotes a data unit relay unit, and 6c to 9c denote memory access control units.

Next, the operation will be described. Communication means 6a
9a to 9a receive the data from the network 1 and deliver the data to the data unit relay means 6b to 9b and the memory access control means 6c to 9c. Data unit relaying means 6b-9b
Holds this data until there is a relay request from the memory access control means 6c to 9c. The memory access control means 6c to 9c determine whether or not the transferred data is memory information, and if it is memory information, confirm whether a read request is issued from the nodes 2 to 5. Nodes 2-5
, The memory access control means 6c-9c compares the memory address with the memory address in the data unit of the received data. If the addresses match, the memory access control means 6c to 9c
Is the contents of the data area of the received data unit
Transfer to 5.

[0004] Thereafter, a request is made to the data unit relay means 6b to 9b for relaying. If a write request has been issued from the nodes 2 to 5, the memory access control means 6c to 9c compare the memory address with the memory address in the data unit of the received data. If the addresses match, the memory access control means 6c to 9c replace the contents of the data area of the received data unit with the write request data, and request the data unit relay means 6b to 9b to relay. The memory access control units 6c to 9c transfer the received data unit as it is or the rewritten data unit to the communication units 6a to 9a, and request transmission of the data unit to the network 1. As described above, since the memory information is periodically transferred within the network 1 and all data can be referred to, shared storage between the nodes 2 to 5 can be easily realized at low cost.

[0005]

Since the conventional distributed shared memory network device is configured as described above,
Since the functions of monitoring the state of the memory and the communication device and controlling the state of the network are lacking, there is a problem that the communication system may be broken by a failure of a certain node.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and a distributed shared memory network device capable of maintaining a network system by detaching a node from a network at the time of a failure including a power failure. The purpose is to gain.

[0007]

According to a first aspect of the present invention, there is provided a distributed shared memory network device for diagnosing and monitoring the state of a distributed shared memory unit and, when a failure including power interruption occurs, a packet received by a link control unit. It has a RAS unit that bypasses directly to another node.

According to a second aspect of the present invention, there is provided a distributed shared memory network device, wherein the memory control unit includes a CPU access type setting unit in which an endian type of a CPU is set, and a load or store instruction from the CPU. And a CPU access conversion unit that converts the data into the endian type set in the above and accesses the local memory unit.

According to a third aspect of the present invention, in the distributed shared memory network device, the memory control unit includes a memory reading unit that reads data from the local memory unit in accordance with a designated address in a store instruction from the CPU; When a memory write instruction comparison unit that compares write data in an instruction with data read by a memory read unit and the memory write instruction comparison unit determines that the write data and the read data are different. And a memory writing unit for writing write data to a specified address of the local memory unit.

According to a fourth aspect of the present invention, in the distributed shared memory network device, the memory control unit receives a burst transfer or a DMA transfer in a store instruction from the CPU, and the block reception control unit receives the burst transfer or the DMA transfer. And a block writing unit for writing the block data to the local memory unit. The transfer control unit generates a block packet including the block data received by the block reception control unit, and the block received via the link control unit. It has a block packet transmission / reception unit that outputs a packet to a memory control unit.

According to a fifth aspect of the present invention, in the distributed shared memory network device, the memory control unit includes an interrupt condition setting unit in which an interrupt generation condition is set in advance by the CPU, a received packet and its interrupt condition setting unit. An interrupt condition judging unit that collates with a set interrupt occurrence condition to judge the occurrence of an interrupt, and an interrupt control unit that notifies the CPU of an interrupt when the interrupt condition judging unit judges the interrupt occurrence. It is.

According to a sixth aspect of the present invention, there is provided a distributed shared memory network device, wherein the transfer control unit includes a network entry control unit to which a node ID is set when newly joining a network, and the network entry control unit sets the node ID. A network entry request unit that generates an entry packet including the received node ID and outputs it to the transfer control unit, and if the received packet is an entry packet, the node ID included in the entry packet matches the own node ID An error bit is added to the received packet and the packet is output to the transfer control unit.
A node ID determination unit that determines that the own node can enter when receiving an entry packet that matches D and does not have an error bit added.

According to a seventh aspect of the present invention, in the distributed shared memory network device, the node ID is output to the network entry control unit starting from the initial value to the transfer control unit and the failure of entry determined by the node ID determination unit is determined. It has a node ID automatic setting unit for increasing the node ID each time and outputting the same to the network entry control unit.

In the distributed shared memory network device according to the present invention, when the RAS unit fails to join in the transfer control unit, the RAS unit displays the entry failure on the entry failure display unit and receives the failure by the link control unit. Is directly bypassed to another node.

According to a ninth aspect of the present invention, in the distributed shared memory network device, the transfer control unit includes: A longevity packet processing unit for rejecting packets exceeding a predetermined number of times.

According to a tenth aspect of the present invention, in the distributed shared memory network device, the transfer control unit includes a maximum node ID detection unit for detecting a maximum value of a node ID of a received packet, and the maximum node ID detection unit. It has a maximum node ID recording unit that records the maximum value of the detected node IDs and sets it as a predetermined number of times in the longevity packet processing unit.

A distributed shared memory network device according to an eleventh aspect of the present invention provides the transfer control unit with a circulation timer unit for outputting a fault occurrence to the RAS unit when a predetermined time has elapsed, and a circulation timer unit for transmitting a packet. A round timer reset section for resetting the section, and a round timer clear section for clearing the round timer section when the packet is received.

According to a twelfth aspect of the present invention, in the distributed shared memory network device, the transmission control unit records a packet transmitted from the own node, the node ID of the received packet, and the own node ID. A packet circulating unit that detects a match between packets and, when a packet is detected by the packet circulating unit, compares the contents of the packet recorded in the transmission buffer unit with the contents of the received packet and forwards the packet by circulating. It includes a recurring packet error detection unit for detecting an error, and a retransmission control unit for retransmitting the packet recorded in the transmission buffer unit when a transmission error is detected by the recurring packet error detection unit.

In the distributed shared memory network device according to the invention, a match is detected in the transfer control unit by the FIFO buffer unit for recording a plurality of packets transmitted from the own node and the round packet detection unit. In this case, a circulating packet error detecting unit that compares the contents of the first packet recorded in the FIFO buffer unit and the received packet and detects a transfer error due to circulating of the packet;
If no transfer error is detected by the circulating packet error detection unit, the leading packet recorded in the FIFO buffer unit is incremented by one, and if a transfer error is detected, all packets recorded in the FIFO buffer unit are incremented. And a retransmission control unit that retransmits the packet with the retransmission bit set, and rejects the packet when the received packet does not have the retransmission bit set.

According to a fourteenth aspect of the present invention, there is provided a distributed shared memory network device, comprising: a relay FIFO buffer unit for recording received packets until transmission is possible;
A transmission priority control unit for giving priority to the transmission processing of the FIFO buffer unit over the relay processing by the relay FIFO buffer unit when the buffer unit is full.

According to a fifteenth aspect of the present invention, in the distributed shared memory network device, the transfer control unit includes a transmission suppressing unit for stopping transmission of a packet from the own node according to a setting from the CPU.

According to a sixteenth aspect of the present invention, the writable area of the local memory unit is set in the memory control unit by the CPU, and the CP
If the store instruction from U is within the writable area, the memory writing unit writes the data to the local memory unit. .

According to a seventeenth aspect of the present invention, in the distributed shared memory network device, the transfer control unit includes a CRC coding unit for performing CRC coding on a packet to be transmitted;
A CRC decryption unit for decrypting the RC-encoded packet;
It has a packet error setting section for checking the error of the packet received by the decoding by the CRC decoding section.

The distributed shared memory network device according to the present invention transmits a semaphore state unit for setting a semaphore state of a node and a request and lock packet relating to a semaphore request to the transfer control unit in accordance with an instruction from the CPU. If the received packet has a semaphore request, the semaphore state part is set to the request, and if the received packet has a lock semaphore request, the semaphore state part is the request. And a semaphore management unit that sets the semaphore state unit to locked.

According to a nineteenth aspect of the present invention, in the distributed shared memory network device, the link control unit includes a bypass unit for directly bypassing a packet received in accordance with an instruction from the RAS unit to another node.

According to a twentieth aspect of the present invention, there is provided a distributed shared memory network device, which is connected between a distributed shared memory unit and a network and bypasses a received packet directly to another node, and a bypass box thereof. And a manual switch unit for manually switching the units.

According to a twenty-first aspect of the present invention, a distributed shared memory network device is connected between a distributed shared memory unit and a network and bypasses a received packet directly to another node. And a bypass switch section for switching the section according to an instruction from the RAS section.

[0028] The distributed shared memory network device according to the invention as claimed in claim 22, further comprising an equalizing packet transmitting unit for transmitting an equalizing request packet to the memory control unit in accordance with an instruction from the CPU; In the case of, the data in the writable area of the local memory unit is read by the memory cycle reading unit at the designated cycle, the read data is transmitted as a packet, and the received packet of the equalizing request is transmitted. And an equalizing control unit.

The distributed shared memory network device according to claim 23, wherein an equalizing packet transmitting unit for transmitting an equalizing request packet to the memory control unit in accordance with an instruction from the CPU, and wherein the received packet is an equalizing request packet. In the case of, the received equalizing request packet and the equalizing start packet are transmitted, and the memory cycle reading unit causes the data of the writable area of the local memory unit to be read at a specified cycle, and the read data is read. And an equalizing control unit that transmits an equalizing end packet, and an equalizing state that manages an equalizing operation state by receiving the equalizing start packet and the equalizing end packet. It is obtained and a recording unit.

[0030] The distributed shared memory network device according to the invention of claim 24 receives an entry request unit for transmitting a join notification packet including its own node ID to the transfer control unit when the join is successful, and receives the join notification packet. In this case, an entry recording unit for extracting and recording the node ID from the packet is provided.

[0031]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. Embodiment 1 FIG. FIG. 1 is a block diagram showing a distributed shared memory network device according to Embodiment 1 of the present invention. In the figure, reference numerals 11a to 11c denote CPUs, and 12a to 1c.
2c is a distributed shared memory unit (hereinafter referred to as RMU) connected to each of the CPUs 11a to 11c, and 18 is a network connected to the RMUs 12a to 12c by a slotted ring.

In each of the RMUs 12a to 12c, 13a to 13c are local memory units accessed by the CPUs 11a to 11c, and 15a to 15c are C
A memory control unit that accesses the local memory units 13a to 13c in response to load or store instructions from the PUs 11a to 11c, and accesses the local memory units 13a to 13c in response to received packets. 16a to 16c generate a packet in response to a store command from the CPUs 11a to 11c and, if the received packet is a valid packet,
Transfer control units for outputting the received packets to 5a to 15c, 17a to 17c are transfer control units 16a to 16c
Is transmitted to the network 18 and the packet is received from the network 18. If the received packet is transmitted from the own node, the received packet is rejected and transmitted from another node. If it is a link control unit, the link control unit outputs the received packet to the transfer control units 16a to 16c. Further, 14a to 14c diagnose and monitor the state of the RMUs 12a to 12c, and when a failure including power interruption occurs, the link control unit 17a.
This is an RAS unit that bypasses packets received by a to 17c directly to another node.

Next, the operation will be described. Here, for simplicity of description, the description will be focused on the a node. CPU
The memory 11a can load or store the local memory 13a of the RMU 12a as an extended memory. CPU
The load or store instruction from the memory 11a is sent to the memory control unit 15a via the bus. The memory control unit 15a reads the data of the address of the local memory unit 13a corresponding to the designated address if the load instruction, and reads the data from the CPU.
11a. In the case of a store instruction, data is written to the address of the local memory unit 13a corresponding to the designated address, and the address and data of the store instruction are output to the transfer control unit 16a. Transfer control unit 16a
Has a unique node I in the network 18 previously set in the control register.
By adding D and the attribute information of the packet, a packet as shown in FIG. 25 is generated, put into a transmission queue, and output.
If there is a received packet, the link control unit 17a gives priority to receiving the received packet, and thereafter transmits the packet in the transmission queue to the network 18.

The packet transmitted from the RMU 12a is received by the adjacent RMU 12b of the b node, for example, and the link control unit 17b checks the node ID of the received packet. If the packet is discarded or transmitted by another node, the packet is output to the transfer control unit 16b. The transfer control unit 16b confirms an interrupt designation and an error flag from the attribute information included in the received packet, and outputs the packet to the memory control unit 15b if it is determined that the packet is valid. In the memory control unit 15b,
Based on the address and data included in the received packet, data is written to a corresponding address in the local memory unit 13b. In the transfer control unit 16b, if an error and an interrupt are specified in the received packet, the packet is written into the control register of the RMU 12b,
An interrupt is notified to the PU 11b. Thus, the CPU 11
a is the local memory unit 13 of the RMU 12a
a and the local memory 13b of the RMU 12b. Similarly, the packet received by the link control unit 17b is also reflected in the local memory unit 13c of the RMU 12c of the c node, and the RMU of each node sequentially stores the packet in the RMU of each node.
Store instruction is reflected. Thus, the consistency of the contents of the RMU of each node is maintained.

The network 18 is of a slotted ring type in which nodes are sequentially connected, and packets are successively relayed to adjacent nodes. If the node ID of the received packet coincides with the own node ID, the received packet is transmitted by itself and has been circulated to all nodes, so that the link control unit 17 completes reflection on all nodes. And discard the packet.

If a catastrophic failure occurs in the RMU 12a or the power is turned off, the link control unit 17a does not operate.
It will be cut inside 7a. Therefore, RAS1
In 4a, the state of the RMU 12a is diagnosed and monitored, and in the event of a failure including power interruption, the network 18 and the transfer control unit 16a
By interrupting the path to and directly bypassing other nodes, a network ring is maintained and communication of other nodes is not hindered.

As described above, according to the first embodiment, the statuses of the RMUs 12a to 12c are diagnosed and monitored, and in the event of a fault including a power failure, the packets received by the link control units 17a to 17c are directly bypassed to another node. RAS part 1
Since the RMUs 4a to 14c are provided, a network ring can be maintained even if a failure including a power failure occurs in the RMUs 12a to 12c, and other nodes can share the local memory unit independently.

Embodiment 2 FIG. 2 is a block diagram showing a distributed shared memory network device according to a second embodiment of the present invention. In FIG.
a, a CPU access type setting unit for setting the CPU type of the CPU 11a;
Is a CPU access conversion unit that converts a load or store instruction from the CPU into a CPU type set in the CPU access type setting unit 21a and accesses the local memory unit 13a. The configurations of the b-node and the c-node are the same as those of the a-node, and the other configurations are the same as those of FIG.

Next, the operation will be described. Generally CPU
Are classified into two types, big endian and little endian, depending on whether the register bit is written from the upper or lower address of the memory address when the CPU register is stored in the memory. In addition, short type, int type,
The arrangement of word non-boundary accesses by the long type is also different. However, in the RMU 12a, the local memory 13
It is necessary to make a match in the network without depending on the CPU 11a. Therefore, a conversion pattern for the endian type of the CPU 11a and a word non-boundary access at the time of non-word boundary access is previously set as a CPU type in the CPU access type setting unit 21a such as a control register. Sometimes, the CPU access type setting unit 21a
Is converted into a value valid for the CPU 11a and written to the local memory unit 13a or returned to the CPU 11a in accordance with the CPU type set in (1).

As described above, according to the second embodiment, the load or store instruction from the CPU 11a is stored in the memory control unit 15a.
CPU access converter 22 for converting to the CPU type set to a and accessing local memory unit 13a
Since a is provided, a distributed shared memory network device in which different types of CPUs are mixed can be configured.

Embodiment 3 FIG. 3 is a block diagram showing a distributed shared memory network device according to a third embodiment of the present invention.
a, a memory read unit that reads data in the local memory unit 13a in accordance with a designated address in a store instruction from the CPU 11a;
The memory write command comparison unit 32a compares the write data in the store command from the memory read unit 31a with the data read by the memory read unit 31a. When it is determined that the data is present, the memory writing unit writes the write data to the specified address of the local memory unit 13a. The configurations of the b-node and the c-node are the same as those of the a-node, and the other configurations are the same as those of FIG.

Next, the operation will be described. CPU 11a
In many cases, a store instruction from the first to the local memory unit 13a is not always a new value but overwrites the same value. At this time, if the packets are transmitted to the network 18 one by one, there is much communication waste. In FIG. 3, the CPU 1
When a store instruction is output from the memory control unit 15a to the memory control unit 15a, the memory read unit 31a reads the data at the specified address from the local memory unit 13a, and the memory write instruction comparison unit 33a reads the data at the specified address and the store instruction. When new data is stored as compared with the write data, the memory writing unit 32a writes the write data in the local memory unit 13a, generates a packet, and outputs the packet to the transfer control unit 16a.

As described above, according to the third embodiment, new data is stored by comparing the data at the designated address of the local memory unit 13a with the write data of the store instruction by the memory write instruction comparison unit 33a. If the memory writing unit 32a
The write data is written to the transfer control unit 16a, and the packet is generated and output to the transfer control unit 16a. Available.

Embodiment 4 FIG. FIG. 4 is a block diagram showing a distributed shared memory network device according to a fourth embodiment of the present invention. In FIG.
a, which receives a burst transfer or a DMA transfer in a store command from the CPU 11a, and 42a stores the block data received by the block reception controller 41a in the local memory 13a.
, A block writing unit 43a for writing to the transfer control unit 16
a, which generates a block packet including the block data received by the block reception control unit 41a and outputs the block packet received via the link control unit 17a to the memory control unit 15a. is there. The configurations of the b-node and the c-node are the same as those of the a-node, and the other configurations are the same as those of FIG.

Next, the operation will be described. CPU 11a
Access to the RMU 12a is not limited to a load or store instruction, but may be a CP transfer such as a burst transfer or a DMA transfer.
In most cases, transfer of block data much longer than the U word length is possible. At this time, the memory control unit 1
The block reception control unit 41a receives the block data from the CPU 11a, and the block writing unit 42a writes the block data into the local memory unit 13a.
Further, in order to transmit the block data, the block data is transmitted to the block packet transmitting / receiving section 43 of the transfer control section 16a.
output to a. In the block packet transmitting / receiving unit 43a,
A block packet is generated by setting the node ID and the block bit, and output to the link control unit 17a. On the other hand, the block packet received via the link control unit 17a is output to the block packet transmitting / receiving unit 43a,
The memory controller 15a writes the block data to the local memory 13a corresponding to the designated address of the block packet.

The block packet is basically the same as the word packet shown in FIG. 25, except that the data portion has a size of a plurality of words. Therefore, since the data ratio per packet increases, the data transfer throughput improves. In addition, since word packets and block packets are mixed, packet processing and transfer processing become complicated.
The block packet has a fixed length. There are various combinations of the arrangement order of each item in the packet.

As described above, according to the fourth embodiment, the block reception control unit 41 that receives a burst transfer or a DMA transfer in a store command from the CPU 11a.
a and a block packet including the block data received by the block reception control unit 41a is generated,
Since the block packet transmitting / receiving unit 43a that outputs the block packet received via the link control unit 17a to the memory control unit 15a is provided, the block transfer from the CPU 11a can be directly reflected in the local memory units 13a to 13c, The transfer from the CPU 11a to the local memory unit 13a and the transfer between the RMUs 12a to 12c become faster, and the communication band can be saved.

Embodiment 5 FIG. FIG. 5 is a block diagram showing a distributed shared memory network device according to a fifth embodiment of the present invention.
a, an interrupt condition setting unit 51a in which an interrupt generation condition is set in advance by the CPU 11a, 51a compares the received packet with the interrupt generation condition set in the interrupt condition setting unit 53a, and determines the occurrence of an interrupt. The interrupt condition judging unit 52a performs an interrupt when the interrupt condition judging unit 53a judges that an interrupt has occurred.
An interrupt control unit that notifies the CPU 11a of an interrupt. The configurations of the b-node and the c-node are the same as those of the a-node, and the other configurations are the same as those of FIG.

Next, the operation will be described. The condition for notifying the CPU 11a of the received packet is set in advance by the CPU 11a by the interrupt condition setting unit 53a.
Set to. The interrupt condition setting unit 53a is configured by a register and the like. The interrupt condition determining unit 51a determines the packet received from the link control unit 17a based on the condition set in the interrupt condition setting unit 53a. For example, if an interrupt bit is set, an illegal address is accessed, an interrupt flag is set in a packet, or the like, matches the value set in the register of the interrupt condition setting unit 53a, the interrupt control unit 52a
Is instructed to notify the CPU 11a of the interruption.
At this time, the cause of the interrupt is written in a part of the register of the interrupt condition setting unit 53a. CPU1
1a can know the interrupt factor by looking at the register in the interrupt processing.

As described above, according to the fifth embodiment, the received packet is compared with the interrupt occurrence condition set in the interrupt condition setting unit 53a, and when it is determined that an interrupt has occurred, the interrupt control unit 52a is determined. From CPU 11
Since the interrupt condition determination unit 51a for notifying the interrupt is provided, the interrupt condition can be set and the interrupt can be notified in the RMU 12a.

Embodiment 6 FIG. FIG. 6 is a block diagram showing a distributed shared memory network device according to Embodiment 6 of the present invention. In the figure, reference numeral 62a denotes a transfer control unit 16a.
Inside the network 18 when entering the network 18
The network entry control unit 63a in which the node ID is set by the PU 11a, 63a is the network entry control unit 62
a network entry requesting unit that generates an entry packet including the node ID set in a and outputs it to the transfer control unit 17a
61a indicates that when the received packet is an entry packet, the node ID included in the entry packet is its own node ID.
Is a node ID determining unit that rejects the received packet if it matches with the own node ID and determines that the own node can join if the own node matches the own node ID during the new entry request. The configurations of the b-node and the c-node are the same as those of the a-node, and the other configurations are the same as those of FIG.

Next, the operation will be described. RMU12a
Is not connected to the network 18 in the initial state, so that the link control unit 17a is controlled so that the packet can be relayed. Furthermore, in order to transmit a packet to another node, in order to collect the packet transmitted by the own node, it is necessary to acquire a node ID of the only network added to the packet. The CPU 11a stores the node ID given in advance in the network entry control unit 62.
Set to “a” to instruct network entry. In response to the instruction from the network entry control unit 62a, the network entry requesting unit 63a generates an entry packet including the set node ID, and transmits the entry packet to the network 18 via the link control unit 17a.

The node ID judging section 61a checks the node IDs of all the packets received by the link control section 17a, relays the packet containing the node ID different from the own node ID, and outputs the own node ID when no new entry request is being made. When a packet including a node ID that matches with is received, the packet is rejected. If a packet including a node ID that matches the own node ID is received during the new entry request, it is determined that the packet was not rejected by the node ID determination units 61b and 61c of other nodes, that is, there was no matching node ID. If it is determined that the own node ID is unique on the network 18, the local memory units 13a to 13
network 18 capable of transmitting the packet reflected in c.
Is determined to be able to enter. If the entry packet does not return after a certain time, it is determined that the network entry has failed, and the network connection of the link control unit 17a is bypassed.

In the sixth embodiment, the node ID
When the determination unit 61a receives a packet including a node ID that matches the own node ID when a new entry request is not being issued, the packet is discarded. In this case, it is determined that the network entry has failed if a certain time has not passed. Can not do it. Therefore, the node ID determination unit 61a
When a packet including a node ID matching the own node ID is received when a new entry request is not being made, an error bit is set without rejecting the packet and the link control unit 17a is set.
, The transmission source node can determine that the network entry has failed without waiting for the timeout of the entry packet.

As described above, according to the sixth embodiment, the node ID included in the entry packet
If it matches, the packet is rejected, and if the own node matches the own node ID during the new entry request, the node ID determination unit 61a determines that the own node can enter.
Is provided, it is possible to detect duplicate node ID settings when newly entering the network 18, and to avoid communication troubles due to setting errors in advance.

Embodiment 7 FIG. FIG. 7 is a block diagram showing a distributed shared memory network device according to Embodiment 7 of the present invention. In the figure, reference numeral 74a denotes a transfer control unit 16a.
And outputs the node ID to the network entry control unit 62a starting from the initial value, and increases the node ID every time entry failure is determined by the node ID determination unit 61a. This is a node ID automatic setting unit to output. The configurations of the b-node and the c-node are the same as those of the a-node, and the other configurations are the same as those of FIG.

Next, the operation will be described. Embodiment 6
Now, the network entry control unit 62 is controlled by the CPU 11a.
In the seventh embodiment, the own node ID is set in the network entry control unit 62a by the node ID automatic setting unit 74a. First, the node ID automatic setting unit 74a sets the initial value of the own node ID in the network entry control unit 62a. The packet circulates on the network 18, and the node ID determination unit 61a
Each time it is determined that the network entry has failed, the node ID automatic setting unit 74a increments or decrements the own node ID and resets the own node ID. In this manner, by sequentially updating the own node ID and transmitting the entry packet, the own node ID whose uniqueness is guaranteed is finally found, and the network is entered by the own node ID.

As described above, according to the seventh embodiment, the node ID is started from the initial value, and
Since the node ID automatic setting unit 74a that increases the node ID and outputs the node ID to the network entry control unit 62a every time the entry failure is determined by 1a is provided, in the sixth embodiment, there is no choice but to set manually. Node I
D can be automatically set.

Embodiment 8 FIG. FIG. 8 is a block diagram showing a distributed shared memory network device according to an eighth embodiment of the present invention. In the figure, reference numeral 81a denotes an entry failure display unit, and RAS unit 14a is used when the transfer control unit 16a fails to enter the network. The entry failure display section 81a
Is displayed, and a packet received by the link control unit 17a is directly bypassed to another node. The configurations of the b-node and the c-node are the same as those of the a-node, and the other configurations are the same as those of FIG.

Next, the operation will be described. Transfer control unit 1
6a, when the network entry fails, the RAS unit 14a
The RAS unit 14a instructs the link control unit 17a to bypass the network 18 and displays a network entry failure signal on an entry failure display unit 81a such as an LED. In the RAS unit 14a,
An entry failure flag is set in a space accessible by the CPU 11a.

As described above, according to the eighth embodiment, when the transfer control section 16a fails to join the network, the entry failure display section 81a displays the entry failure and the link control section 17a receives the entry failure. Since the RAS unit 14a that directly bypasses the packet to another node is provided,
By bypassing the network 18 due to network entry failure, it is possible to prevent network operation in a state where node IDs are duplicated. Further, by externally displaying the failure to enter the network, trouble finding becomes easy.

Embodiment 9 FIG. 9 is a block diagram showing a distributed shared memory network device according to Embodiment 9 of the present invention. In the figure, reference numeral 91a denotes a transfer control unit 16a.
A relay counter unit that is provided within and increases the number of relays included in the received packet for each relay of the received packet;
Reference numeral 92a denotes a long-lived packet processing unit for excluding packets whose number of relays exceeds a predetermined number. b-node and c
The configuration of the node is the same as that of the a-node, and the other configuration is the same as that of FIG.

Next, the operation will be described. As shown in FIG. 26, a packet is provided with a relay count which is increased every time a packet is relayed.
1a increases the number of relays. If the MRU of the node that transmitted the packet stops before collecting the circulating packet, the packet has to roam the network 18 forever because there is no collection source. Therefore, the longevity packet processing unit 92a compares the predetermined number of times with the number of relays included in the packet, and if the number of relays exceeds the predetermined number, discards the packet without relaying.

As described above, according to the ninth embodiment, each time a received packet is relayed, the relay counter 91a increases the number of relays included in the packet, and the number of relays exceeds a predetermined number. Since the longevity packet processing unit 92a that excludes the packet is provided, even if a failure occurs in the transmission source node during the packet circulation, the illegal packet can be detected by the number of relays and the packet can be discarded. Robustness and fault analysis can be improved.

Embodiment 10 FIG. FIG. 10 is a block diagram showing a distributed shared memory network device according to Embodiment 10 of the present invention. In the figure, 101a is provided in the transfer control unit 16a, and receives a node I of a received packet.
A maximum node ID detector for detecting the highest value of D, 102a
Records the highest value of the node ID detected by the maximum node ID detection unit 101a,
This is a maximum node ID recording unit that is set as a predetermined number in a. The configurations of the b-node and the c-node are the same as those of the a-node, and the other configurations are the same as those of FIG.

Next, the operation will be described. Maximum node I
The D detection unit 101a detects the highest value of the node ID of the received packet. Also, the maximum node ID detection unit 101a
The maximum value of the node ID detected by the above is recorded and set as a predetermined number of times in the longevity packet processing unit 92a. In the longevity packet processing unit 92a, as described in the tenth embodiment, the predetermined number is compared with the number of relays included in the packet, and when the number of relays exceeds the predetermined number, the packet is not relayed. Discard the packet.

As described above, according to the tenth embodiment, the maximum node ID detecting section 101a for detecting the maximum value of the node ID of the received packet, the maximum value of the node ID is recorded, and the longevity packet is recorded. Since the processing unit 92a is provided with the maximum node ID recording unit 102a which is set as a predetermined number of times, the learning can be automatically performed without setting the predetermined number of times in advance. The determination can be made at an early stage.

Embodiment 11 FIG. FIG. 11 is a block diagram showing a distributed shared memory network device according to an eleventh embodiment of the present invention. In the figure, reference numeral 110a is provided in the transfer control unit 16a, and when a predetermined time has elapsed, R
A circulating timer unit that outputs a fault occurrence to the AS unit 14a, 11
1a is a round timer reset unit that resets the round timer unit 110a when transmitting a packet, and 112a is a round timer clear unit that clears the round timer unit 110a when receiving the packet. The configurations of the b-node and the c-node are the same as those of the a-node, and the other configurations are the same as those of FIG.

Next, the operation will be described. When transmitting a packet, the circulation timer reset unit 111a resets the circulation timer unit 110a, and when the circulation packet is received, the circulation timer clear unit 112a clears the circulation timer unit 110a. When the cycle timer unit 110a detects a timeout, the time is output to the RAS unit 14a, and it is considered that a failure has occurred in the relay function of the network 18 or another node. Note that the setting of the timeout time can be performed by setting parameters from the CPU 11a.

As described above, according to the eleventh embodiment, the circulation timer unit 110a that outputs a failure occurrence to the RAS unit 14a when a predetermined time has elapsed, and the circulation timer 110a is reset when transmitting a packet. Loop timer reset unit 111a, and a round timer clear unit 112a that clears round timer unit 110a when receiving the packet.
Thus, it is possible to detect a failure such as a network failure that prevents the packet from being circulated, and avoid the spread of the failure.

Embodiment 12 FIG. FIG. 12 is a block diagram showing a distributed shared memory network device according to a twelfth embodiment of the present invention. In the figure, reference numeral 121a denotes a transmission buffer unit provided in a transfer control unit 16a for recording a packet transmitted from its own node. , 122a is a circulating packet detection unit that detects the coincidence between the node ID of the received packet and its own node ID, and 123a is recorded in the transmission buffer unit 121a when the circulating packet detection unit 122a detects a match. A circulating packet error detection unit 124a for comparing the contents of the packet and the received packet and detecting a transmission error due to circulating of the packet, and a transmission buffer unit 124a when the circulating packet error detection unit 123a detects a transmission error. It is a retransmission control unit that retransmits the packet recorded in 121a. The configurations of the b-node and the c-node are the same as those of the a-node, and the other configurations are the same as those of FIG.

Next, the operation will be described. The packet transmitted from the own node is recorded in the transmission buffer unit 121a. The circulating packet detection unit 122a checks whether the node ID of the received packet matches the own node ID,
It detects packets that it transmitted and circulated. The circulating packet error detection unit 123a compares the packet transmitted and circulated by itself with the contents of the packet recorded in the transmission buffer unit 121a, and rejects the packet as a normal wrap if they match. If they do not match, it is assumed that a transfer error has occurred on the network 18, and the retransmission control unit 124a retransmits the packet recorded in the transmission buffer unit 121a. Further, if the retransmitted packet circulates and causes an error again, the RAS unit 14a leaves the network as a card failure. Therefore, a new packet cannot be transmitted from the memory control unit 15a until the transmitted packet circulates and the error check ends.

As described above, according to the twelfth embodiment, the transmission buffer unit 121a for recording the packet transmitted from the own node, the node ID of the received packet,
Packet detector 122a for detecting a match between the packet and its own node ID, and, when a match is detected by the packet detector 122a, the contents of the packet recorded in the transmission buffer 121a and the contents of the received packet are And a retransmission packet error detecting unit 123a for detecting a transfer error due to repetition of the packet, and retransmitting the packet recorded in the transmission buffer unit 121a when the retransmission packet error detection unit 123a detects a transfer error. Since the retransmission control unit 124a is provided, a communication error during network relay can be corrected, and the reliability of the distributed shared memory can be improved.

Embodiment 13 FIG. FIG. 13 is a block diagram showing a distributed shared memory network device according to a thirteenth embodiment of the present invention. In the figure, reference numeral 131a denotes a FIFO provided in a transfer control unit 16a for recording a plurality of packets transmitted from its own node. It is a buffer unit. Also,
The circulating packet error detecting unit 123a, when a match is detected by the circulating packet detecting unit 122a,
The contents of the first packet recorded in the buffer unit 131a and the contents of the received packet are compared, and the retransmission control unit 124a
When the transfer error is not detected by the cyclic packet error detection unit 123a, the leading packet recorded in the FIFO buffer unit 131a is incremented by one, and when the transfer error is detected, the FIFO buffer unit It has a function of setting a retransmission bit for all packets recorded in 131a, retransmitting the packet, and rejecting the packet when a transmitted packet having no retransmission bit received is received. The configurations of the b-node and the c-node are the same as those of the a-node, and the other configurations are the same as those of FIG.

Next, the operation will be described. As compared with FIG. 12, the transmission buffer unit 121a is different from the FIFO buffer unit 1 in FIG.
At 31a, packets can be continuously transmitted until the FIFO queue is full. The circulating packet error detection unit 123a includes a circulating packet detection unit 122a.
When a match is detected, the received packet circulated is compared with the first packet recorded in the FIFO buffer unit 131a. If the comparisons match, retransmission control section 124a advances the leading packet by one. If they do not match, a retransmission bit is set for the packet currently circulating on the network 18, that is, all the packets recorded in the FIFO buffer unit 131a, and the packet is retransmitted. When retransmission starts, all packets circulated and received by the own node are discarded until the packet with the retransmission bit set circulates, and only the packet with the retransmission bit set is FI
This is compared with the first packet recorded in the FO buffer unit 131a. If all the retransmitted packets are error free, the retransmission has succeeded, and the process returns to the normal processing.
If an error is detected in the retransmitted packet, the RAS unit 14a leaves the node as a card failure.

As described above, according to the thirteenth embodiment, the FIFO buffer unit 131a for recording a plurality of packets transmitted from the own node is provided, and the retransmission control unit 124
When a transfer error is detected by the cyclic packet error detection unit 123a, retransmission bits are set for all packets recorded in the FIFO buffer unit 131a and retransmission is performed, and no transmitted retransmission bit is set. In the twelfth embodiment, since a packet cannot be transmitted until the packet circulates, a function of rejecting the packet when the packet is received is provided.
Transmission and error checking can be performed continuously until overflows. Therefore, the transmission efficiency of the node is greatly improved. Further, if the depth of the FIFO buffer unit 131a is set to be equal to or longer than the packet circulation time, the FIFO buffer unit 131
The overflow of a does not occur.

Embodiment 14 FIG. FIG. 14 is a block diagram showing a distributed shared memory network device according to Embodiment 14 of the present invention. In the figure, reference numeral 141a denotes a relay FIFO provided in a transfer control unit 16a for recording received packets until transmission becomes possible. The buffer unit 142a is a transmission priority control unit that gives priority to the transmission processing of the FIFO buffer unit 131a over the relay processing by the relay FIFO buffer unit 141a when the FIFO buffer unit 131a is full. The configurations of the b-node and the c-node are the same as those of the a-node, and the other configurations are the same as those of FIG.

Next, the operation will be described. The FIFO buffer unit 131a is provided for temporarily recording a packet transmitted from the own node in order to prioritize a relay process of a packet received from another node. However, the FIFO buffer unit 131a is used for error retransmission. When 131a is full, the transmission priority control unit 142a outputs a transmission request to the link control unit 17a with priority given to transmission of a packet from the FIFO buffer unit 131a over relay processing by the relay FIFO buffer unit 141a. When the FIFO buffer unit 131a becomes empty, the transmission priority control unit 14
2a returns to the relay processing by the relay FIFO buffer unit 141a again. That is, by temporarily giving priority to a node whose FIFO buffer unit 131a is full to transmission, the delay of a packet transmission request from the node is improved.

As described above, according to the fourteenth embodiment, when the FIFO buffer unit 131a is full,
Since the transmission priority control unit 142a that prioritizes the transmission processing of the FIFO buffer unit 131a over the relay processing by the relay FIFO buffer unit 141a is provided, the transfer of the specific node is stopped in a situation where the CPU access load of the RMU of the specific node is high. Can be alleviated.

Embodiment 15 FIG. FIG. 15 is a block diagram showing a distributed shared memory network device according to a fifteenth embodiment of the present invention. In the figure, reference numeral 151a is provided in the transfer control unit 16a, and transmits a packet from its own node by setting from the CPU 11a. This is a transmission suppression unit that stops. The configurations of the b-node and the c-node are the same as those of the a-node, and the other configurations are the same as those of FIG.

Next, the operation will be described. Transmission suppression unit 1
51a ignores the packet transmission request from the memory control unit 15a according to the setting from the CPU 11a. At this time,
The reception of the packet and the reflection of the received packet on the local memory unit 13a are performed in the same manner as in the first embodiment. Therefore, although the packet flowing through the network 18 is reflected in the local memory unit 13a, the packet cannot be transmitted from the own node. The setting from the CPU 11a to the transmission suppression unit 151a is performed in the control register (CS
R) or by sending a command to the memory control unit 15a.

As described above, according to the fifteenth embodiment, the transmission suppressing unit 151a for stopping the transmission of the packet from the own node according to the setting from the CPU 11a is provided. , Or the RMU can be equalized with the state of another node.

Embodiment 16 FIG. FIG. 16 is a block diagram showing a distributed shared memory network device according to Embodiment 16 of the present invention. In the figure, reference numeral 161a is provided in the memory control unit 15a, and a writable area of the local memory unit 13a is set by the CPU 11a. , CPU 11
If the store instruction from a is within the writable area, the data is written by the memory writing unit 162a, and if the store instruction is outside the writable area, no writing is performed. The configurations of the b-node and the c-node are the same as those of the a-node, and the other configurations are the same as those of FIG.

Next, the operation will be described. The writable area setting unit 161a sets an area in the local memory unit 13a in which the CPU 11a of its own node can write,
The setting is made from the PU 11a, and when there is a store instruction from the CPU 11a, the address is checked by the memory writing unit 162a, and if it is within the writable area, the data is written to the local memory unit 13a by the memory writing unit 162a. If it is outside the writable area, the store command is ignored, and neither writing to the local memory unit 13a nor transmission of a packet is performed.

The method for setting the writable area from the CPU 11a includes a method of designating the start and end addresses of the possible area, or a method of designating the start address and size. It is also possible to specify a plurality of address sets. The writable area can be set to be writable from a plurality of nodes. Further, when an access is made to the outside of the writable area, there is a method of notifying the CPU 11a of a write prohibition violation by interruption or notifying the CPU 11a by CSR.

As described above, according to the sixteenth embodiment, the writable area of the local memory unit 13a is set by the CPU 11a, and if the store instruction from the CPU 11a is within the writable area, the memory writing unit 162a
Since the writable area setting unit 161a that writes the data and does not perform writing if the data is outside the writable area is provided, the setting of the area of the writable local memory unit 13a can be changed for each node. Data change by a node other than the node can be prevented, and data protection becomes possible.

Embodiment 17 FIG. FIG. 17 is a block diagram showing a distributed shared memory network device according to a seventeenth embodiment of the present invention. Reference numeral 172a denotes a CRC decoding unit that decodes the received packet, and 173a denotes a packet error setting unit that checks an error of the packet received by the decoding by the CRC decoding unit 172a. The configurations of the b-node and the c-node are the same as those of the a-node, and the other configurations are the same as those of FIG.

Next, the operation will be described. Packets to be transmitted are CRC-encoded by the CRC encoding unit 171a, so that all packets transmitted and received
Encoded and transmitted to network 18. The received packet is decrypted by the CRC decryption unit 172a, and the packet ID is set by the packet error setting unit 173a.
Then, the number of relays and the like are checked. If an error is detected at the time of decoding and the packet is to be relayed, the packet error setting unit 173a sets an error bit in the attribute information included in the packet and transmits the packet. The packet with the error bit set cannot be reflected in the local memory unit at each node, and when the packet is collected as a circulated packet by the transmission source node,
An error will be retransmitted. Note that encoding and decoding may be performed using parity and ECC codes instead of CRC codes.
In particular, when a one-bit error can be automatically corrected such as two bits of ECC, the result of the automatic correction can be used for reflection in a memory and relay processing.

As described above, according to the seventeenth embodiment, CRC encoding section 171a for CRC encoding a packet to be transmitted, CRC decoding section 172a for decrypting a received packet, and CRC decoding section 172a And the packet error setting unit 173a for checking the error of the packet received by the decoding by the packet decoding unit.
The situation where the error packet is reflected in the memory of each node does not occur. If the error is limited, it can be automatically repaired.

Embodiment 18 FIG. FIG. 18 is a block diagram showing a distributed shared memory network device according to Embodiment 18 of the present invention. In the figure, 183a is provided in the memory control unit 15a, and sets a semaphore state of a node. A semaphore operation requesting unit that transmits a request, lock, free and abort packets related to a semaphore request in accordance with an instruction from the CPU 1a.
A semaphore management unit that sets the semaphore status unit 183a. The configurations of the b-node and the c-node are the same as those of the a-node, and the other configurations are the same as those of FIG.

Next, the operation will be described. CPU is RM
When processing a critical section of the local memory unit of U, exclusive control of the operation is performed using a network semaphore that can be locked only by this node on the network. In the eighteenth embodiment, this network semaphore is provided. In FIG. 18, the semaphore operation request unit 1
81a is a CSR write from the CPU 11a, or
The command sends a request, lock, free, and abort packets related to the semaphore request to the network 18 and issues an operation request for a network semaphore that can be locked only by a specific node on the network 18. The semaphore management unit 182a responds to a semaphore operation request from another node. The semaphore status unit 183a is composed of two types of registers, a request status A and a lock status B, which indicate the semaphore status of the node.

The state set in the semaphore state section 183a has a state transition shown in FIG. The free state is a state in which no request or lock has been applied to this node, the request state means that any node has made a request and is in a lock reservation state, and the locked state means that the semaphore is any node Is locked by

When the CPU 11a wants to lock the writing to the local memory units 13a to 13c,
U11a confirms the current setting of the semaphore status unit 183a, and if it is a request or a lock, it means that a lock request has been issued from another node, so that lock processing cannot be performed. If free, the semaphore operation request unit 181a transmits a request packet. In another b node, for example, the semaphore management unit 182b receives the request packet, and if the semaphore status unit 183b is not in the request status, the semaphore status unit 183b
b is set to the request state A. Semaphore status section 183b
Is in a request state, an error bit is set in the received packet and relayed.

In all nodes, semaphore state unit 1
When the node 83 is set to the request state A and a packet in which an error bit is not set is received at the a node, it is determined that the request request is satisfied, and the semaphore operation request unit 181a transmits a lock packet. In another node b, for example, the lock packet is received by the semaphore management unit 182b, and if the semaphore state unit 183b is in the request state A, the semaphore state unit 183b
To the locked state B. If the semaphore state unit 183b is not in the request state B, the received packet is set with an error bit and relayed.

In all nodes, the semaphore state unit 1
83 is set to the lock state B, and when a packet without an error bit set is received at the a-node,
It is determined that the lock request has been established. If the request fails, the semaphore operation request unit 181a transmits an abort packet, and the semaphore status unit 183a of another node.
After the request status A is cleared, a request failure is output to the CPU 11a. Further, if the lock request fails, the semaphore operation request unit 181a transmits a free packet, clears the request state A and the lock state B of the semaphore state unit 183a of another node, and outputs a lock failure to the CPU 11a. .

As described above, according to the eighteenth embodiment, the semaphore state unit 1 that sets the semaphore state of a node
83a, a semaphore operation requesting unit 181a for transmitting a request, lock, free and abort packet related to a semaphore request in accordance with an instruction from the CPU 1a; State part 183
Since the semaphore management unit 182a for setting a is provided, the exclusive control operation of the distributed system can be performed by a packet.

Embodiment 19 FIG. FIG. 19 is a block diagram showing a distributed shared memory network device according to a nineteenth embodiment of the present invention. In the figure, reference numeral 191a is provided in the link control unit 17a, and directly receives a packet according to an instruction from the RAS unit 14a. This is a bypass unit that bypasses to another node. The configuration of b node and c node is a
The configuration is the same as that of the node, and the other configuration is the same as that of FIG.

Next, the operation will be described. Bypass unit 1
Reference numeral 91a denotes a ring bypass circuit that switches whether the transfer control unit 16a can receive and transmit data from the network 18 or disconnects the network 18 from the transfer control unit 16a and bypasses it. By operating the bypass unit 191a in the link control unit 17a according to the instruction of the RAS unit 14a, the node can be controlled to leave the network. In particular, in the event of a node failure or a power failure, the network is voluntarily disconnected from the network in accordance with an instruction from the CPU 11a or an instruction from the RAS unit 14a. When the power is turned on, the bypass unit 191a is in the bypass state, and the bypass is released and the transmission / reception is not enabled unless the entry procedure is taken.

As described above, according to the nineteenth embodiment, the bypass unit 191a for directly bypassing the received packet to another node is provided according to the instruction of the RAS unit 14a, so that a failure such as a node failure or a power cut-off may occur. At the time, the RAS unit 1
By voluntarily leaving the network according to the instruction of 4a, it is possible to prevent the spread from the node failure to the network failure.

Embodiment 20 FIG. FIG. 20 is a block diagram showing a distributed shared memory network device according to a twentieth embodiment of the present invention. In the figure, 201a is connected between the distributed shared memory unit 12a and the network 18 and directly receives packets. A bypass box 202a for bypassing to the node is a manual switch for manually switching the bypass box 201a. The configurations of the b-node and the c-node are the same as those of the a-node, and the other configurations are the same as those of FIG.

Next, the operation will be described. The bypass box 201a is a circuit equivalent to the bypass 191a in FIG. 19, and is operated by operating the manual switch 202a.
The network 18 can be switched to a connection to a node or a bypass. The bypass unit 191a shown in FIG. 19 automatically bypasses the network 18 due to power failure or node failure, thereby avoiding link disconnection and maintaining a distributed shared memory network of another node. It was a switch.
However, it is necessary to replace the RMU in the event of an RMU failure, and there is a problem that the network 18 is disconnected even when the network 18 is disconnected from the RMU even in the bypass mode. The bypass box 201a according to the twentieth embodiment shown in FIG. 20 is provided outside the RMU in order to enable replacement of the RMU. Therefore, the operation of the manual switch 202a causes the bypass box 2
Since the network 18 can be bypassed inside 01a, the network 18 is maintained even if the cable on the RMU side is disconnected.

As described above, according to the twentieth embodiment, the distributed shared memory unit 12a and the network 18
And a manual switch unit 202a for manually switching the bypass box 201a, which is connected between the network and the other nodes, so as to maintain a distributed shared memory network. However, it is possible to exchange the RMU of a certain node. In addition, the bypass box 20
By giving the cable media conversion and repeater functions to 1a, the effect of extending the cable and converting different cable media (light and electric wires, etc.) can be provided.

Embodiment 21 FIG. FIG. 21 is a block diagram showing a distributed shared memory network device according to Embodiment 21 of the present invention. In the figure, reference numeral 212a denotes a bypass switch unit that switches the bypass box unit 201a according to an instruction from the RAS unit 14a. The configurations of the b-node and the c-node are the same as those of the a-node, and the other configurations are the same as those of FIG.

Next, the operation will be described. RAS unit 14
According to the instruction of a, the bypass switch unit 212a switches the bypass box unit 201a to enable reception and transmission of the MRU 12a and the network 18,
It controls whether the MRU 12a and the network 18 are separated and bypassed.

As described above, according to the twenty-first embodiment, the bypass switch section 212a for switching the bypass box section 201a according to the instruction of the RAS section 14a is provided.
However, in the twenty-first embodiment, the effect of the nineteenth embodiment and the mobile phone 20 of the embodiment can be obtained without the need for the manual switch unit 202a.

Embodiment 22 FIG. FIG. 22 is a block diagram showing a distributed shared memory network device according to Embodiment 22 of the present invention. In the figure, an equalizing packet 224a is provided in the memory control unit 15a and transmits an equalizing request packet in accordance with an instruction from the CPU 11a. When the received packet is an equalizing request packet, the transmitting unit 222a causes the memory cycle reading unit 223a to read data in the writable area of the local memory unit 13a at a specified cycle and to read the read data. The equalizing control unit transmits the received packet of the equalizing request while transmitting the packet as a packet. The configurations of the b-node and the c-node are the same as those of the a-node, and the other configurations are the same as those of FIG.

Next, the operation will be described. Embodiment 1
Since the local memory unit 13a of the new entry node does not match the local memory units 13b and 13c of other nodes, it is necessary to perform a memory equalization process called equalizing. Equalizing packet transmission unit 22
4a transmits an equalizing request packet to the network 18 according to an instruction from the CPU 11a. When the equalizing request packet is received by, for example, the equalizing control unit 222b of the b-node, the local memory unit 13b is designated by the memory cycle reading unit 223b at the designated cycle.
In the writable area, and transmits the read data as a packet via the equalizing packet transmitting unit 224b.

The transmission of the packet is basically every word length. However, if the number of nodes is large, there is a fear that the communication band is used up for transmission and relay of the packet. Therefore, the memory cycle reading unit 223b transmits the data in a designated cycle set in advance as data in a range in which the band is not used up. When transmission of this packet ends,
The packet of the equalizing request is transmitted to a neighboring node, for example,
Send to node c. Similarly, the node c transmits the packet of the data in the writable area of the local memory unit 13c and the packet of the equalizing request to the node a. Then, when the equalizing request packet is received by the equalizing control unit 222a, it is determined that the equalizing process is completed. Therefore, the packet of the equalizing request is not transmitted to the next node unless the packet of the data in the writable area is transmitted in each node, so that it takes a considerable time to complete the equalizing process of all the nodes. In addition, it is necessary to set the time-out period of the packet of the equalizing request much longer than the normal time-out period.

As described above, according to the twenty-second embodiment, equalizing packet transmitting section 2 for transmitting an equalizing request packet in response to an instruction from CPU 11a.
24a and when the equalizing request packet is received, the memory cycle reading unit 223a causes the data in the writable area of the local memory unit 13a to be read at a specified cycle and transmits the read data as a packet. Since the equalizing control unit 222a that transmits the received packet of the equalizing request is provided, the local memory unit 13a of the newly joining node can be matched with the local memory units 13b and 13c of the other nodes. That is, a memory equalization process called equalization can be performed.

Embodiment 23 FIG. FIG. 23 is a block diagram showing a distributed shared memory network device according to Embodiment 23 of the present invention. In the figure, when an equalizing control unit 222a receives an equalizing request packet, the equalizing request packet And an equalizing start packet are transmitted, and the data in the writable area of the local memory unit 13a is read by the memory cycle reading unit 223a at a specified cycle,
The read data is transmitted as a packet, and a packet after the end of equalizing is transmitted. An equalizing status recording unit 235a manages the status of the equalizing operation by receiving the equalizing start packet and the equalizing end packet. The configurations of the b-node and the c-node are the same as those of the a-node, and the other configurations are the same as those of FIG.

Next, the operation will be described. Embodiment 2
In 2, the equalizing request packet is sequentially transmitted to each node. In the twenty-third embodiment, the equalizing request packet is transmitted to all the nodes almost simultaneously. The equalizing packet transmitting unit 224a
In accordance with an instruction from the CPU 11a, an equalizing request packet is transmitted to the network 18. When the equalizing request packet is received by, for example, the equalizing control unit 222b of the b node, the equalizing request packet and the equalizing start packet including the own node ID are transmitted to the network 18 immediately. Further, the data in the writable area of the local memory unit 13b is read at a designated cycle by the memory cycle reading unit 223b, and the equalizing packet transmitting unit 224 is read.
b, and transmits the read data as a packet. Further, when the transmission of this packet is completed, an equalizing end packet including the own node ID is transmitted.

At the node a, which is the source of the equalizing request packet, the equalizing status recording unit 235a
Thus, an equalizing start packet and an equalizing end packet that have circulated around the network 18 are received, and the state of the equalizing operation is managed by the node ID. Equalizing status recording unit 23
If it is confirmed that all equalizing operations have been completed by 5a, it is determined that the equalizing operation has been completed.
Notify the PU 11a.

As described above, according to the twenty-third embodiment, when an equalizing request packet is received,
The received equalizing request packet and equalizing start packet are transmitted, and the memory cycle reading unit 223a sends the packet to the local memory unit 13 at a specified cycle.
a equalizing control unit 222a for reading the data in the writable area a, transmitting the read data as a packet, and transmitting an equalizing end packet, and receiving the equalizing start packet and the equalizing end packet Since the equalizing status recording unit 235a that manages the status of the equalizing operation is provided, all nodes can perform the equalizing operation all at once, and much of the bandwidth of the network 18 is occupied by the equalizing. The equalizing process can be completed earlier than in the twenty-second embodiment. Further, it is possible to automatically manage which node is currently equalizing and which node has ended based on the node ID, and perform node management of the distributed shared memory and fault management during equalizing.

Embodiment 24 FIG. FIG. 24 is a block diagram showing a distributed shared memory network device according to Embodiment 24 of the present invention. In the figure, reference numeral 243a is provided in the transfer control unit 16a and transmits a participation notification packet including its own node ID when the participation is successful. The entry requesting unit 244a is an entry recording unit that, when receiving an entry notification packet, extracts a node ID from the packet and records it.
The configurations of the b-node and the c-node are the same as those of the a-node, and the other configurations are the same as those of FIG.

Next, the operation will be described. Embodiment 7
In, when the entry is successful, the entry requesting unit 243a transmits an entry notification packet including the own node ID to the network. When the entry notification packet is received by, for example, the node ID determination unit 61b of the b node, the node ID is extracted from the packet and recorded in the entry recording unit 244b. The entry notification packet is an error packet or a packet defined for exclusive use.
4b, and is not reflected on the local memory unit 13.

As described above, according to the twenty-fourth embodiment, the entry requesting unit 243a for transmitting the entry notification packet including the own node ID when the entry is successful, and when the entry notification packet is received, And an entry recording unit 244a that extracts and records the node ID from
Since new entry node IDs can be recorded sequentially,
It is possible to know the node IDs that have entered after this node. In particular, when the ID recording memory is insufficient, there is also a method of recording only the number of participants in the entry recording unit 244a.
However, when the distributed shared memory network operates in the retransmission mode, the retransmission causes an error in the unit number record.

[0117]

As described above, according to the first aspect of the present invention, the state of the distributed shared memory unit is diagnosed and monitored, and in the event of a failure including power interruption, a packet received by the link control unit is directly transmitted to another node. Since the RAS unit is configured to be bypassed, the CPU can copy and share data without being conscious of communication. Further, since the network ring can be maintained even if a node fails or power is cut off, other The effect is that the node can use the distributed shared memory unit independently.

According to the second aspect of the present invention, the memory control unit has a CPU access type setting unit in which the endian type of the CPU is set, and a load or store instruction from the CPU in the endian type set in the CPU access type setting unit. Since the configuration includes the CPU access conversion unit that converts the type into the type and accesses the local memory unit, there is an effect that a distributed shared memory unit in which different types of CPUs are mixed can be configured.

According to the third aspect of the present invention, the memory control unit includes: a memory reading unit that reads data in the local memory unit in accordance with a designated address in a store instruction from the CPU; A memory write command comparing unit for comparing data read by the memory reading unit; and a local memory unit when the write data and the read data are different from each other by the memory write command comparing unit. Is configured to include a memory writing unit that writes write data to the specified address, so that meaningless data is not transmitted to be reflected in the local memory unit, and there is an effect that the communication band can be used efficiently.

According to the fourth aspect of the present invention, the memory control unit stores the block reception control unit for receiving the burst transfer or the DMA transfer in the store instruction from the CPU and the block data received by the block reception control unit. A block writing unit for writing to the local memory unit, wherein the transfer control unit generates a block packet including the block data received by the block reception control unit, and transmits the block packet received via the link control unit to the memory control unit. Block transmission / reception unit for outputting to the distributed shared memory unit, the block transfer from the CPU can be directly reflected in the distributed shared memory unit. It has the effect of speeding up transfer and saving bandwidth

According to the fifth aspect of the present invention, an interrupt condition setting unit in which an interrupt generation condition is set in advance by the CPU, a received packet and an interrupt generation set in the interrupt condition setting unit are set in the memory control unit. An interrupt condition judging unit that collates a condition and judges occurrence of an interrupt;
When an interrupt condition is determined by the interrupt condition determining unit, the CPU is configured to include an interrupt control unit that notifies the CPU of an interrupt, so that event notification and interrupt notification between nodes can be performed using the distributed shared memory unit. There is an effect.

According to the invention of claim 6, the transfer control unit includes a network entry control unit to which a node ID is set when newly joining a network, and a node ID set to the network entry control unit. A network entry request unit that generates an entry packet and outputs the packet to the transfer control unit; and a received packet if the received packet is an entry packet and the node ID included in the entry packet matches the own node ID. And an error bit is added to the output to the transfer control unit, and when the own node receives an entry packet that matches the own node ID during a new entry request and has no error bit added, the own node can enter. Each node has a unique ID and is newly added to the network. There is an effect that can be entered.

According to the seventh aspect of the present invention, the node ID is output to the transfer control unit from the initial value to the network entry control unit. Is configured to include a node ID automatic setting unit that outputs to the network entry control unit by increasing the number of nodes, so that there is an effect that a node ID to newly enter the distributed shared memory network device can be automatically given.

According to the eighth aspect of the present invention, when the transfer control unit fails in entry, the RAS unit displays the entry failure on the entry failure display unit and directly transmits the packet received by the link control unit to another unit. Since the configuration is such that the node is bypassed, there is an effect that the network can be immediately excluded when the network entry fails, and the failure can be notified to the outside.

According to the ninth aspect of the present invention, the transfer control unit includes a relay counter unit for increasing the number of relays included in a received packet for each relay of the received packet, and the number of relays exceeding a predetermined number. Since the apparatus is provided with the long-lived packet processing unit that discards packets, it is possible to detect and exclude packets circulating infinitely, losing nodes to be collected.

According to the tenth aspect of the present invention, the transfer control unit includes a maximum node ID detection unit for detecting the maximum value of the node ID of the received packet, and a node ID detected by the maximum node ID detection unit. Is recorded, and the longest-lived packet processing unit is provided with a maximum node ID recording unit that is set as a predetermined number of times. Therefore, there is an effect that the life of a packet to be excluded can be automatically set on the network side. .

According to the eleventh aspect of the present invention, the transfer control unit includes a circulation timer unit that outputs a failure occurrence to the RAS unit when a predetermined time has elapsed, and a circulation timer unit that resets the circulation timer unit when transmitting a packet. Since the configuration includes the timer reset unit and the round timer clear unit that clears the round timer unit when the packet is received, there is an effect that packet loss due to network disconnection or the like can be detected.

According to the twelfth aspect of the present invention, the transfer control unit records the packet transmitted from the own node, and detects whether the node ID of the received packet matches the own node ID. When a match is detected by the circulating packet detector and the circulating packet detector,
A packet error detector that compares the contents of the packet recorded in the transmission buffer and the received packet and detects a transfer error due to the packet circulation; and a transfer error detected by the packet error detector. To
It is configured to include a retransmission control unit that retransmits the packet recorded in the transmission buffer unit, so that a transmission error due to packet rounding is detected, and when a transmission error is detected, the packet is retransmitted. This has the effect of improving communication reliability.

According to the thirteenth aspect of the present invention, the transfer control unit includes a FIFO buffer unit for recording a plurality of packets transmitted from the own node, and a FIFO buffer unit for detecting the coincidence by the circulating packet detection unit. A packet error detection unit that compares the contents of the first packet recorded in the packet with the received packet and detects a transfer error due to the packet circulation, and when no packet transfer error is detected by the packet error detection unit Next, the first packet recorded in the FIFO buffer is moved up by one, and if a transfer error is detected, all packets recorded in the FIFO buffer are set with retransmission bits and retransmitted. A retransmission control unit that rejects a packet when a packet with no retransmission bit set is received Since form was, while maintaining high reliability, since it becomes possible continuous packet transmission, there is an effect capable of improving communication throughput.

According to the fourteenth aspect of the present invention, a relay FIFO buffer unit for recording received packets until transmission is possible, and when the FIFO buffer unit is full,
The FI rather than the relay processing by the relay FIFO buffer
The transmission priority control unit that prioritizes the transmission processing of the FO buffer unit is provided, so that a node frequently accessed from the CPU or a node in which retransmission has occurred is temporarily set to transmission priority. There is an effect that the overflow of the transmission packet of the node can be suppressed.

According to the fifteenth aspect of the present invention, the transfer control unit is provided with the transmission suppressing unit for stopping the transmission of the packet from the own node according to the setting from the CPU. Since it can be set to perform but not transmit, there is an effect that a test and a memory equalizing that should not affect other nodes can be performed safely.

According to the sixteenth aspect of the present invention, the writable area of the local memory section is set by the CPU in the memory control section, and if a store instruction from the CPU is within the writable area, the memory writing section Since the data is written to the local memory unit and a writable area setting unit that does not perform writing outside the writable area is provided, it is possible to prevent unauthorized writing to the local memory unit due to a program error or the like. There is an effect that can be done.

According to the seventeenth aspect of the present invention, the transfer control unit includes a CRC encoding unit for performing CRC encoding on a packet to be transmitted, a CRC decrypting unit for decrypting the received CRC encoded packet, A packet error setting unit that checks an error of a packet received by decryption by the CRC decryption unit is provided, so that packet communication errors are not reflected in the memory of each node, so that communication and the distributed shared memory unit have high reliability. There is an effect that enables.

According to the eighteenth aspect of the present invention, the semaphore status unit for setting the semaphore status of the node and the semaphore operation request unit for transmitting a request and lock packet relating to the semaphore request in accordance with an instruction from the CPU in the transfer control unit If the received packet has a semaphore request for the request, set the semaphore state part to the request, and if the received packet has a semaphore request for the lock, confirm that the semaphore state part is the request. And a semaphore management unit that sets the semaphore state unit to a lock, so that it is possible to guarantee that only one node can be locked on the distributed shared memory unit, so that exclusive control processing of the distributed system becomes possible. There is.

According to the nineteenth aspect of the present invention, since the link control unit is provided with the bypass unit for directly bypassing the packet received by the instruction of the RAS unit to another node, the power supply of a certain node can be cut off. By autonomously excluding the network when a failure occurs, there is an effect that the operation of the distributed shared memory of another node can be maintained.

According to the twentieth aspect, the bypass box is connected between the distributed shared memory unit and the network and bypasses the received packet directly to another node, and the bypass box is manually switched. Since the configuration includes the manual switch unit, there is an effect that the distributed shared memory unit of the node can be replaced while maintaining the network ring of the distributed shared memory.

According to the twenty-first aspect of the present invention, a bypass box unit connected between a distributed shared memory unit and a network and directly bypassing a received packet to another node, and the bypass box unit serving as a RAS unit Since the apparatus is configured to include the bypass switch unit that switches according to an instruction, each apparatus according to the nineteenth and twentieth aspects can be integrated into one apparatus, so that there is an effect that cost can be reduced.

According to the twenty-second aspect of the present invention, an equalizing packet transmitting section for transmitting an equalizing request packet to the memory control section in accordance with an instruction from the CPU;
When the received packet is a packet for the equalizing request, the memory period reading unit causes the data in the writable area of the local memory unit to be read at a specified period and transmits the read data as a packet. Since it is configured to include an equalizing control unit that transmits a received packet of the equalizing request, a certain participating node issues a request, so that the local memory unit can be equalized, and the requesting node can be replaced by another node. There is an effect that it can be matched with the local memory unit.

According to the twenty-third aspect of the present invention, an equalizing packet transmitting unit for transmitting an equalizing request packet to the memory control unit according to an instruction from the CPU;
If the received packet is an equalizing request packet, the received equalizing request packet and equalizing start packet are transmitted, and the memory cycle reading unit reads data in the writable area of the local memory unit at a specified cycle. And an equalizing control unit that transmits the read data as a packet, and transmits an equalizing end packet, and an equalizing state that manages an equalizing operation state by receiving the equalizing start packet and the equalizing end packet. With the configuration including the recording unit, the equalization processing of the invention according to claim 22 can be performed in a short time, and the completion status of the equalization processing of each node can be grasped on the request side. is there.

According to the twenty-fourth aspect of the present invention, an entry requesting unit for transmitting an entry notification packet including its own node ID to the transfer control unit when the entry is successful, and when receiving the entry notification packet, And an entry recording unit that extracts and records the node ID from
It is possible to detect a new entry node ID and read out the entry status by the CPU, thereby giving an effect of instructing processes such as configuration management and equalizing.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a distributed shared memory network device according to Embodiment 1 of the present invention.

FIG. 2 is a block diagram showing a distributed shared memory network device according to a second embodiment of the present invention.

FIG. 3 is a block diagram showing a distributed shared memory network device according to Embodiment 3 of the present invention.

FIG. 4 is a block diagram showing a distributed shared memory network device according to a fourth embodiment of the present invention.

FIG. 5 is a block diagram showing a distributed shared memory network device according to a fifth embodiment of the present invention.

FIG. 6 is a block diagram showing a distributed shared memory network device according to Embodiment 6 of the present invention.

FIG. 7 is a block diagram showing a distributed shared memory network device according to a seventh embodiment of the present invention.

FIG. 8 is a block diagram showing a distributed shared memory network device according to an eighth embodiment of the present invention.

FIG. 9 is a block diagram showing a distributed shared memory network device according to Embodiment 9 of the present invention.

FIG. 10 is a block diagram showing a distributed shared memory network device according to Embodiment 10 of the present invention.

FIG. 11 is a block diagram showing a distributed shared memory network device according to Embodiment 11 of the present invention.

FIG. 12 is a block diagram showing a distributed shared memory network device according to Embodiment 12 of the present invention.

FIG. 13 is a block diagram showing a distributed shared memory network device according to Embodiment 13 of the present invention.

FIG. 14 is a block diagram showing a distributed shared memory network device according to Embodiment 14 of the present invention.

FIG. 15 is a block diagram showing a distributed shared memory network device according to Embodiment 15 of the present invention.

FIG. 16 is a block diagram showing a distributed shared memory network device according to Embodiment 16 of the present invention.

FIG. 17 is a block diagram showing a distributed shared memory network device according to Embodiment 17 of the present invention.

FIG. 18 is a block diagram showing a distributed shared memory network device according to Embodiment 18 of the present invention.

FIG. 19 is a block diagram showing a distributed shared memory network device according to Embodiment 19 of the present invention.

FIG. 20 is a block diagram showing a distributed shared memory network device according to Embodiment 20 of the present invention.

FIG. 21 is a block diagram showing a distributed shared memory network device according to Embodiment 21 of the present invention.

FIG. 22 is a block diagram showing a distributed shared memory network device according to Embodiment 22 of the present invention.

FIG. 23 is a block diagram showing a distributed shared memory network device according to Embodiment 23 of the present invention.

FIG. 24 is a block diagram showing a distributed shared memory network device according to Embodiment 24 of the present invention.

FIG. 25 is an explanatory diagram showing a packet structure according to the first embodiment of the present invention.

FIG. 26 is an explanatory diagram showing a packet structure according to Embodiment 9 of the present invention.

FIG. 27 is an explanatory diagram showing a state transition of a semaphore state unit according to Embodiment 18 of the present invention.

FIG. 28 is a block diagram showing a conventional distributed shared memory network device.

FIG. 29 is an explanatory diagram showing how memory information circulates between nodes in data units.

[Explanation of symbols]

11a to 11c CPU, 12a to 12c Distributed shared memory unit (RMU), 13a to 13c Local memory unit, 14a to 14c RAS unit, 15a to 15c
Memory controller, 16a-16c Transfer controller, 17a-
17c link control unit, 18 network, 21a
CPU access type setting unit, 22a CPU access conversion unit, 31a memory read unit, 32a, 162a
Memory write unit, 33a memory write instruction comparison unit, 4
1a Block reception control unit, 42a Block writing unit, 43a Block packet transmission / reception unit, 51a Interrupt condition determination unit, 52a Interrupt control unit, 53a Interrupt condition setting unit, 61a Node ID determination unit, 62a
Network entry control unit, 63a network entry requesting unit, 74a node ID automatic setting unit, 81a entry failure display unit, 91a relay counter unit, 92a longevity packet processing unit, 101a maximum node ID detection unit, 102a
Maximum node ID recording unit, 110a circulation timer unit, 1
11a circulation timer reset unit, 112a circulation timer clear unit, 121a transmission buffer unit, 122a circulation packet detection unit, 123a circulation packet error detection unit,
124a retransmission control section, 131a FIFO buffer section, 141a relay FIFO buffer section, 142a transmission priority control section, 151a transmission suppression section, 161a writable area setting section, 171a CRC encoding section, 172
a CRC decoding unit, 173a packet error setting unit,
181a semaphore operation request unit, 182a semaphore management unit, 183a semaphore status unit, 191a bypass unit, 201a bypass box unit, 202a manual switch unit, 212a bypass switch unit, 222a
Equalizing control unit, 223a Memory cycle reading unit, 224a Equalizing packet transmission unit, 235
a Equalizing status recording unit, 243a entry requesting unit, 244a entry recording unit.

Claims (24)

[Claims] 1. A network in which a plurality of CPUs are connected by a slotted ring via respective distributed shared memory units, wherein each of the distributed shared memory units has a local memory unit accessed by the CPU and A memory control unit that accesses the local memory unit in response to a load or store instruction from the CPU, and accesses the local memory unit in response to a received packet; Transfer control unit that generates a packet including a node ID, an attribute, an address, and data, and decodes an attribute included in the received packet and outputs the received packet to the memory control unit when the packet is a valid packet. And transmit the packet generated by the transfer control unit to the above network Receive the packet from the network, and if the node ID included in the received packet is the own node, reject the received packet; otherwise, output the received packet to the transfer control unit. And a RAS unit for diagnosing and monitoring the state of the distributed shared memory unit and for bypassing a packet received by the link control unit to another node in the event of a failure including power-off. Distributed shared memory network device. 2. A memory control unit comprising: a CPU access type setting unit in which an endian type of a CPU is set; and a load or store instruction from the CPU converted to an endian type set in the CPU access type setting unit for localization. 2. The distributed shared memory network device according to claim 1, further comprising a CPU access conversion unit for accessing the memory unit. 3. A memory control unit comprising: a memory read unit that reads data in a local memory unit corresponding to a designated address in a store command from the CPU; a memory read unit that reads data written in a store command from the CPU; A memory write command comparing unit that compares the read data with the specified data. When the write data and the read data are determined to be different from each other, the memory write command comparator writes the data to the specified address of the local memory unit. 3. The distributed shared memory network device according to claim 1, further comprising a memory writing unit that writes data. 4. A block control unit for receiving a burst transfer or a DMA transfer in a store command from a CPU, and a block writing unit for writing block data received by the block reception control unit to a local memory unit. The transfer control unit generates a block packet including the block data received by the block reception control unit, and outputs the block packet received via the link control unit to the memory control unit. 2. The distributed shared memory network device according to claim 1, further comprising a unit. 5. The memory control unit compares an interrupt condition setting unit in which an interrupt generation condition is set in advance by a CPU with a received packet and an interrupt generation condition set in the interrupt condition setting unit, and generates an interrupt. 2. The distributed shared memory according to claim 1, further comprising: an interrupt condition judging unit for judging the interrupt condition; and an interrupt control unit for notifying the CPU of an interrupt when the interrupt condition judging unit judges the occurrence of the interrupt. Network device. 6. The transfer control unit generates a network entry control unit to which a node ID is set when newly joining a network, and an entry packet including the node ID set in the network entry control unit. And a network entry request unit that outputs an error bit to the received packet if the node ID included in the received packet matches the own node ID when the received packet is the entry packet. Output to the transfer control unit, and when the own node
And a node ID determining unit that determines that the own node can enter when receiving an entry packet to which the error packet has been added and to which an error bit has not been added.
A distributed shared memory network device as described. 7. The transfer control unit outputs a node ID to the network entry control unit starting from an initial value, and increases the node ID every time entry failure determined by the node ID determination unit increases, thereby controlling the network entry control. 7. The distributed shared memory network device according to claim 6, further comprising a node ID automatic setting unit for outputting to the unit. 8. The RAS unit, when the transfer control unit fails to join, displays the entry failure on the entry failure display unit and bypasses the packet received by the link control unit directly to another node. The distributed shared memory network device according to claim 6 or 7, wherein 9. A relay control unit for increasing the number of relays included in a received packet for each relay of a received packet, and a long-lived packet processing unit for rejecting a packet whose number of relays exceeds a predetermined number. 7. The distributed shared memory network device according to claim 6, comprising: 10. The transfer control unit records a maximum node ID detection unit that detects a maximum value of a node ID of a received packet, and records a maximum value of a node ID detected by the maximum node ID detection unit, and records a longevity. 10. The distributed shared memory network device according to claim 9, further comprising a maximum node ID recording unit that is set as a predetermined number of times in the packet processing unit. 11. A transfer timer unit for outputting a fault occurrence to the RAS unit when a predetermined time has elapsed,
2. The distributed shared memory according to claim 1, further comprising: a round timer reset unit that resets the round timer unit when transmitting a packet; and a round timer clear unit that clears the round timer unit when receiving the packet. Network device. 12. A transfer control unit, comprising: a transmission buffer unit for recording a packet transmitted from the own node; a circulating packet detecting unit for detecting a match between a node ID of the received packet and the own node ID; When a match is detected by the packet detection unit, the contents of the packet recorded in the transmission buffer unit and the received packet are compared,
A recirculation packet error detection unit that detects a transmission error due to recirculation of a packet, and a retransmission control unit that retransmits the packet recorded in the transmission buffer unit when a transmission error is detected by the recirculation packet error detection unit. The distributed shared memory network device according to claim 1, further comprising: 13. A transfer control unit, comprising: a FIFO buffer unit for recording a plurality of packets transmitted from the own node; and a first packet recorded in the FIFO buffer unit when a coincidence is detected by the cyclic packet detection unit. And a content of the received packet, and a cyclic packet error detecting unit for detecting a transfer error due to the cyclic of the packet. If the cyclic packet error detecting unit does not detect the transfer error, the The recorded first packet is moved up by one, and if a transfer error is detected, all packets recorded in the FIFO buffer are set with retransmission bits and retransmitted, and the transmitted retransmission bit is set. 13. A retransmission control unit for rejecting an unacceptable packet when the packet is received. A distributed shared memory network device as described. 14. A relay FIFO buffer unit for recording a received packet until transmission becomes possible, and when the FIFO buffer unit is full, transmission processing of the FIFO buffer unit is performed more than relay processing by the relay FIFO buffer unit. 14. The distributed shared memory network device according to claim 13, further comprising a transmission priority control unit for giving priority to the transmission. 15. The distributed shared memory network device according to claim 1, wherein the transfer control unit includes a transmission suppressing unit that stops transmission of a packet from the own node according to a setting from the CPU. 16. A memory control section, wherein a writable area of a local memory section is set from the CPU, and if a store instruction from the CPU is within the writable area, the data is stored in the local memory section by the memory writing section. 2. The distributed shared memory network device according to claim 1, further comprising a writable area setting unit that does not perform writing if it is outside the writable area. 17. The transfer control unit transmits a packet to be transmitted to C
A CRC encoding unit for RC encoding, a CRC decryption unit for decrypting the received CRC encoded packet,
2. The distributed shared memory network device according to claim 1, further comprising: a packet error setting unit that checks an error of a packet received by decoding by the RC decoding unit. 18. A transfer control unit, comprising: a semaphore state unit for setting a semaphore state of a node; a semaphore operation request unit for transmitting a request and lock packet relating to a semaphore request according to an instruction from the CPU; If there is a semaphore request, set the semaphore state part to the request, and if there is a lock semaphore request in the received packet, confirm that the semaphore state part is a request and lock the semaphore state part. 2. The distributed shared memory network device according to claim 1, further comprising: a semaphore management unit that sets the semaphore. 19. The distributed shared memory network device according to claim 1, wherein the link control unit includes a bypass unit that directly bypasses a packet received according to an instruction of the RAS unit to another node. 20. A power supply system comprising: a bypass box connected between a distributed shared memory unit and a network, for bypassing a received packet directly to another node; and a manual switch for manually switching the bypass box. The distributed shared memory network device according to claim 1, wherein: 21. A bypass box unit connected between the distributed shared memory unit and the network, for bypassing a received packet directly to another node, and a bypass switch unit for switching the bypass box unit according to an instruction of the RAS unit. The distributed shared memory network device according to claim 1, further comprising: 22. An equalizing packet transmitting unit for transmitting an equalizing request packet in accordance with an instruction from the CPU, and, when the received packet is an equalizing request packet, by a memory period reading unit at a designated period. An equalizing control unit for reading data in the writable area of the local memory unit, transmitting the read data as a packet, and transmitting the received packet of the equalizing request. The distributed shared memory network device according to claim 1. 23. An equalizing packet transmitting unit for transmitting an equalizing request packet in accordance with an instruction from the CPU, and when the received packet is an equalizing request packet, the memory controlling unit transmits the equalizing request packet. And a packet for starting the equalizing is transmitted, and the data in the writable area of the local memory unit is read out at a specified period by the memory period reading unit, and the read data is transmitted as a packet and a packet for ending the equalizing is transmitted. 2. An equalizing control unit which performs the equalizing operation, and an equalizing state recording unit which manages an equalizing operation state by receiving the equalizing start packet and the equalizing end packet.
A distributed shared memory network device as described. 24. A transfer control unit for transmitting a join notification packet including its own node ID when the join is successful, and when receiving the join notification packet, extracts and records the node ID from the packet. The distributed shared memory network device according to claim 7, further comprising an entry recording unit.