JPH10275813A - Field effect transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a compound semiconductor field effect transistor(FET), which is constituted to exhibit stable characteristics by suppressing the secular change of the characteristics of the transistor, caused particularly by the interfacial level. SOLUTION: In a field effect transistor, in which a channel layer 3 containing an impurity at a high concentration, a cap layer 4, a semiconductor surface protective layer 5, and a surface protective layer 6 are successively formed on a semiconductor substrate 1, at least the parts of the cap layer 4 which are in contact with the semiconductor surface protective layer 5 are constituted of undoped layers, and the layer 5 is constituted of an undoped layer formed of a material having a wider bandgap than the material forming the cap layer 4 has.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor (FET) using a compound semiconductor as a material, and in particular, proposes a structure which suppresses a temporal change in transistor characteristics due to an interface state and realizes stable characteristics. I do.

[0002]

2. Description of the Related Art As a conventional FET having such a purpose, as shown in FIG. 5, after a channel layer 3 is formed by a method such as epitaxial growth or ion implantation, a Schottky gate electrode 11 is formed. For the purpose of increasing the barrier, a cap layer 4 containing no carrier is formed on the surface, and an ohmic electrode 12 composed of a gate electrode 11, a source electrode and a drain electrode is formed in contact with the cap layer. There is a type that covers the surface protective film 6.

Further, among conventional FETs having the same purpose, there is a conventional FET having a double highly doped layer (Japanese Patent Laid-Open No. 4-225533). An important characteristic of the FET is the transconductance (g) indicating the correlation between the input signal and the output signal.
m), and the larger the value, the better.
In order to improve gm, it is necessary to shorten the gate length. gm is represented by the degree of expansion of the depletion layer in the channel with respect to the voltage applied to the gate.
Therefore, even if the gate length is shortened, gm does not improve as the gate length is shortened because the extension of the gate length in the channel of the depletion layer must be considered.

As a countermeasure, the highly doped layer is doubled,
All the expansion of the depletion layer caused by the interface state is absorbed by the highly doped layer provided on the surface side, and the channel contributes to gm.
That is, an FET having a structure in which a current actually flows only in a deeply doped layer on the deep side has been proposed. In the FET having this structure, the design values such as the doping amount and the thickness of the channel on the surface side do not reach the channel on the side where the natural depletion layer existing in the initial state of the FET is deep, and apply an appropriate bias voltage to the gate electrode. In such a case, the optimum gm is set.

Further, an FET having a structure in which GaInP is formed on a semiconductor surface has been proposed in Japanese Patent Application No. 6-111812. However, the structure of this FET is such that GaInP is formed directly on the high-concentration doped layer, and the surface in contact with the surface protective film may be GaAs. On the other hand, the FET of the present invention is provided under the surface protective film and on the undoped layer. Ga
It forms InP and is structurally different.
Another problem to be solved by the invention is that the invention of the present application lies in the suppression of the characteristic change caused by the interface state between the surface protective film and the semiconductor surface, whereas the characteristic change in the heat treatment step during device manufacturing. Is to suppress.

[0006]

However, in the FET having the above-described structure having the cap layer, as shown in the band diagram of FIG. 6, the interface state 21 formed between the surface protective film 6 and the cap layer 4 is formed. Acts as an electron trap. For this reason, when the FET is energized for a long time or when a large current is transiently applied, electrons are trapped in the interface state, and as a result, the surface depletion layer 11a expands, the current flowing through the channel layer 3 decreases, and the time elapses. There is a problem that the characteristics are changed.

An FE having a structure in which a highly doped layer is doubled
When a current is applied for a long time or a large transient current is applied at T, these cause electrons from the channel to be formed at the interface between the surface protective film and the outermost surface which is the surface of the semiconductor. There is a problem that the design conditions of the highly doped layer, which is captured in the trap and is optimal in the initial state, are broken and the initial characteristics cannot be exhibited.

[0008]

SUMMARY OF THE INVENTION The present invention relates to a field effect transistor having a channel layer, a cap layer, a semiconductor surface protection layer, and a surface protection film having a high impurity concentration on a semiconductor substrate in that order. The region in contact with the layer is an undoped layer that is a layer not doped with impurities, and the semiconductor surface protective layer is an undoped layer formed of a material having a wider band gap than the material forming the cap layer. .

With the above configuration, the FET of the present invention has an undoped semiconductor surface protective layer having a large energy gap between the insulating surface protective film and the cap layer, so that electrons pass through this layer. Any attempt is prevented by this energy gap. Also,
In the present invention, the semiconductor surface protective layer is an undoped layer in order to suppress generation of interface states. The cap layer is an undoped layer to increase the Schottky barrier. Further, by selecting a material that hardly forms an impurity level as a material for forming the semiconductor surface protective layer, formation of an interface level is suppressed.

As a result, even when a long-term or transient large current is applied to the FET of the present invention, the number of electrons trapped by the electron trap formed in the surface protection film is significantly reduced, and the depletion layer spreads. And the characteristics are stabilized over time.

Further, the cap layer of the present invention may have a three-layer structure in which an undoped layer, a highly doped layer, and an undoped layer are formed in this order from the side in contact with the channel layer.

The present invention provides an FET having a plurality of such highly doped layers, by adding a semiconductor surface protective layer composed of an undoped layer having a band gap wider than that of the cap layer, thereby providing an interface with the protective film. Electron traps due to levels can be significantly reduced, the output signal can be suppressed from changing over time, and characteristics can be stabilized.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The embodiments of the present invention will be described below with reference to FIGS. Note that the same elements are given the same numbers, and duplicate descriptions are omitted.

(Embodiment 1) FE of the embodiment of the present invention
The cross-sectional structure of T is shown in FIG. A buffer layer 2 made of undoped GaAs is formed on a semi-insulating GaAs substrate 1 by 8
000 °, 160 ° for the channel layer 3 made of Si-doped GaAs, 400 ° for the cap layer 4 made of undoped GaAs, and 50 ° for the semiconductor surface protective layer 5 made of undoped GaInP. For example, metalorganic chemical vapor deposition (OMVPE) Method). Here, the doping amount of the channel layer was set to 2.65 × 10 18 / cm 3. The semiconductor surface protection layer 5 is covered with a surface protection film 6 made of SiN.

The ohmic electrode 12 is formed in contact with the cap layer 4. Immediately below the ohmic electrode 12, Si ions are implanted and activated at a high concentration until reaching the channel layer 3, and an n + high concentration layer 13 is formed. ing. The gate electrode 11 is also formed in contact with the cap layer 4.

FIG. 2 shows a band diagram of a region covered with the surface protective film 6 of the FET of FIG. Electron capture levels 21 are formed at the interface between the outermost semiconductor surface protection layer 5 made of GaInP and the surface protection film 6 made of SiN. The density of the electron capture levels 21 depends on the material properties of GaInP.
This is far less than when the cap layer 4 made of s is directly in contact with the surface protection film 6 made of SiN.

The probability that a current flowing through the channel layer 3 is trapped by the interface state 21 can be improved by using GaInP, which is a material having a wider energy gap than the cap layer 4, for the semiconductor surface protection layer 5. The protective layer 5 acts as a barrier and decreases. As a result, the electrons move to the interface level 21.
And the surface depletion layer 11a
Is suppressed, and a stable gm can be obtained.

(Manufacturing Method) The FET according to the present embodiment is
It can be manufactured as follows by a combination of known techniques. On a semi-insulating GaAs substrate 1, a buffer layer 2 made of GaAs as an undoped layer, a channel layer 3 doped with Si, a cap layer 4 made of GaAs,
The semiconductor surface protective layer 5 made of GaInP, which is an undoped layer, is continuously formed with the above-mentioned predetermined thickness.

Next, the surface protection film 6 made of Si
N is formed to a thickness of 800 °, and Si ions are applied to a region where the ohmic electrode 12 is formed, for example, at 130 keV.
Implantation is performed at a concentration of 4.0 × 10 13 / cm 2 to form an n + high concentration layer 13.

At this time, in order to make the n + high concentration region 13 self-aligned with the gate electrode 11, Si may be implanted after the dummy gate is manufactured. Thereafter, the surface protection film 6 made of SiN formed earlier is used as an annealing film as n +
Activate the Si ions implanted into the high concentration region 13.

Next, after patterning the ohmic electrode region with a photoresist, the SiN protective film 6 is etched and opened to expose the semiconductor surface protective layer 5 made of GaInP. Thereafter, only the semiconductor surface protection layer 5 is selectively removed by wet etching using phosphoric acid, and an opening is formed.
The aAs cap layer 4 is exposed, and an ohmic electrode 12 is formed thereon. The fabrication of the gate electrode 11 is performed in the same procedure as that for the ohmic electrode 12, thereby completing the FET.

(Embodiment 2) FIG. 3 shows a cross-sectional structure of an FET having a plurality of highly doped layers according to another embodiment of the present invention. On a semi-insulating GaAs substrate 1, Ga as an undoped layer is formed.
The buffer layer 2 made of As is 8000 °, the channel layer 3 made of GaAs doped with Si is 80 °, GaAs
The cap layers 41, 42 and 43 made of s are 900 ° and G
A semiconductor surface protection layer 5 made of aInP is continuously formed at 50 °.

Here, the GaAs cap layers 41, 42, 4
3 is different from the first embodiment in that the first undoped GaAs
Layer 41, Si-doped GaAs layer 42, undoped GaAs
s43, which is formed of three layers of undoped GaAs.
The layer 43 is the next undoped GaInP semiconductor surface protective layer 5
Is in contact with Gate electrode 11, ohmic electrode 12,
Other structures such as the surface protection film 6 are the same as those of the first embodiment. The n + high concentration layer 13 is obtained by ion-implanting and activating Si to a depth reaching the channel layer 3.

The semiconductor surface protective layer 5 according to the present invention comprises:
Particularly in the case of an FET having such a plurality of doped layers, a particularly large effect can be exhibited. That is, the cap layers 41 and 4
By using GaInP having a wider energy gap than that of 2, 43 as the semiconductor surface protective layer 5, the density itself of the interface states 21 is reduced, and the probability that electrons in the channel 3 are captured by the interface states 21 is increased. Decrease.

The FET according to the present embodiment can be manufactured according to the first embodiment. However, the cap layers 41, 42, and 43 have a three-layer structure of undoped GaAs layer / Si-doped GaAs layer / undoped GaAs layer.

In the above embodiment, the case where GaInP is lattice-matched with GaAs as the semiconductor surface protective layer 6 has been described. However, if the thickness is smaller than a critical thickness that does not cause a defect due to lattice mismatch, the composition becomes There is no limitation, and for example, AlInP, AlInGaP, and the like exhibit the same effect.

In the present invention, the case of an FET has been described. However, the present invention is not limited to the FET.
A similar effect can be obtained when applied to a HEMT which is a high mobility transistor having a structure of GaAs channel layer / undoped AlGaAs spacer layer / Si doped AlGaAs electron supply layer.

[0028]

The present invention relates to a field effect transistor (FET) using a compound semiconductor as a material, and by adding a semiconductor surface protection layer composed of an undoped layer having a band gap wider than a cap layer, a channel based on an interface state is provided. Eliminate the trapping of electrons from the layer
Of the gm, which is an important characteristic of the above, is suppressed, and stable characteristics are realized.

The present invention also relates to an FET having a plurality of highly doped layers, by adding a semiconductor surface protective layer composed of an undoped layer having a band gap wider than that of the cap layer, so that the interface state with the protective film can be improved. Can significantly reduce electron traps, suppress changes over time in gm, and stabilize characteristics.

[0030]

[Brief description of the drawings]

FIG. 1 is a diagram showing a field effect transistor according to an embodiment of the present invention.

FIG. 2 is a diagram showing a band structure of the field-effect transistor shown in FIG.

FIG. 3 is a diagram showing a field effect transistor according to another embodiment of the present invention.

FIG. 4 is a diagram showing a band structure of the field-effect transistor shown in FIG.

FIG. 5 is a diagram showing a conventional field effect transistor.

6 is a diagram showing a band structure of the field-effect transistor shown in FIG.

[Explanation of symbols]

 1: semiconductor substrate 2: buffer layer 3: channel layer 4: cap layer 41, 43: undoped layer 42: highly doped layer 5: semiconductor surface protective layer 6: surface protective film 11: gate electrode 12: ohmic electrode 13: n + high Concentration layer 21: Interface level 31: Depletion layer

Claims (6)

[Claims] 1. A field effect transistor comprising a channel layer having a high impurity concentration on a semiconductor substrate, a cap layer on the channel layer, a semiconductor surface protection layer on the cap layer, and a surface protection film on the semiconductor surface protection layer. At least a region of the cap layer in contact with the semiconductor surface protection layer is an undoped layer, and the semiconductor surface protection layer is an undoped layer formed of a material having a wider band gap than the material forming the cap layer. A field-effect transistor characterized by the above-mentioned. 2. The electric field according to claim 1, wherein the cap layer has a three-layer structure in which an undoped layer, a highly doped layer, and an undoped layer are formed in this order from the side in contact with the channel layer. Effect transistor. 3. The field effect transistor according to claim 1, wherein a material forming the semiconductor surface protection layer is GaInP. 4. The field effect transistor according to claim 1, wherein a material forming the semiconductor surface protection layer is AlInP. 5. The material for forming the cap layer is GaAs.
s.
Item 3. The field effect transistor according to item 1. 6. A material for forming the cap layer is AlG.
The field effect transistor according to claim 1, wherein the field effect transistor is aAs.