JPH10275483A - Non-volatile semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To record multivalued information or analog information at high speed with high accuracy by writing an amount a little less than the amount corresponding to the multivalued information to be stored into a memory cell transistor and repeating write and read in a short cycle later. SOLUTION: A write circuit 52 generates a write voltage (VH/VM/VL) corresponding to a 1st write period continuously for a prescribed period, performs write for the amount corresponding to write information into a memory cell transistor 40 and writes a lacked component during a following 2nd write period. During the 2nd write period, write operation based on a write clock ϕW and read operation based on a read clock ϕR from a read circuit 51 are repeated. At the time point when a discrimination circuit 53 discriminates that the read potential of bit line 42 reaches a discriminate value set corresponding to the multivalued information to be stored and inverts a discriminate signal D, the write operation and the read operation are stopped.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile semiconductor memory device capable of storing multi-value data by a memory cell transistor having a floating gate.

[0002]

2. Description of the Related Art An electrically erasable programmable ROM (EEPROM: Elmer) in which a memory cell comprises a single transistor.
(ectrically Erasable Programmable ROM)
Each memory cell is formed by a transistor having a double gate structure having a floating gate and a control gate. In such a memory cell transistor having a double gate structure, data is written by accelerating and injecting hot electrons generated on the drain region side of the floating gate into the floating gate. Then, data is read by detecting a difference in operation characteristics of the memory cell transistor depending on whether or not charge is injected into the floating gate.

FIG. 7 is a plan view of a memory cell portion of a nonvolatile semiconductor memory device having a floating gate.
FIG. 8 is a cross-sectional view taken along the line XX. This figure shows a split gate structure in which a part of the control gate is arranged side by side with the floating gate. A plurality of isolation regions 2 made of a selectively thick oxide film (LOCOS) are formed in a strip shape in a surface region of a P-type silicon substrate 1 to partition an element region. A floating gate 4 is arranged on a silicon substrate 1 with an oxide film 3 interposed between adjacent isolation regions 2.
This floating gate 4 is arranged independently for each memory cell. Also, the oxide film 5 on the floating gate 4 is formed thick at the center of the floating gate 4 and makes the end of the floating gate 4 an acute angle. This makes it easier for electric field concentration to occur at the end of the floating gate 4 during the data erasing operation. On the silicon substrate 1 on which a plurality of floating gates 4 are arranged, control gates 6 are arranged corresponding to each column of the floating gates 4. The control gate 6 is arranged so that a part thereof overlaps the floating gate 4 and the remaining part is in contact with the silicon substrate 1 via the oxide film 3. The floating gate 4 and the control gate 6 are arranged such that adjacent rows are plane-symmetric with each other. N-type first diffusion layers 7 and second diffusion layers 8 are formed in a substrate region between control gates 6 and a substrate region between floating gates 4. The first diffusion layers 7 are surrounded by the isolation regions 2 between the control gates 6 and are independent of each other.
The second diffusion layer 8 continues in the direction in which the control gate 6 extends. These floating gate 4, control gate 6, first diffusion layer 7, and second diffusion layer 8 constitute a memory cell transistor. Then, aluminum wiring 10 is arranged on control gate 6 via oxide film 9 in a direction crossing control gate 6. This aluminum wiring 10 is connected to first diffusion layer 7 through contact hole 11.

In the case of such a memory cell transistor having a double gate structure, the on-resistance between the source and the drain varies according to the amount of charge injected into the floating gate 4. Therefore, by selectively injecting charges into the floating gate 4, the on-resistance value of a specific memory cell transistor is varied stepwise, and the resulting difference in the operating characteristics of each memory cell transistor is associated with data to be stored. Like that. For example, the amount of charge injected into the floating gate 4 is set in four stages,
By reading the on-resistance value of the memory cell transistor in the same four stages, it becomes possible to store four-level (two bits) data in one memory cell transistor.

FIG. 9 is a circuit diagram of the memory cell portion shown in FIG. In this figure, memory cells are divided into 4 rows × 4
This shows a case in which they are arranged in columns. In the memory cell transistor 20 having the double gate structure, the control gate 6 is connected to the word line 21 and the first diffusion layer 7 and the second diffusion layer 8
Are connected to the bit line 22 and the source line 23, respectively. Each bit line 22 is connected to a select transistor 24
And the data line 25 is connected to the readout circuit 27 via the resistor 26. A sense amplifier (not shown) for reading a voltage value is connected to each bit line 22. Each source line 23
Are connected to a power line 28, and a writing circuit 29 is connected to the power line 28. Normally, the control gate 6 itself commonly formed by the memory cell transistors 20 is used as the word line 21 and the first diffusion layer 7
Is used as bit line 22. The second diffusion layer 8 extending in parallel with the control gate 6 is used as the source line 23.

[0006] The row selection information LS1 to LS4 are generated based on row address information.
By selecting one of these, a specific row of the memory cell transistors 20 is activated. Column selection signals CS1 to CS
Numeral 4 is generated based on the column address information, and activates a specific column of the memory cell transistors 20 by turning on one of the selection transistors 24. Thereby, one of the plurality of memory cell transistors 20 arranged in a matrix is designated according to the row address information and the column address information, and is connected to the data line 25.

When writing multi-valued information (or analog information) to the memory cell transistor 20, the injection (writing) of the charge and the confirmation (reading) of the injected amount are repeated in a short cycle in order to improve the recording accuracy. . That is, reading is performed each time while writing to the memory cell transistor 20 is performed little by little, and the writing is stopped when the read result matches the content of the data to be stored.

The write clock φW is, for example, as shown in FIG.
As shown in (1), the pulse is generated so as to rise for a certain period at a certain cycle. This write clock φW
Are the power line 28 and the source line 23 from the write circuit 29.
Is applied to the memory cell transistor 20 via At this time, the data line 25 is pulled down to the ground potential in synchronization with the write clock φW. Therefore, while the write clock φW is rising, a current flows from the source line 23 to the bit line 22 through the selected memory cell transistor 20, and this current causes charge injection into the floating gate 4.

On the other hand, the read clock φR is, for example,
As shown in FIG. 10, a pulse is generated so that a pulse rises during the gap period of the write clock φW, and the read circuit 2
7 to the memory cell transistor 20 via the resistor 26 and the bit line 22. At this time, the power line 28
Is lowered to the ground potential in synchronization with the read clock φR. Therefore, the data line 25 is connected to the power line 2 through the resistor 26 and the selected memory cell transistor 20.
8 flows to the bit line 22 according to the ratio between the on-resistance value of the memory cell transistor 20 and the resistance value of the resistor 26.
Changes. The potential at this time is read by the sense amplifier connected to the bit line 22, and the above-described write and read cycles are repeated until the result becomes a value corresponding to the information to be written.

[0010]

In the above-mentioned memory device for storing multi-valued information or analog information, writing with higher precision becomes possible as one step of the writing cycle is reduced. However, when one step is reduced, a write cycle required until the write amount of the memory cell reaches a desired level increases, which causes a problem that the write speed becomes slow.

In general, one step of the write cycle is set to be small when the storage accuracy is more important than the operation speed, and is set to be larger when the operation speed is more important than the storage accuracy. The setting of one step of the write cycle is performed according to the purpose of use of the memory device. However, since the write characteristics are not always uniform among a plurality of memory cells provided in parallel, It is difficult to set an optimal state for the setting, and the degree of freedom in setting is small.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to maintain the write operation of a memory device for recording multi-valued information or analog information at high speed and high accuracy, and to simplify the setting of operating conditions.

[0013]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and has a feature in that the present invention has an electrically independent floating gate, and stores the floating gate in the floating gate. A memory cell transistor that changes an on-resistance value in accordance with the amount of electric charge, a bit line connected to a drain side of the memory cell transistor, a source line connected to a source side of the memory cell transistor, A bit line is grounded, a constant voltage is applied to the memory cell transistor from the source line during a first writing period, and a fixed period is applied to the memory cell transistor from the source line during a second writing period. And a write circuit for applying a write clock during the second write period. A read circuit for applying a read clock having a constant peak value through a resistor having a predetermined resistance value to the bit line to ground the source line,
A write operation in the first write period is controlled according to the content of the multi-valued information to be stored, and the potential of the bit line is synchronized with a determination value corresponding to the multi-valued information in synchronization with the operation of the read circuit. And a determination circuit for comparison.

According to the present invention, an amount slightly smaller than the amount corresponding to the multi-valued information to be stored is previously written to the memory cell transistor. After that, the writing operation and the reading operation are repeated so that accurate writing is performed. Therefore, at the beginning of the write operation, the read operation for confirmation is omitted,
It supports high-speed operation.

[0015]

FIG. 1 is a circuit diagram showing a first embodiment of a nonvolatile semiconductor memory device according to the present invention. In this figure, memory cell transistors 40 are arranged in 4 rows × 1 column for simplification of the drawing. The memory cell transistor 40 has the same structure as the memory cell transistor 20 shown in FIG. 7, has a floating gate and a control gate, and changes the on-resistance value according to the amount of charge injected (stored) in the floating gate. . The word lines 41 are arranged corresponding to each column of the memory cell transistors 40, and each memory cell transistor 4
0 control gates are respectively connected. Row selection signals LS1 to LS4 supplied from a row decoder (not shown) that receives row selection information are applied to the word line 41, and one of the rows is selectively activated. The bit line 42 extends in the column direction in which the memory cell transistors 40 are arranged, and the drain side of each memory cell transistor 40 is connected. The source line 43 is arranged to extend in a direction intersecting the bit line 42, and the source side of each memory cell transistor 40 is connected. As a result, each memory cell transistor 40 is connected in parallel to the bit line 42, and receives a predetermined potential from the bit line 42 and the source line 43 for each operation of writing, reading, and erasing.

The data line 45 is connected to the bit line 42 via a column selection transistor 44 which operates in response to the column selection information LS1, and a read circuit 51 via a read load resistor 46 having a constant resistance. Connected to. The data line 45 is grounded via a switching transistor 47 that operates in response to the current control signal S0 supplied from the write circuit 52. The power line 48 is connected to each of the source lines 43 and the write circuit 5
2 is connected.

The read circuit 51 has a read clock φ.
R is generated, and a constant voltage is applied to the memory cell transistor 40 from the data line 46 and the bit line 42 via the resistor 46 at a constant cycle. This read clock φ
R is the same as the read clock φR shown in FIG.
It has a constant cycle according to the write clock φW while maintaining a constant peak value. The write circuit 52 applies a write voltage (VH) corresponding to the stored information during the first write period.
/ VM / VL) are continuously generated for a predetermined period, and a write clock φW is generated in a subsequent second write period. Write voltage or write clock φ corresponding to stored information
W is applied to the memory cell transistor 40 from the power line 48 and the source line 43. Further, the write circuit 52 generates a current control signal S0 in synchronization with the write clock φW and applies it to the switching transistor 47.

The determination circuit 53 takes in multi-value information to be stored, and in accordance with the determination of the information, determines the write voltage (VH / VM / V) in the first write period in the write circuit 52.
L). At the same time, the second
The determination value in the read operation in the gap period of the read period is set. Then, the potential of the bit line 42 is read in accordance with the operation of the read circuit 51, the potential of the bit line 42 is compared with a set determination value, and the comparison result is output as a determination signal D.

When four-level (two bits) information is stored in the memory cell transistor 40, as shown in FIG.
According to the write information of “1, 1”, “0, 1”, “1, 0”, the high voltage (VH), the medium voltage (VM), and the low voltage (VL) are respectively set in the first write period. Selected. During the first write period, the read clock φR is stopped, and only the write operation by the write clock φW is continuously performed. The length of the first writing period is set to a range in which the read potential of the bit line 42 does not exceed each determination value when the first writing period is completed.
Note that, for storing the write information “0, 0”, the write operation is unnecessary because the memory cell transistor 40 is used in the erased state.

When the first write period is completed, a second write period is started. As shown in FIG. 2, the read circuit 51 generates a read clock φR, and the write circuit 52
Generates a write clock φW and a current control signal S0 synchronized with the write clock φW. The peak value of the write clock φR at this time is set to, for example, the low potential VL. In the second write period, the write operation by the write clock φW and the read operation by the read clock φR are repeated. Then, the judgment circuit 53
Accordingly, when the read potential of the bit line 42 reaches the determination value set corresponding to the stored multilevel information and the determination signal D is inverted, the write operation and the read operation are stopped.

In the first write period, after the amount corresponding to the write information is written to the memory cell transistor 40, the shortage is written in the second write period. Therefore, the writing operation completed in the first writing period and the second writing period is completed in a substantially constant period regardless of the content of the writing information. FIG. 3 is a circuit diagram showing a second embodiment of the nonvolatile semiconductor memory device of the present invention. In this figure, a memory transistor 40, a word line 41, a bit line 42, a source line 43, a selection transistor 44, a data line 45, a read load resistor 46, and a power line 48 are the same as those in FIG. Further, the read circuit 51 and the determination circuit 53 are the same as those in FIG. 1, and the potential of the bit line 42 is compared with a determination value set in accordance with storage information every time a read operation is performed in the second write period. .

The write circuit 54 generates a constant write voltage continuously during a first write period for a period corresponding to stored information, and generates a write clock φW having a constant peak value during a subsequent second write period. I do. A constant write voltage or write clock φW is applied to the memory cell transistor 40 from the power line 48 and the source line 43 as in the case of FIG.

When four-valued (two-bit) information is stored in the memory cell transistor 40, as shown in FIG. 4, "1, 1", "0, 1",
The write clock φW is raised only during a period corresponding to each write information of “1, 0”, and a constant write voltage is applied. In the first write period, the read clock φR is stopped, and only the write operation by the write clock φW is continuously performed. The length of the rising period of the write clock φW in the first write period is
At the end of the first write period, the read potential of the bit line 42 is set to a range that does not exceed the respective determination values. The operation in the second writing period following the first writing period is the same as the writing operation shown in FIG. Note that the storage of the write information “0, 0” is used while the memory cell transistor 40 is in the erased state, as in the case of FIG.

In the first write period, after the amount corresponding to the write information is written to the memory cell transistor 40, the shortage is written in the second write period. In the first writing period, the same writing voltage as that in the second writing period is applied. However, since the reading operation for checking the writing state is omitted, writing is performed at a stroke. Therefore, the writing time is greatly reduced.

FIG. 5 is a circuit diagram showing a third embodiment of the nonvolatile semiconductor memory device of the present invention. Also in this figure, the memory transistor 40, word line 41, bit line 42, source line 43, select transistor 44, data line 45, read load resistor 46 and power line 48 are shown in FIG.
Is the same as The readout circuit 51 and the determination circuit 5
3 is the same as that of FIG. 1, and the potential of the bit line 42 is compared with a judgment value and a preliminary judgment value set corresponding to the stored information every time a read operation is performed.

The data line 45 is connected to a read circuit 51 via a read load resistor 46 having a constant resistance, and operates in response to current control signals S0, S1, S2 supplied from a write circuit 55. Grounded through the parallel switching transistors 49a, 49b, 49c. The write circuit 55 generates a constant write voltage continuously for a constant period during a first write period, and generates a write clock φW having a constant peak value during a subsequent second write period. The constant write voltage or write clock φW is applied to the power line 4 as in the case of FIG.
8 and the source line 43 are applied to the memory cell transistor 40. The write circuit 55 generates current control signals S0, S1, and S2 according to the write information,
It is supplied to the switching transistors 49a, 49b, 49c.

When four-valued (two-bit) information is stored in the memory cell transistor 40, as shown in FIG. 6, "1, 1", "0, 1",
The current control signals S0, S1, and S2 are selectively activated so as to correspond to the respective write information of "1, 0". Switching transistors 49a, 49b connected in parallel,
49c limits the current flowing from the bit line 42 to the ground side, and determines the current flowing from the source line 43 to the bit line 42 through the memory cell transistor 40, that is, the write current according to the number of turning on. Therefore,
The current control signal S corresponding to the write information of "1, 1"
When 0, S1, and S2 are all activated, a large current flows as a write current, and when only the current control signal S0 is activated corresponding to the write information of "0, 1", a small current flows as a write current. . In the first write period, the read clock φR is stopped, and only the write operation by the write clock φW is continuously performed.

In the first writing period, the writing voltage value and the current amount are set within a range in which the read potential of the bit line 42 does not exceed the respective judgment values at the time when the first writing period ends. In the operation in the second writing period following the first writing period, only the current control signal S0 rises and only the switching transistor 49a operates, the current control signals S1 and S2 are fixed, and the switching transistors 49b and 49c are turned off. Will remain. The write operation in the second write period by the switching transistor 49a and the write clock φR is the same as the write operation shown in FIG. Note that the write information “0, 0”
As in the case of FIG. 1, the memory cell transistor 40 is used in an erased state.

After the amount of writing corresponding to the write information is performed on the memory cell transistor 40 in the first writing period, the shortage is written in the second writing period. In the first writing period, the current path from the bit line 42 to the ground side is set to be large in accordance with the write information, so that the write current flows in an amount corresponding to the write information and the writing is performed. . At this time, since the reading operation for confirming the writing state is omitted, the writing is performed at a stretch. Therefore, the writing time is greatly reduced.

In the above memory device, continuous writing is performed in advance on the memory cell transistor 40. For this reason, the read potential of the bit line 42 is
In a short period of time in the writing period. Then, during the second writing period, the change slowly occurs until the desired judgment is reached. In the writing operation of the memory cell transistor 40 in the first writing period, switching of the writing voltage, switching of the writing time, and switching of the writing current can be considered, but these may be combined. .

In the above embodiment, the case where four-valued (two-bit) information is stored in the memory cell transistor 40 has been described as an example. Minutes), 16 values (4 bits) or more. In this case, the write circuits 52, 54, and 55 are configured to switch the write voltage, the write time, and the write current according to the number of stored information.

[0032]

According to the present invention, the writing speed can be increased when storing multi-valued information in the memory cell transistor. Alternatively, highly accurate writing can be performed without lowering the writing speed. Therefore, it is easy to set the write condition for the memory cell transistor, and the degree of freedom in setting the condition is expanded.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a nonvolatile semiconductor memory device of the present invention.

FIG. 2 is a waveform diagram of a write clock and a current control signal according to the first embodiment.

FIG. 3 is a circuit diagram showing a second embodiment of the nonvolatile semiconductor memory device of the present invention.

FIG. 4 is a waveform diagram of a write clock and a current control signal according to the second embodiment.

FIG. 5 is a circuit diagram showing a third embodiment of the nonvolatile semiconductor memory device of the present invention.

FIG. 6 is a waveform diagram of a write clock and a current control signal according to the third embodiment.

FIG. 7 is a plan view showing a structure of a memory cell of a conventional nonvolatile semiconductor memory device.

FIG. 8 is a sectional view taken along line XX of FIG. 7;

FIG. 9 is a circuit diagram showing a configuration of a conventional nonvolatile semiconductor memory device.

FIG. 10 is a waveform diagram of a write clock and a read clock.

[Explanation of symbols]

Reference Signs List 1 semiconductor substrate 2 isolation region 3, 5, 9 oxide film 4 floating gate 6 control gate 7 drain region 8 source region 10 aluminum wiring 11 contact hole 20, 40 memory cell transistor 21, 41 word line 22, 42 bit line 23, 43 Source line 24, 44 Selection transistor 25, 45 Data line 26, 46 Read load resistance 27, 51 Read circuit 28, 48 Power line 29, 52, 54, 55 Write circuit 47, 49a, 49b, 49c Switching transistor 53 Judgment circuit

Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 29/792

Claims (4)

[Claims] 1. A memory cell transistor having an electrically independent floating gate and changing an on-resistance value according to the amount of electric charge stored in the floating gate, and a memory cell transistor connected to a drain side of the memory cell transistor. And a source line connected to the source side of the memory cell transistor, and the bit line are grounded, and a constant voltage is applied to the memory cell transistor from the source line during a first writing period. A write circuit for applying a write clock from the source line to the memory cell transistor at a constant period in a second write period; and a write circuit for applying a write clock during the second write period and within a gap period of the write clock. The source line is grounded and the bit line has a constant peak value via a resistor having a predetermined resistance value A read circuit that applies a read clock, and controls a write operation in the first write period according to the content of the multi-valued information to be stored, and adjusts the potential of the bit line in synchronization with the operation of the read circuit. A judgment circuit for comparing with a judgment value corresponding to the multi-value information;
A nonvolatile semiconductor memory device comprising: 2. The non-volatile memory according to claim 1, wherein the write circuit variably sets the peak value of the write clock during the first write period according to the content of the multi-valued information to be stored. Semiconductor memory device. 3. The non-volatile semiconductor memory device according to claim 1, wherein the write circuit expands and contracts the length of the first write period in accordance with the content of the multi-valued information to be stored. . 4. The writing circuit includes a current limiting circuit for limiting at least stepwise a current flowing from the bit line to the ground when the bit line is grounded, and the current limiting circuit stores the content of the multi-valued information. 2. The nonvolatile semiconductor memory device according to claim 1, wherein a current is limited during the first writing period.