JP2009016858A - Semiconductor storage device, writing method thereof, and storage medium with writing method stored therein - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress a deterioration in a memory cell due to overcurrent in a multivalued semiconductor storage device capable of storing ternary or more storage states. <P>SOLUTION: A current control circuit 8 generates three types of different stationary currents I1 to I3 and applies at least one current value selected among the three types of different current values to one of selected memory cells 10 to 13 in accordance with a data signal from the outside. Consequently, overcurrent is inhibited from flowing into the memory cells, and a multivalued memory cell is achieved which can store ternary or more information in one memory cell by making the different current values correspond to three types of different thresholds. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device capable of storing data, and more particularly to a multi-value type semiconductor memory device capable of storing a storage state of three or more values, a writing method thereof, and a storage medium storing a writing method. is there.

  Currently, semiconductor memory devices in practical use only give two memory states “0” and “1” to one memory cell. Therefore, the memory capacity of one memory cell is 1 bit (= 2). On the other hand, four types of storage information (“00”, “01”, “10”, “11”) are given to one memory cell, and four data corresponding to each storage information are provided. A semiconductor memory device has been proposed in which memory is held by a threshold voltage, for example, (1V, 2V, 3V, 4V), that is, one memory cell has a storage capacity of 2 bits (= 4 values).

  An example of the above-described multi-value type semiconductor memory device is described in, for example, Japanese Patent Laid-Open No. 6-195987.

  In Japanese Patent Laid-Open No. 6-195987, when the four types of stored information described above are given, the stored information is associated with the four types of voltage values, and any one of the four types of voltage values is stored. A method of applying data to a memory cell for writing data is described.

  A method is also described in which these stored information is made to correspond to four types of signals having different time widths, and any one of these signals is applied to a memory cell for writing data.

  However, in the method described in Japanese Patent Laid-Open No. 6-195987, when the storage state written in one memory cell is varied by different voltage values, the memory cell is directly connected, particularly in the initial state where a voltage is applied. This voltage is applied.

  When a constant voltage is applied to the memory cell, a current corresponding to the voltage value flows directly to the memory cell. Here, electrons are injected from the drain through the tunnel oxide film to the floating gate due to the potential difference between the drain of the memory cell and the control gate. The tunnel oxide film is damaged by the electrons.

  As a result, the threshold value of the memory cell fluctuates, which makes it difficult to maintain a predetermined storage state, or when the damage of the tunnel oxide film is large, the memory cell itself may be destroyed. It was.

  The present invention has been made to solve such a problem. In a multi-value type semiconductor memory device capable of storing a storage state of three or more values, the deterioration of the memory cell due to overcurrent is suppressed. Another object of the present invention is to provide a semiconductor memory device with improved reliability.

  The semiconductor memory device of the present invention has at least three different types of memory cells including a charge storage layer, a control gate electrode formed on the charge storage layer via an insulating film, and a source / drain. Write control means for writing multi-value data corresponding to one threshold value selected from the threshold value into the memory cell, and the write control means is a current for controlling at least three different current values. And a control means for controlling a current value flowing through at least one of the drain and the control gate electrode by the current control means.

  In one embodiment of the semiconductor memory device of the present invention, the current control means is a control means for maintaining the current value at a predetermined constant value.

  In one embodiment of the semiconductor memory device of the present invention, the threshold value is set large according to the magnitude of the current value controlled by the current control means.

  According to another aspect of the present invention, there is provided a method of writing a semiconductor memory device including at least three types of memory cells each including at least a charge storage layer, a control gate electrode formed on the charge storage layer via an insulating film, and a source / drain. A first step of selecting one current value from current values controlled to at least three predetermined values, and at least the drain of the memory cell or the And a second step of passing the selected current value to one of the control gate electrodes.

  In one aspect of the writing method of the semiconductor memory device of the present invention, the current values controlled to the at least three predetermined values are determined based on different levels of threshold voltages of the memory cells.

  In the storage medium of the present invention, the first and second steps constituting the writing method of the semiconductor storage device are stored so as to be readable from a computer.

  A semiconductor device of the present invention is formed on a first insulating layer formed on a semiconductor substrate, a gate electrode formed on the first insulating layer, and one of the semiconductor substrates on one side of the gate electrode. The first conductive region formed, the second conductive region formed on the other semiconductor substrate on one side of the gate electrode, a current generation circuit capable of varying a current value in multiple stages, and the current Current generating means for controlling a value of a current flowing in one of the first and second conductive regions by a generation circuit;

  In one embodiment of the semiconductor device of the present invention, a lower electrode connected to one of the first and second conductive regions, a dielectric layer formed on the lower electrode, An upper electrode formed on the dielectric layer, and the lower electrode, the dielectric layer, and the upper electrode function as a capacitor.

  In one embodiment of the semiconductor device of the present invention, the first conductive region functions as a source, the second conductive region functions as a drain, and the current control means has a current value flowing through the drain. Current control means for controlling the charge storage layer, wherein the gate electrode functions as a charge storage layer, a control gate electrode formed on the charge storage layer via a second insulating layer, and a charge in the charge storage layer Charge storage means for introducing the.

  In one embodiment of the semiconductor device of the present invention, the semiconductor device is a multi-value semiconductor memory device capable of storing a storage state of three or more values.

  In one embodiment of the semiconductor device of the present invention, the charge storage means is selected from at least three different threshold values by the charge amount adjusting means for changing the charge amount in multiple stages and the charge amount adjusting means. Charge introduction means for introducing data corresponding to one threshold value into the charge storage layer as a charge amount.

  In one embodiment of the semiconductor device of the present invention, the current control means has variable resistance means having a function capable of changing the resistance value.

  In one aspect of the semiconductor device of the present invention, the current generating circuit includes means for varying the current value based on a predetermined data value.

[Action]
In the present invention, at least three kinds of current values controlled to a predetermined value by the current control means are generated, and one current value selected from these current values is applied to the memory cell. Since the upper limit value of each current value applied to the memory cell is reliably controlled to a current value that the memory cell can withstand, a write operation can be performed without applying an overcurrent to the memory cell. . In addition, in the present invention, by preparing at least three kinds of these controlled current values, the current value is made to correspond to each of the threshold values of the multi-value memory cell, and the multi-value information is stored in one memory cell. It becomes possible to memorize.

  According to the present invention, in a multi-value type semiconductor memory device capable of storing a storage state of three or more values, it is possible to suppress deterioration of memory cells due to overcurrent. Accordingly, it is possible to provide a multi-value type semiconductor memory device with improved reliability.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a plan view showing a part of an EEPROM memory cell array which is a nonvolatile semiconductor memory device according to an embodiment of the present invention. FIG. 2 is a block diagram showing the main configuration of the EEPROM of this embodiment. FIG. 3 is a schematic sectional view showing one memory cell of the EEPROM formed on the silicon semiconductor substrate.

  In FIG. 1, the memory cells 10 to 13 have a floating gate 106. The word line 20 is connected to the control gates of the memory cells 10 and 11, and the word line 21 is connected to the control gates of the memory cells 12 and 13, respectively.

  However, actually, each word line and each control gate are integrally formed of, for example, polysilicon, and the word line itself constitutes the control gate in the area of each memory cell. .

  On the other hand, bit lines 22 are connected to the drains of the memory cells 10 and 12, respectively, and bit lines 23 are connected to the drains of the memory cells 11 and 13, respectively. Further, the sources of the memory cells 10 to 13 are connected to a common source line 109.

  FIG. 2 shows the main configuration of the EEPROM of this embodiment.

  Word lines 20, 21 connected to the control gates of the memory cells 10-13 are connected to the column decoder 2, while bit lines 22, connected to the drains of the memory cells 10-13. 23 is connected to the row decoder 3 via the row selector 4.

  The address signal input through the address buffer 5 is sent to these decoders 2 and 3, and the word lines and bit lines are selected by these decoders 2 and 3, respectively.

  As shown in FIG. 3, each of the memory cells 10 to 13 has phosphorous (P) or phosphorus (P) on the surface region of the element active region 102 defined by the element isolation structure such as a field oxide film on the p-type silicon semiconductor substrate 101. A tunnel oxide film 105 is formed on a source region 103 and a drain 104 which are a pair of impurity diffusion layers formed by ion implantation of an n-type impurity such as arsenic (As), and a channel region C between the source 103 and the drain 104. An isolated island-shaped floating gate 106 patterned through a dielectric gate 107 and a control gate 108 capacitively coupled to the floating gate 106 patterned through a dielectric film 107 made of an ONO film or the like. It is configured.

  In FIG. 2, the voltage from the write voltage generation circuit 6 is applied to the drain 104 or the control gate 108 of each of the memory cells 10 to 13 through the current control circuit 8 to the memory cell selected by the row decoder 3. Is done. Here, the current flowing into the drain 104 or the control gate 108 is controlled by the current control circuit 8 to determine the upper limit value.

  FIG. 4 is a characteristic diagram schematically showing each current value controlled by the current control circuit 8. In FIG. 4, the vertical axis indicates the current value, and the horizontal axis indicates time. The current control circuit 8 can set four kinds of current values by controlling the voltage from the write voltage generation circuit 6. In FIG. 4, I1, I2, I3, and I4 indicate the set current values. A curve indicated by a dotted line indicates a change in current when a voltage from the write voltage control circuit 6 is directly applied to the drain 104 of the memory cell without passing through the current control circuit 8.

  By applying one current value selected from these four types of current values to the selected memory cell, data is written into the memory cell. That is, a current value selected from these four kinds of current values according to an external data signal flows to the drain 104 of the memory cell, and the charge accumulated in the floating gate 106 passes through the tunnel oxide film 105. Passed and pulled out.

  As shown in FIG. 4, the current values I1 to I4 controlled to a constant current asymptotically reach the predetermined currents I1 'to I4' when a predetermined time elapses. T0 shown in FIG. 4 indicates a predetermined write time. The current is stopped when the time t0 elapses after the current of any of I1 to I4 is passed through the memory cell. Thereby, the write operation is completed.

  In FIG. 4, the curves from the current values I1 to I4 to I1 'to I4' are different from each other between the drain 104 of the memory cell and the substrate potential (V0) as shown in FIG. This is because a band-to-band tunneling current I0 corresponding to

  The band-to-band tunneling current I 0 decreases as the writing of the memory cell proceeds and the potential of the floating gate 106 rises with respect to the silicon semiconductor substrate 101. Therefore, when the supply current is different and the writing speed is different, the decreasing tendency of the band-to-band tunnel current I0 is different.

  As described above, the EEPROM according to the present embodiment causes four values (1 V, 2 V, 3 V, and 4 V) as shown in FIG. 5 by flowing one current value selected from the constant currents I1 to I4 to the memory cell. The storage information corresponding to each of the threshold values can be stored. The magnitude of each threshold value corresponds to each of the current values I1 to I4, and the amount of charge drawn from the floating gate 106 increases as the current value increases, so that the threshold value of the memory cell is set to be small. Will be.

  FIG. 6 shows a specific configuration of the current control circuit 8 shown in FIG. The current control circuit 8 includes four types of load transistors (Tr1 to Tr4) having different threshold values as shown in FIG. 6A and electric resistances having four types of different resistance values as shown in FIG. 6B. (R1 to R4) or load means 8b comprising capacitors (C1 to C4), electric resistances (r1 to r4) and a diode as shown in FIG. 6C.

  As shown in FIG. 6A, the present invention includes a transistor Tr1 (corresponding to I1) having a first threshold value and a second threshold value different from the first threshold value. Transistor Tr2 (corresponding to I2), transistor Tr3 (corresponding to I3) having a third threshold different from the first and second thresholds, first, second, and third thresholds Has been described using a transistor Tr4 (corresponding to I4) having a different fourth threshold value, but a multi-value nonvolatile memory capable of setting at least three different threshold values may be used instead. .

  This multi-value nonvolatile memory cell has the configuration shown in FIG. 3 and has a predetermined threshold value depending on the amount of charge introduced into the floating gate electrode. In this memory, the threshold value is set as it is unless it is electrically erased. Also, if you want to set (change) a new threshold value, electrically erase the charge introduced to the floating gate, then change the amount of charge on this floating gate and set it to a new threshold value. Is possible. In other words, this memory is a memory that can be set to a plurality of threshold values by changing the amount of charge of the floating gate electrode in multiple stages.

  As described above, the load means 8b has four stages of loads for setting four kinds of current values I1, I2, I3 and I4, and the selection means 8a selects one of these loads. It is possible.

  Next, a method for using the EEPROM of this embodiment will be described. First, a writing method using this EEPROM will be described. At the time of writing, according to the address signal from the address buffer 5, after selecting any one of the memory cells 10 to 13 by the column decoder 2 and the row decoder 3, the binary data string from the input / output circuit 9 is used as the storage information. As shown in FIG. 2, the selected memory cell is written.

  First, when the storage information “11” is written, a predetermined voltage is applied to the control gate 108 of the memory cell, the source 103 is opened, and the drain 104 is set to the ground potential. At this time, the current flowing through the drain 104 is passed through one of the four-stage load means 8b in FIGS. 6A to 6C, and the value of the current flowing through the drain 104 is made steady as shown in FIG. Control to current I4. At this time, electrons are sufficiently injected from the drain 104 to the floating gate 106, and the threshold voltage of the memory cell becomes about 4V. This storage state is assumed to be “11”.

  Next, when the memory information “10” is written, the control gate 108 of the memory cell is set to the ground potential, the source 103 is opened, and a predetermined voltage is applied to the drain 104 from the write voltage control circuit. At this time, the current flowing through the drain 104 is passed through one of the four-stage load means 8b in FIGS. 6A to 6C, and the value of the current flowing through the drain 104 is made steady as shown in FIG. Control to current I1.

  At this time, electrons are extracted from the floating gate 106 through the tunnel oxide film 105, and the threshold voltage (VT) is shifted. The threshold voltage of the memory cell is about 3V. This storage state is assumed to be “10”.

  Next, when the storage information “01” is written, the control gate 108 of the memory cell is set to the ground potential, the source 103 is opened, and a predetermined voltage is applied to the drain 108. At this time, the current flowing through the drain 104 is passed through one of the four-stage load means 8b in FIGS. 6A to 6C, and the value of the current flowing through the drain 104 is made steady as shown in FIG. Control to current I2. At this time, electrons are extracted from the floating gate 106 through the tunnel oxide film 105, and the threshold voltage of the memory cell becomes about 2V. This storage state is assumed to be “01”.

  Next, when the memory information “00” is written, the control gate 108 of the memory cell is set to the ground potential, the source 103 is opened, and a predetermined voltage is applied to the drain 104. At this time, the current flowing through the drain 104 is passed through one of the four-stage load means 8b in FIGS. 6A to 6C, and the value of the current flowing through the drain 104 is made steady as shown in FIG. Control to current I3. At this time, electrons are extracted from the floating gate 106 through the tunnel oxide film 105, and the threshold voltage of the memory cell becomes about 1V. This storage state is set to “00”.

  Therefore, in this EEPROM writing method, any one of “00”, “01”, “10”, and “11” is selected by recognizing the threshold and selecting one of the constant currents I1 to I4. Data can be written. Further, writing may be performed by applying the constant currents I1 to I4 to the control gate 108 with the drain 104 as the ground potential. In this case, the amount of charge accumulated in the floating gate 106 increases according to the magnitudes of the current values I1 to I4, so that the threshold value increases with the current values I1 to I4.

  Next, a reading method using this EEPROM will be described. At the time of reading, after selecting one of the memory cells 10 to 13, for example, the memory cell 11 by the column decoder 2 and the row decoder 3 in accordance with the address signal from the address buffer 5, reading from the memory cell 11 is performed as shown below. Perform the action. FIG. 7 is a flowchart showing each step of the read operation.

  As shown in FIG. 5, the storage information read from the selected memory cell 11 has four peaks (four values) with threshold voltages (VT) of about 1V, about 2V, about 3V and about 4V. Show the distribution. In FIG. 5, when the threshold voltage VT is detected in the range indicated by R1, the storage state is "00", and when the threshold voltage VT is detected in the range indicated by R2. The storage state is “01”. When the threshold voltage VT is detected in the range indicated by R3, the storage state is "10", and when the threshold voltage VT is detected in the range indicated by R4, the storage state is indicated. “11”.

  Therefore, first, whether the storage state is “R1 or R2” or “R3 or R4”, that is, whether the upper bit of the storage information stored in the memory cell 11 is “0” or “1”. Whether or not there is is determined using the transistor Tr1. In this case, as shown in FIG. 7, about 5 V is applied to the source 3 and drain 4 and the gate electrode 6 (step S1), the drain current is detected by the sense amplifier 21, and the threshold voltage VT and the transistor Tr1 are adjusted. The magnitude relationship with the threshold voltage is determined (step S2). At this time, when the threshold voltage VT is larger than the threshold voltage of the transistor Tr1, that is, when the current of the transistor Tr1 is larger than the current flowing through the channel region C of the memory cell, the upper bit is “1”. If the threshold voltage VT is smaller than the threshold voltage of the transistor Tr1, that is, if the current flowing through the memory cell 11 is larger than the current flowing through the transistor Tr1, it is determined that the upper bit is “0”. Thus, it is output from the output terminal D1 as the upper bits of the stored information prior to the lower bits (steps S3 and S4).

  Next, when the threshold voltage VT is larger than the threshold voltage of the transistor Tr1, a similar read operation is performed using the transistor Tr2, and the current flowing through the memory cell 11 is compared with the current flowing through the transistor Tr2 (step S5). ) If the threshold voltage VT is lower than the threshold voltage of the transistor Tr1, a similar read operation is determined using the transistor Tr3 (step S6).

  In step S5, if the threshold voltage VT is larger than the threshold voltage of the transistor Tr1 and the threshold voltage VT is larger than the threshold voltage of the transistor Tr2 in the above read operation, the threshold voltage VT is stored in the memory cell 11. The lower bit of the stored information is determined to be “1” and is output from the output terminal D0 (step S7). Therefore, in this case, the storage information read from the memory cell 11 is “11”.

  On the other hand, if the threshold voltage VT is smaller than the threshold voltage of the transistor Tr2 in step S5, it is determined that the stored information stored in the memory cell 11 is "10" and is output from the output terminal D0. (Step S8). Therefore, in this case, the storage information read from the memory cell 11 is “10”.

  In step S6, if the threshold voltage VT is smaller than the threshold voltage of the transistor Tr1, that is, if the current of the memory cell 11 is larger than the current of the transistor Tr1, the threshold voltage of the transistor Tr3 is next. If the threshold voltage of the memory cell 11 is large, the lower bit is determined to be “1” and is output from the output terminal D0 as the lower bit of the stored information (step S9). Therefore, in this case, the storage information read from the memory cell 11 is “01”.

  On the other hand, if the threshold voltage VT is smaller than the threshold voltage of the transistor Tr1 in the above read operation, that is, if the current of the memory cell 11 is larger than the current of the transistor Tr1, the threshold of the transistor Tr3 is next. If the threshold voltage of the memory cell is smaller than the voltage, the lower bit is determined to be “0” and output from the output terminal D0 as the lower bit of the stored information (step S10). Therefore, in this case, the storage information read from the memory cell 11 is “00”.

  In this embodiment, the case where the stored information is quaternary (2 bits) has been described, but the present invention is not limited to this. For example, when the storage state is 3 bits (8 values), eight threshold voltages are stored in the storage states “000”, “001”, “010”, “011”, “100”, “101”, “ 110 ”and“ 111 ”are associated with each other, and at the time of reading, one storage state may be specified from the eight types by a predetermined determination operation. Further, when the storage information is not binary data but information composed of 0, 1, 2 for example, the storage state is set to “0”, “1”, “2”, “00”, “01”, “02”, “10”, “11”, “12”, “20”, “21”, “22” can also be used. In such a case, the former will express the memory state as three values, and the latter as nine values.

  As described above, in the present embodiment, four types of current values I1 to I4 controlled to a predetermined value by the current control circuit 8 are generated, and one current value selected from these current values is stored in the memory cell 10. Apply to one of ~ 13. Since the upper limit value of each current value applied to the memory cells 10 to 13 is reliably controlled to a current value that the memory cells 10 to 13 can withstand, an overcurrent is not applied to the memory cells 10 to 13. A write operation can be performed.

  Further, in the present embodiment, by preparing at least three types of these controlled current values, each of the threshold values of the multilevel memory cell capable of storing binary (= 1 bit) or more data is provided. It is possible to store multi-value information in one memory cell in correspondence with current values.

  Further, the present invention is not limited to the EEPROM, and includes, for example, a memory capacitor for storing signal charges and an access transistor for selecting the memory capacitor. The memory capacitor has a predetermined reference. The present invention is also applicable to a multi-value type DRAM that is a volatile memory that sets a charge accumulation state by applying a voltage and stores stored information corresponding to a reference voltage.

For example, a multi-value DRAM has a configuration as shown in FIG.
By selectively forming a field oxide film 202 (element isolation insulating structure) on the surface of the p-type silicon substrate 201, a plurality of transistor formation regions are partitioned in a predetermined region where a memory cell array is formed. .

  A gate oxide film 203 formed on the surface of the p-type silicon substrate 201 in the transistor formation region, a word electrode 204 traversing the transistor formation region, and a pair of n + -type diffusion layers (source / drain) 205 on both sides of the word electrode 204 With. Also, a first interlayer insulating film 206 formed on the p-type silicon substrate 201 and an upper portion of one of the n + -type diffusion layers 205 on both sides of the first word electrode 204 formed on the first interlayer insulating film 206. The stack polysilicon film 207 (first conductive film) formed in and near the first contact hole portion, and the capacitance formed on the stack polysilicon film 207, respectively. An insulating film 208 and a capacitive polysilicon film 209 (counter electrode) are formed. Furthermore, the second interlayer insulating film 210 and the third interlayer insulating film 211 (BPSG film) formed on the p-type silicon substrate 201 and the first, second, and third interlayer insulating films 206, 210, and 211 are formed. The second contact hole (bit line contact hole) C2 is formed, and the bit line 212 made of tungsten silicide or the like is formed in the contact hole C2. Further, this multi-value can be applied not only to EEPROM and DRAM but also to various other semiconductor memories.

  Further, the program code itself for operating various devices and the program code for supplying the computer to the computer so as to realize the functions of the writing method and the reading method described in the present embodiment, and in particular, the memory erasing method. Means, for example, the storage medium 31 shown in FIG. 2 storing such program code belongs to the category of the present invention.

  The storage medium 31 causes the storage / reproduction device 32 to read out the program code stored therein and operate the computer. As a storage medium for storing the program code, for example, a floppy (registered trademark) disk, a hard disk, an optical disk, a magneto-optical disk, a CD-ROM, a magnetic tape, a nonvolatile memory card, a ROM, or the like can be used.

  Further, by executing the program code supplied by the computer, not only the functions of the above-described embodiments are realized, but also the OS (operating system) or other application software in which the program code is running on the computer, etc. Such a program code is also included in the present invention even when the functions of the above-described embodiment are realized together.

  Further, after the supplied program code is stored in the memory provided in the function expansion board of the computer or the function expansion unit connected to the computer, the CPU provided in the function expansion board or function expansion unit based on the instruction of the program code A system in which the functions of the above-described embodiment are realized by performing part or all of the actual processing and the like is also included in the present invention.

1 is a circuit diagram showing a part of an EEPROM memory cell array according to an embodiment of the present invention; FIG. It is a block diagram which shows the main structures of EEPROM which concerns on one Embodiment of this invention. 1 is a schematic cross-sectional view showing an EEPROM memory cell according to an embodiment of the present invention. It is a characteristic view which shows the electric current value which flows into the memory cell of EEPROM which concerns on one Embodiment of this invention. In the EEPROM which concerns on one Embodiment of this invention, it is a characteristic view which shows distribution of a threshold voltage. It is a schematic diagram which shows the current control circuit of EEPROM which concerns on one Embodiment of this invention. 4 is a flowchart showing steps in reading four-level stored information from an EEPROM according to an embodiment of the present invention. It is a schematic sectional drawing which shows the multi-value DRAM which concerns on the modification of one Embodiment of this invention.

Explanation of symbols

2 column decoder 3 row decoder 4 row selector 5 address buffer 6 write voltage generation circuit 8 current control circuit 8a selection means 8b load means 9 input / output circuit 10, 11, 12, 13 memory cell 20, 21 word line 22, 23 bit line DESCRIPTION OF SYMBOLS 31 Storage medium 32 Storage / reproducing apparatus 101 Silicon semiconductor substrate 102 Element active region 103 Source 104 Drain 105 Tunnel oxide film 106 Floating gate 107 Dielectric film 108 Control gate 109 Source line

Claims (6)

A first insulating layer formed on a semiconductor substrate;
A gate electrode formed on the first insulating layer;
A first conductive region formed on one of the semiconductor substrates on one side of the gate electrode;
A second conductive region formed on the other semiconductor substrate on one side of the gate electrode;
Current control means configured to provide a plurality of predetermined current values during a write operation, and
The current control means is further configured to apply one of the plurality of predetermined current values to one of the gate electrode and the conductive region for a predetermined time according to each of a plurality of input data. The semiconductor device characterized by the above-mentioned. A lower electrode connected to one of the first and second conductive regions, a dielectric layer formed on the lower electrode, and an upper electrode formed on the dielectric layer Prepared,
The semiconductor device according to claim 1, wherein the lower electrode, the dielectric layer, and the upper electrode function as a capacitor. The first conductive region functions as a source, the second conductive region functions as a drain, and the current control unit is a current control unit that controls a current value flowing through the drain,
The gate electrode functions as a charge storage layer;
A control gate electrode formed on the charge storage layer via a second insulating layer;
Charge storage means for introducing charge into the charge storage layer;
The semiconductor device according to claim 1, further comprising:   4. The semiconductor device according to claim 2, wherein the semiconductor device is a multi-value semiconductor memory device capable of storing a storage state of three or more values. The charge storage means;
Charge amount adjusting means for changing the charge amount in multiple stages;
Charge introduction means for introducing data corresponding to one threshold value selected from at least three different threshold values into the charge storage layer as a charge amount by the charge amount adjustment means;
The semiconductor device according to claim 3, further comprising: The semiconductor device according to claim 1, wherein the current control unit includes a variable resistance unit having a function capable of varying a resistance value.

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